cpu: Turn the stage 2 ARM MMUs from params to children.
[gem5.git] / src / cpu / minor / trace.hh
1 /*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40 /**
41 * @file
42 *
43 * This file contains miscellaneous classes and functions for formatting
44 * general trace information and also MinorTrace information.
45 *
46 * MinorTrace is this model's cycle-by-cycle trace information for use by
47 * minorview.
48 */
49
50 #ifndef __CPU_MINOR_TRACE_HH__
51 #define __CPU_MINOR_TRACE_HH__
52
53 #include <string>
54
55 #include "base/trace.hh"
56 #include "debug/MinorTrace.hh"
57
58 namespace Minor
59 {
60
61 /** DPRINTFN for MinorTrace reporting */
62 #define MINORTRACE(...) \
63 DPRINTF(MinorTrace, "MinorTrace: " __VA_ARGS__)
64
65 /** DPRINTFN for MinorTrace MinorInst line reporting */
66 #define MINORINST(sim_object, ...) \
67 DPRINTFS(MinorTrace, (sim_object), "MinorInst: " __VA_ARGS__)
68
69 /** DPRINTFN for MinorTrace MinorLine line reporting */
70 #define MINORLINE(sim_object, ...) \
71 DPRINTFS(MinorTrace, (sim_object), "MinorLine: " __VA_ARGS__)
72
73 }
74
75 #endif /* __CPU_MINOR_TRACE_HH__ */