src/cpu/nativetrace.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_NATIVETRACE_HH__
  33 #define __CPU_NATIVETRACE_HH__
  34
  35 #include "arch/x86/floatregs.hh"
  36 #include "arch/x86/intregs.hh"
  37 #include "base/trace.hh"
  38 #include "base/types.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "sim/insttracer.hh"
  41
  42 class ThreadContext;
  43
  44 namespace Trace {
  45
  46 class NativeTrace;
  47
  48 class NativeTraceRecord : public InstRecord
  49 {
  50   protected:
  51     NativeTrace * parent;
  52
  53   public:
  54     NativeTraceRecord(NativeTrace * _parent,
  55                Tick _when, ThreadContext *_thread,
  56                const StaticInstPtr _staticInst, Addr _pc, bool spec,
  57                const StaticInstPtr _macroStaticInst = NULL, MicroPC _upc = 0)
  58         : InstRecord(_when, _thread, _staticInst, _pc, spec,
  59                 _macroStaticInst, _upc),
  60         parent(_parent)
  61     {
  62     }
  63
  64     void dump();
  65 };
  66
  67 class NativeTrace : public InstTracer
  68 {
  69   protected:
  70     int fd;
  71
  72     ListenSocket native_listener;
  73
  74     bool checkRcx;
  75     bool checkR11;
  76     uint64_t oldRcxVal, oldR11Val;
  77     uint64_t oldRealRcxVal, oldRealR11Val;
  78
  79     struct ThreadState {
  80         uint64_t rax;
  81         uint64_t rcx;
  82         uint64_t rdx;
  83         uint64_t rbx;
  84         uint64_t rsp;
  85         uint64_t rbp;
  86         uint64_t rsi;
  87         uint64_t rdi;
  88         uint64_t r8;
  89         uint64_t r9;
  90         uint64_t r10;
  91         uint64_t r11;
  92         uint64_t r12;
  93         uint64_t r13;
  94         uint64_t r14;
  95         uint64_t r15;
  96         uint64_t rip;
  97         //This should be expanded to 16 if x87 registers are considered
  98         uint64_t mmx[8];
  99         uint64_t xmm[32];
 100
 101         void update(int fd)
 102         {
 103             int bytesLeft = sizeof(ThreadState);
 104             int bytesRead = 0;
 105             do
 106             {
 107                 int res = read(fd, ((char *)this) + bytesRead, bytesLeft);
 108                 if(res < 0)
 109                     panic("Read call failed! %s\n", strerror(errno));
 110                 bytesLeft -= res;
 111                 bytesRead += res;
 112             } while(bytesLeft);
 113             rax = TheISA::gtoh(rax);
 114             rcx = TheISA::gtoh(rcx);
 115             rdx = TheISA::gtoh(rdx);
 116             rbx = TheISA::gtoh(rbx);
 117             rsp = TheISA::gtoh(rsp);
 118             rbp = TheISA::gtoh(rbp);
 119             rsi = TheISA::gtoh(rsi);
 120             rdi = TheISA::gtoh(rdi);
 121             r8 = TheISA::gtoh(r8);
 122             r9 = TheISA::gtoh(r9);
 123             r10 = TheISA::gtoh(r10);
 124             r11 = TheISA::gtoh(r11);
 125             r12 = TheISA::gtoh(r12);
 126             r13 = TheISA::gtoh(r13);
 127             r14 = TheISA::gtoh(r14);
 128             r15 = TheISA::gtoh(r15);
 129             rip = TheISA::gtoh(rip);
 130             //This should be expanded if x87 registers are considered
 131             for (int i = 0; i < 8; i++)
 132                 mmx[i] = TheISA::gtoh(mmx[i]);
 133             for (int i = 0; i < 32; i++)
 134                 xmm[i] = TheISA::gtoh(xmm[i]);
 135         }
 136
 137         void update(ThreadContext * tc)
 138         {
 139             rax = tc->readIntReg(X86ISA::INTREG_RAX);
 140             rcx = tc->readIntReg(X86ISA::INTREG_RCX);
 141             rdx = tc->readIntReg(X86ISA::INTREG_RDX);
 142             rbx = tc->readIntReg(X86ISA::INTREG_RBX);
 143             rsp = tc->readIntReg(X86ISA::INTREG_RSP);
 144             rbp = tc->readIntReg(X86ISA::INTREG_RBP);
 145             rsi = tc->readIntReg(X86ISA::INTREG_RSI);
 146             rdi = tc->readIntReg(X86ISA::INTREG_RDI);
 147             r8 = tc->readIntReg(X86ISA::INTREG_R8);
 148             r9 = tc->readIntReg(X86ISA::INTREG_R9);
 149             r10 = tc->readIntReg(X86ISA::INTREG_R10);
 150             r11 = tc->readIntReg(X86ISA::INTREG_R11);
 151             r12 = tc->readIntReg(X86ISA::INTREG_R12);
 152             r13 = tc->readIntReg(X86ISA::INTREG_R13);
 153             r14 = tc->readIntReg(X86ISA::INTREG_R14);
 154             r15 = tc->readIntReg(X86ISA::INTREG_R15);
 155             rip = tc->readNextPC();
 156             //This should be expanded if x87 registers are considered
 157             for (int i = 0; i < 8; i++)
 158                 mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
 159             for (int i = 0; i < 32; i++)
 160                 xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
 161         }
 162
 163     };
 164
 165     ThreadState nState;
 166     ThreadState mState;
 167
 168
 169   public:
 170
 171     template<class T>
 172     bool
 173     checkReg(const char * regName, T &val, T &realVal)
 174     {
 175         if(val != realVal)
 176         {
 177             DPRINTFN("Register %s should be %#x but is %#x.\n",
 178                     regName, realVal, val);
 179             return false;
 180         }
 181         return true;
 182     }
 183
 184     bool
 185     checkRcxReg(const char * regName, uint64_t &, uint64_t &);
 186
 187     bool
 188     checkR11Reg(const char * regName, uint64_t &, uint64_t &);
 189
 190     bool
 191     checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
 192
 193     NativeTrace(const Params *p);
 194
 195     NativeTraceRecord *
 196     getInstRecord(Tick when, ThreadContext *tc,
 197             const StaticInstPtr staticInst, Addr pc,
 198             const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0)
 199     {
 200         if (tc->misspeculating())
 201             return NULL;
 202
 203         return new NativeTraceRecord(this, when, tc,
 204                 staticInst, pc, tc->misspeculating(), macroStaticInst, upc);
 205     }
 206
 207     void
 208     check(ThreadContext *, bool syscall);
 209
 210     friend class NativeTraceRecord;
 211 };
 212
 213 /* namespace Trace */ }
 214
 215 #endif // __CPU_NATIVETRACE_HH__