src/cpu/o3/FuncUnitConfig.py

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  39 # Authors: Kevin Lim
  40
  41 from m5.SimObject import SimObject
  42 from m5.params import *
  43 from FuncUnit import *
  44
  45 class IntALU(FUDesc):
  46     opList = [ OpDesc(opClass='IntAlu') ]
  47     count = 6
  48
  49 class IntMultDiv(FUDesc):
  50     opList = [ OpDesc(opClass='IntMult', opLat=3),
  51                OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
  52     count=2
  53
  54 class FP_ALU(FUDesc):
  55     opList = [ OpDesc(opClass='FloatAdd', opLat=2),
  56                OpDesc(opClass='FloatCmp', opLat=2),
  57                OpDesc(opClass='FloatCvt', opLat=2) ]
  58     count = 4
  59
  60 class FP_MultDiv(FUDesc):
  61     opList = [ OpDesc(opClass='FloatMult', opLat=4),
  62                OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
  63                OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
  64     count = 2
  65
  66 class SIMD_Unit(FUDesc):
  67     opList = [ OpDesc(opClass='SimdAdd'),
  68                OpDesc(opClass='SimdAddAcc'),
  69                OpDesc(opClass='SimdAlu'),
  70                OpDesc(opClass='SimdCmp'),
  71                OpDesc(opClass='SimdCvt'),
  72                OpDesc(opClass='SimdMisc'),
  73                OpDesc(opClass='SimdMult'),
  74                OpDesc(opClass='SimdMultAcc'),
  75                OpDesc(opClass='SimdShift'),
  76                OpDesc(opClass='SimdShiftAcc'),
  77                OpDesc(opClass='SimdSqrt'),
  78                OpDesc(opClass='SimdFloatAdd'),
  79                OpDesc(opClass='SimdFloatAlu'),
  80                OpDesc(opClass='SimdFloatCmp'),
  81                OpDesc(opClass='SimdFloatCvt'),
  82                OpDesc(opClass='SimdFloatDiv'),
  83                OpDesc(opClass='SimdFloatMisc'),
  84                OpDesc(opClass='SimdFloatMult'),
  85                OpDesc(opClass='SimdFloatMultAcc'),
  86                OpDesc(opClass='SimdFloatSqrt') ]
  87     count = 4
  88
  89 class ReadPort(FUDesc):
  90     opList = [ OpDesc(opClass='MemRead') ]
  91     count = 0
  92
  93 class WritePort(FUDesc):
  94     opList = [ OpDesc(opClass='MemWrite') ]
  95     count = 0
  96
  97 class RdWrPort(FUDesc):
  98     opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
  99     count = 4
 100
 101 class IprPort(FUDesc):
 102     opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
 103     count = 1
 104