src/cpu/o3/FuncUnitConfig.py

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  39 # Authors: Kevin Lim
  40
  41 from m5.SimObject import SimObject
  42 from m5.defines import buildEnv
  43 from m5.params import *
  44
  45 from m5.objects.FuncUnit import *
  46
  47 class IntALU(FUDesc):
  48     opList = [ OpDesc(opClass='IntAlu') ]
  49     count = 6
  50
  51 class IntMultDiv(FUDesc):
  52     opList = [ OpDesc(opClass='IntMult', opLat=3),
  53                OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
  54
  55     # DIV and IDIV instructions in x86 are implemented using a loop which
  56     # issues division microops.  The latency of these microops should really be
  57     # one (or a small number) cycle each since each of these computes one bit
  58     # of the quotient.
  59     if buildEnv['TARGET_ISA'] in ('x86'):
  60         opList[1].opLat=1
  61
  62     count=2
  63
  64 class FP_ALU(FUDesc):
  65     opList = [ OpDesc(opClass='FloatAdd', opLat=2),
  66                OpDesc(opClass='FloatCmp', opLat=2),
  67                OpDesc(opClass='FloatCvt', opLat=2) ]
  68     count = 4
  69
  70 class FP_MultDiv(FUDesc):
  71     opList = [ OpDesc(opClass='FloatMult', opLat=4),
  72                OpDesc(opClass='FloatMultAcc', opLat=5),
  73                OpDesc(opClass='FloatMisc', opLat=3),
  74                OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
  75                OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
  76     count = 2
  77
  78 class SIMD_Unit(FUDesc):
  79     opList = [ OpDesc(opClass='SimdAdd'),
  80                OpDesc(opClass='SimdAddAcc'),
  81                OpDesc(opClass='SimdAlu'),
  82                OpDesc(opClass='SimdCmp'),
  83                OpDesc(opClass='SimdCvt'),
  84                OpDesc(opClass='SimdMisc'),
  85                OpDesc(opClass='SimdMult'),
  86                OpDesc(opClass='SimdMultAcc'),
  87                OpDesc(opClass='SimdShift'),
  88                OpDesc(opClass='SimdShiftAcc'),
  89                OpDesc(opClass='SimdDiv'),
  90                OpDesc(opClass='SimdSqrt'),
  91                OpDesc(opClass='SimdFloatAdd'),
  92                OpDesc(opClass='SimdFloatAlu'),
  93                OpDesc(opClass='SimdFloatCmp'),
  94                OpDesc(opClass='SimdFloatCvt'),
  95                OpDesc(opClass='SimdFloatDiv'),
  96                OpDesc(opClass='SimdFloatMisc'),
  97                OpDesc(opClass='SimdFloatMult'),
  98                OpDesc(opClass='SimdFloatMultAcc'),
  99                OpDesc(opClass='SimdFloatSqrt'),
 100                OpDesc(opClass='SimdReduceAdd'),
 101                OpDesc(opClass='SimdReduceAlu'),
 102                OpDesc(opClass='SimdReduceCmp'),
 103                OpDesc(opClass='SimdFloatReduceAdd'),
 104                OpDesc(opClass='SimdFloatReduceCmp') ]
 105     count = 4
 106
 107 class PredALU(FUDesc):
 108     opList = [ OpDesc(opClass='SimdPredAlu') ]
 109     count = 1
 110
 111 class ReadPort(FUDesc):
 112     opList = [ OpDesc(opClass='MemRead'),
 113                OpDesc(opClass='FloatMemRead') ]
 114     count = 0
 115
 116 class WritePort(FUDesc):
 117     opList = [ OpDesc(opClass='MemWrite'),
 118                OpDesc(opClass='FloatMemWrite') ]
 119     count = 0
 120
 121 class RdWrPort(FUDesc):
 122     opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'),
 123                OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')]
 124     count = 4
 125
 126 class IprPort(FUDesc):
 127     opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ]
 128     count = 1
 129