src/cpu/o3/FuncUnitConfig.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  26 #
  27 # Authors: Kevin Lim
  28
  29 from m5.SimObject import SimObject
  30 from m5.params import *
  31 from FuncUnit import *
  32
  33 class IntALU(FUDesc):
  34     opList = [ OpDesc(opClass='IntAlu') ]
  35     count = 6
  36
  37 class IntMultDiv(FUDesc):
  38     opList = [ OpDesc(opClass='IntMult', opLat=3),
  39                OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
  40     count=2
  41
  42 class FP_ALU(FUDesc):
  43     opList = [ OpDesc(opClass='FloatAdd', opLat=2),
  44                OpDesc(opClass='FloatCmp', opLat=2),
  45                OpDesc(opClass='FloatCvt', opLat=2) ]
  46     count = 4
  47
  48 class FP_MultDiv(FUDesc):
  49     opList = [ OpDesc(opClass='FloatMult', opLat=4),
  50                OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
  51                OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
  52     count = 2
  53
  54 class ReadPort(FUDesc):
  55     opList = [ OpDesc(opClass='MemRead') ]
  56     count = 0
  57
  58 class WritePort(FUDesc):
  59     opList = [ OpDesc(opClass='MemWrite') ]
  60     count = 0
  61
  62 class RdWrPort(FUDesc):
  63     opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
  64     count = 4
  65
  66 class IprPort(FUDesc):
  67     opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
  68     count = 1
  69