src/cpu/o3/O3CPU.py

   1 # Copyright (c) 2016, 2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
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  13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
  14 # All rights reserved.
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  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Kevin Lim
  40
  41 from __future__ import print_function
  42
  43 from m5.defines import buildEnv
  44 from m5.params import *
  45 from m5.proxy import *
  46
  47 from m5.objects.BaseCPU import BaseCPU
  48 from m5.objects.FUPool import *
  49 from m5.objects.O3Checker import O3Checker
  50 from m5.objects.BranchPredictor import *
  51
  52 class FetchPolicy(ScopedEnum):
  53     vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
  54
  55 class SMTQueuePolicy(ScopedEnum):
  56     vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]
  57
  58 class CommitPolicy(ScopedEnum):
  59     vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ]
  60
  61 class DerivO3CPU(BaseCPU):
  62     type = 'DerivO3CPU'
  63     cxx_header = 'cpu/o3/deriv.hh'
  64
  65     @classmethod
  66     def memory_mode(cls):
  67         return 'timing'
  68
  69     @classmethod
  70     def require_caches(cls):
  71         return True
  72
  73     @classmethod
  74     def support_take_over(cls):
  75         return True
  76
  77     activity = Param.Unsigned(0, "Initial count")
  78
  79     cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
  80           "Constrains stores only.")
  81     cacheLoadPorts = Param.Unsigned(200, "Cache Ports. "
  82           "Constrains loads only.")
  83
  84     decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
  85     renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
  86     iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
  87                                    "delay")
  88     commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
  89     fetchWidth = Param.Unsigned(8, "Fetch width")
  90     fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
  91     fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
  92                                     "per-thread")
  93
  94     renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
  95     iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
  96                                     "delay")
  97     commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
  98     fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
  99     decodeWidth = Param.Unsigned(8, "Decode width")
 100
 101     iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
 102                                     "delay")
 103     commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
 104     decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
 105     renameWidth = Param.Unsigned(8, "Rename width")
 106
 107     commitToIEWDelay = Param.Cycles(1, "Commit to "
 108                "Issue/Execute/Writeback delay")
 109     renameToIEWDelay = Param.Cycles(2, "Rename to "
 110                "Issue/Execute/Writeback delay")
 111     issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
 112               "to the IEW stage)")
 113     dispatchWidth = Param.Unsigned(8, "Dispatch width")
 114     issueWidth = Param.Unsigned(8, "Issue width")
 115     wbWidth = Param.Unsigned(8, "Writeback width")
 116     fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
 117
 118     iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
 119                "delay")
 120     renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
 121     commitWidth = Param.Unsigned(8, "Commit width")
 122     squashWidth = Param.Unsigned(8, "Squash width")
 123     trapLatency = Param.Cycles(13, "Trap latency")
 124     fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
 125
 126     backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
 127     forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
 128
 129     LQEntries = Param.Unsigned(32, "Number of load queue entries")
 130     SQEntries = Param.Unsigned(32, "Number of store queue entries")
 131     LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
 132     LSQCheckLoads = Param.Bool(True,
 133         "Should dependency violations be checked for loads & stores or just stores")
 134     store_set_clear_period = Param.Unsigned(250000,
 135             "Number of load/store insts before the dep predictor should be invalidated")
 136     LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
 137     SSITSize = Param.Unsigned(1024, "Store set ID table size")
 138
 139     numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
 140
 141     numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
 142     numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
 143                                       "registers")
 144     # most ISAs don't use condition-code regs, so default is 0
 145     _defaultNumPhysCCRegs = 0
 146     if buildEnv['TARGET_ISA'] in ('arm','x86'):
 147         # For x86, each CC reg is used to hold only a subset of the
 148         # flags, so we need 4-5 times the number of CC regs as
 149         # physical integer regs to be sure we don't run out.  In
 150         # typical real machines, CC regs are not explicitly renamed
 151         # (it's a side effect of int reg renaming), so they should
 152         # never be the bottleneck here.
 153         _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
 154     numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
 155                                       "registers")
 156     numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate "
 157                                       "registers")
 158     numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
 159                                    "Number of physical cc registers")
 160     numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
 161     numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
 162
 163     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
 164     smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
 165     smtLSQPolicy    = Param.SMTQueuePolicy('Partitioned',
 166                                            "SMT LSQ Sharing Policy")
 167     smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
 168     smtIQPolicy    = Param.SMTQueuePolicy('Partitioned',
 169                                           "SMT IQ Sharing Policy")
 170     smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
 171     smtROBPolicy   = Param.SMTQueuePolicy('Partitioned',
 172                                           "SMT ROB Sharing Policy")
 173     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
 174     smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy")
 175
 176     branchPred = Param.BranchPredictor(TournamentBP(numThreads =
 177                                                        Parent.numThreads),
 178                                        "Branch Predictor")
 179     needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
 180                           "Enable TSO Memory model")
 181
 182     def addCheckerCpu(self):
 183         if buildEnv['TARGET_ISA'] in ['arm']:
 184             from m5.objects.ArmTLB import ArmTLB
 185
 186             self.checker = O3Checker(workload=self.workload,
 187                                      exitOnError=False,
 188                                      updateOnError=True,
 189                                      warnOnlyOnLoadError=True)
 190             self.checker.itb = ArmTLB(size = self.itb.size)
 191             self.checker.dtb = ArmTLB(size = self.dtb.size)
 192             self.checker.cpu_id = self.cpu_id
 193
 194         else:
 195             print("ERROR: Checker only supported under ARM ISA!")
 196             exit(1)