1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 from m5
.defines
import buildEnv
30 from m5
.params
import *
31 from m5
.proxy
import *
32 from BaseCPU
import BaseCPU
34 from O3Checker
import O3Checker
36 class DerivO3CPU(BaseCPU
):
38 cxx_header
= 'cpu/o3/deriv.hh'
40 activity
= Param
.Unsigned(0, "Initial count")
42 cachePorts
= Param
.Unsigned(200, "Cache Ports")
44 decodeToFetchDelay
= Param
.Cycles(1, "Decode to fetch delay")
45 renameToFetchDelay
= Param
.Cycles(1 ,"Rename to fetch delay")
46 iewToFetchDelay
= Param
.Cycles(1, "Issue/Execute/Writeback to fetch "
48 commitToFetchDelay
= Param
.Cycles(1, "Commit to fetch delay")
49 fetchWidth
= Param
.Unsigned(8, "Fetch width")
51 renameToDecodeDelay
= Param
.Cycles(1, "Rename to decode delay")
52 iewToDecodeDelay
= Param
.Cycles(1, "Issue/Execute/Writeback to decode "
54 commitToDecodeDelay
= Param
.Cycles(1, "Commit to decode delay")
55 fetchToDecodeDelay
= Param
.Cycles(1, "Fetch to decode delay")
56 decodeWidth
= Param
.Unsigned(8, "Decode width")
58 iewToRenameDelay
= Param
.Cycles(1, "Issue/Execute/Writeback to rename "
60 commitToRenameDelay
= Param
.Cycles(1, "Commit to rename delay")
61 decodeToRenameDelay
= Param
.Cycles(1, "Decode to rename delay")
62 renameWidth
= Param
.Unsigned(8, "Rename width")
64 commitToIEWDelay
= Param
.Cycles(1, "Commit to "
65 "Issue/Execute/Writeback delay")
66 renameToIEWDelay
= Param
.Cycles(2, "Rename to "
67 "Issue/Execute/Writeback delay")
68 issueToExecuteDelay
= Param
.Cycles(1, "Issue to execute delay (internal "
70 dispatchWidth
= Param
.Unsigned(8, "Dispatch width")
71 issueWidth
= Param
.Unsigned(8, "Issue width")
72 wbWidth
= Param
.Unsigned(8, "Writeback width")
73 wbDepth
= Param
.Unsigned(1, "Writeback depth")
74 fuPool
= Param
.FUPool(DefaultFUPool(), "Functional Unit pool")
76 iewToCommitDelay
= Param
.Cycles(1, "Issue/Execute/Writeback to commit "
78 renameToROBDelay
= Param
.Cycles(1, "Rename to reorder buffer delay")
79 commitWidth
= Param
.Unsigned(8, "Commit width")
80 squashWidth
= Param
.Unsigned(8, "Squash width")
81 trapLatency
= Param
.Cycles(13, "Trap latency")
82 fetchTrapLatency
= Param
.Cycles(1, "Fetch trap latency")
84 backComSize
= Param
.Unsigned(5, "Time buffer size for backwards communication")
85 forwardComSize
= Param
.Unsigned(5, "Time buffer size for forward communication")
87 predType
= Param
.String("tournament", "Branch predictor type ('local', 'tournament')")
88 localPredictorSize
= Param
.Unsigned(2048, "Size of local predictor")
89 localCtrBits
= Param
.Unsigned(2, "Bits per counter")
90 localHistoryTableSize
= Param
.Unsigned(2048, "Size of local history table")
91 localHistoryBits
= Param
.Unsigned(11, "Bits for the local history")
92 globalPredictorSize
= Param
.Unsigned(8192, "Size of global predictor")
93 globalCtrBits
= Param
.Unsigned(2, "Bits per counter")
94 globalHistoryBits
= Param
.Unsigned(13, "Bits of history")
95 choicePredictorSize
= Param
.Unsigned(8192, "Size of choice predictor")
96 choiceCtrBits
= Param
.Unsigned(2, "Bits of choice counters")
98 BTBEntries
= Param
.Unsigned(4096, "Number of BTB entries")
99 BTBTagSize
= Param
.Unsigned(16, "Size of the BTB tags, in bits")
101 RASSize
= Param
.Unsigned(16, "RAS size")
103 LQEntries
= Param
.Unsigned(32, "Number of load queue entries")
104 SQEntries
= Param
.Unsigned(32, "Number of store queue entries")
105 LSQDepCheckShift
= Param
.Unsigned(4, "Number of places to shift addr before check")
106 LSQCheckLoads
= Param
.Bool(True,
107 "Should dependency violations be checked for loads & stores or just stores")
108 store_set_clear_period
= Param
.Unsigned(250000,
109 "Number of load/store insts before the dep predictor should be invalidated")
110 LFSTSize
= Param
.Unsigned(1024, "Last fetched store table size")
111 SSITSize
= Param
.Unsigned(1024, "Store set ID table size")
113 numRobs
= Param
.Unsigned(1, "Number of Reorder Buffers");
115 numPhysIntRegs
= Param
.Unsigned(256, "Number of physical integer registers")
116 numPhysFloatRegs
= Param
.Unsigned(256, "Number of physical floating point "
118 numIQEntries
= Param
.Unsigned(64, "Number of instruction queue entries")
119 numROBEntries
= Param
.Unsigned(192, "Number of reorder buffer entries")
121 instShiftAmt
= Param
.Unsigned(2, "Number of bits to shift instructions by")
123 smtNumFetchingThreads
= Param
.Unsigned(1, "SMT Number of Fetching Threads")
124 smtFetchPolicy
= Param
.String('SingleThread', "SMT Fetch policy")
125 smtLSQPolicy
= Param
.String('Partitioned', "SMT LSQ Sharing Policy")
126 smtLSQThreshold
= Param
.Int(100, "SMT LSQ Threshold Sharing Parameter")
127 smtIQPolicy
= Param
.String('Partitioned', "SMT IQ Sharing Policy")
128 smtIQThreshold
= Param
.Int(100, "SMT IQ Threshold Sharing Parameter")
129 smtROBPolicy
= Param
.String('Partitioned', "SMT ROB Sharing Policy")
130 smtROBThreshold
= Param
.Int(100, "SMT ROB Threshold Sharing Parameter")
131 smtCommitPolicy
= Param
.String('RoundRobin', "SMT Commit Policy")
133 needsTSO
= Param
.Bool(buildEnv
['TARGET_ISA'] == 'x86',
134 "Enable TSO Memory model")
136 def addCheckerCpu(self
):
137 if buildEnv
['TARGET_ISA'] in ['arm']:
138 from ArmTLB
import ArmTLB
140 self
.checker
= O3Checker(workload
=self
.workload
,
143 warnOnlyOnLoadError
=True)
144 self
.checker
.itb
= ArmTLB(size
= self
.itb
.size
)
145 self
.checker
.dtb
= ArmTLB(size
= self
.dtb
.size
)
146 self
.checker
.cpu_id
= self
.cpu_id
149 print "ERROR: Checker only supported under ARM ISA!"