1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 from m5
.params
import *
30 from m5
.proxy
import *
31 from m5
import build_env
32 from BaseCPU
import BaseCPU
35 if build_env
['USE_CHECKER']:
36 from O3Checker
import O3Checker
38 class DerivO3CPU(BaseCPU
):
40 activity
= Param
.Unsigned(0, "Initial count")
41 numThreads
= Param
.Unsigned(1, "number of HW thread contexts")
43 if build_env
['FULL_SYSTEM']:
44 profile
= Param
.Latency('0ns', "trace the kernel stack")
45 if build_env
['USE_CHECKER']:
46 if not build_env
['FULL_SYSTEM']:
47 checker
= Param
.BaseCPU(O3Checker(workload
=Parent
.workload
,
50 warnOnlyOnLoadError
=False),
53 checker
= Param
.BaseCPU(O3Checker(exitOnError
=False, updateOnError
=True,
54 warnOnlyOnLoadError
=False), "checker")
55 checker
.itb
= Parent
.itb
56 checker
.dtb
= Parent
.dtb
58 cachePorts
= Param
.Unsigned(200, "Cache Ports")
59 icache_port
= Port("Instruction Port")
60 dcache_port
= Port("Data Port")
61 _mem_ports
= ['icache_port', 'dcache_port']
63 decodeToFetchDelay
= Param
.Unsigned(1, "Decode to fetch delay")
64 renameToFetchDelay
= Param
.Unsigned(1 ,"Rename to fetch delay")
65 iewToFetchDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to fetch "
67 commitToFetchDelay
= Param
.Unsigned(1, "Commit to fetch delay")
68 fetchWidth
= Param
.Unsigned(8, "Fetch width")
70 renameToDecodeDelay
= Param
.Unsigned(1, "Rename to decode delay")
71 iewToDecodeDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to decode "
73 commitToDecodeDelay
= Param
.Unsigned(1, "Commit to decode delay")
74 fetchToDecodeDelay
= Param
.Unsigned(1, "Fetch to decode delay")
75 decodeWidth
= Param
.Unsigned(8, "Decode width")
77 iewToRenameDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to rename "
79 commitToRenameDelay
= Param
.Unsigned(1, "Commit to rename delay")
80 decodeToRenameDelay
= Param
.Unsigned(1, "Decode to rename delay")
81 renameWidth
= Param
.Unsigned(8, "Rename width")
83 commitToIEWDelay
= Param
.Unsigned(1, "Commit to "
84 "Issue/Execute/Writeback delay")
85 renameToIEWDelay
= Param
.Unsigned(2, "Rename to "
86 "Issue/Execute/Writeback delay")
87 issueToExecuteDelay
= Param
.Unsigned(1, "Issue to execute delay (internal "
89 dispatchWidth
= Param
.Unsigned(8, "Dispatch width")
90 issueWidth
= Param
.Unsigned(8, "Issue width")
91 wbWidth
= Param
.Unsigned(8, "Writeback width")
92 wbDepth
= Param
.Unsigned(1, "Writeback depth")
93 fuPool
= Param
.FUPool(DefaultFUPool(), "Functional Unit pool")
95 iewToCommitDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to commit "
97 renameToROBDelay
= Param
.Unsigned(1, "Rename to reorder buffer delay")
98 commitWidth
= Param
.Unsigned(8, "Commit width")
99 squashWidth
= Param
.Unsigned(8, "Squash width")
100 trapLatency
= Param
.Tick(13, "Trap latency")
101 fetchTrapLatency
= Param
.Tick(1, "Fetch trap latency")
103 backComSize
= Param
.Unsigned(5, "Time buffer size for backwards communication")
104 forwardComSize
= Param
.Unsigned(5, "Time buffer size for forward communication")
106 predType
= Param
.String("tournament", "Branch predictor type ('local', 'tournament')")
107 localPredictorSize
= Param
.Unsigned(2048, "Size of local predictor")
108 localCtrBits
= Param
.Unsigned(2, "Bits per counter")
109 localHistoryTableSize
= Param
.Unsigned(2048, "Size of local history table")
110 localHistoryBits
= Param
.Unsigned(11, "Bits for the local history")
111 globalPredictorSize
= Param
.Unsigned(8192, "Size of global predictor")
112 globalCtrBits
= Param
.Unsigned(2, "Bits per counter")
113 globalHistoryBits
= Param
.Unsigned(13, "Bits of history")
114 choicePredictorSize
= Param
.Unsigned(8192, "Size of choice predictor")
115 choiceCtrBits
= Param
.Unsigned(2, "Bits of choice counters")
117 BTBEntries
= Param
.Unsigned(4096, "Number of BTB entries")
118 BTBTagSize
= Param
.Unsigned(16, "Size of the BTB tags, in bits")
120 RASSize
= Param
.Unsigned(16, "RAS size")
122 LQEntries
= Param
.Unsigned(32, "Number of load queue entries")
123 SQEntries
= Param
.Unsigned(32, "Number of store queue entries")
124 LFSTSize
= Param
.Unsigned(1024, "Last fetched store table size")
125 SSITSize
= Param
.Unsigned(1024, "Store set ID table size")
127 numRobs
= Param
.Unsigned(1, "Number of Reorder Buffers");
129 numPhysIntRegs
= Param
.Unsigned(256, "Number of physical integer registers")
130 numPhysFloatRegs
= Param
.Unsigned(256, "Number of physical floating point "
132 numIQEntries
= Param
.Unsigned(64, "Number of instruction queue entries")
133 numROBEntries
= Param
.Unsigned(192, "Number of reorder buffer entries")
135 instShiftAmt
= Param
.Unsigned(2, "Number of bits to shift instructions by")
137 function_trace
= Param
.Bool(False, "Enable function trace")
138 function_trace_start
= Param
.Tick(0, "Cycle to start function trace")
140 smtNumFetchingThreads
= Param
.Unsigned(1, "SMT Number of Fetching Threads")
141 smtFetchPolicy
= Param
.String('SingleThread', "SMT Fetch policy")
142 smtLSQPolicy
= Param
.String('Partitioned', "SMT LSQ Sharing Policy")
143 smtLSQThreshold
= Param
.Int(100, "SMT LSQ Threshold Sharing Parameter")
144 smtIQPolicy
= Param
.String('Partitioned', "SMT IQ Sharing Policy")
145 smtIQThreshold
= Param
.Int(100, "SMT IQ Threshold Sharing Parameter")
146 smtROBPolicy
= Param
.String('Partitioned', "SMT ROB Sharing Policy")
147 smtROBThreshold
= Param
.Int(100, "SMT ROB Threshold Sharing Parameter")
148 smtCommitPolicy
= Param
.String('RoundRobin', "SMT Commit Policy")
150 def addPrivateSplitL1Caches(self
, ic
, dc
):
151 BaseCPU
.addPrivateSplitL1Caches(self
, ic
, dc
)
152 self
.icache
.tgts_per_mshr
= 20
153 self
.dcache
.tgts_per_mshr
= 20