1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 from m5
.defines
import buildEnv
30 from m5
.params
import *
31 from m5
.proxy
import *
32 from BaseCPU
import BaseCPU
35 if buildEnv
['USE_CHECKER']:
36 from O3Checker
import O3Checker
38 class DerivO3CPU(BaseCPU
):
40 activity
= Param
.Unsigned(0, "Initial count")
42 if buildEnv
['USE_CHECKER']:
43 if not buildEnv
['FULL_SYSTEM']:
44 checker
= Param
.BaseCPU(O3Checker(workload
=Parent
.workload
,
47 warnOnlyOnLoadError
=False),
50 checker
= Param
.BaseCPU(O3Checker(exitOnError
=False, updateOnError
=True,
51 warnOnlyOnLoadError
=False), "checker")
52 checker
.itb
= Parent
.itb
53 checker
.dtb
= Parent
.dtb
55 cachePorts
= Param
.Unsigned(200, "Cache Ports")
56 icache_port
= Port("Instruction Port")
57 dcache_port
= Port("Data Port")
58 _cached_ports
= BaseCPU
._cached
_ports
+ ['icache_port', 'dcache_port']
60 decodeToFetchDelay
= Param
.Unsigned(1, "Decode to fetch delay")
61 renameToFetchDelay
= Param
.Unsigned(1 ,"Rename to fetch delay")
62 iewToFetchDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to fetch "
64 commitToFetchDelay
= Param
.Unsigned(1, "Commit to fetch delay")
65 fetchWidth
= Param
.Unsigned(8, "Fetch width")
67 renameToDecodeDelay
= Param
.Unsigned(1, "Rename to decode delay")
68 iewToDecodeDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to decode "
70 commitToDecodeDelay
= Param
.Unsigned(1, "Commit to decode delay")
71 fetchToDecodeDelay
= Param
.Unsigned(1, "Fetch to decode delay")
72 decodeWidth
= Param
.Unsigned(8, "Decode width")
74 iewToRenameDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to rename "
76 commitToRenameDelay
= Param
.Unsigned(1, "Commit to rename delay")
77 decodeToRenameDelay
= Param
.Unsigned(1, "Decode to rename delay")
78 renameWidth
= Param
.Unsigned(8, "Rename width")
80 commitToIEWDelay
= Param
.Unsigned(1, "Commit to "
81 "Issue/Execute/Writeback delay")
82 renameToIEWDelay
= Param
.Unsigned(2, "Rename to "
83 "Issue/Execute/Writeback delay")
84 issueToExecuteDelay
= Param
.Unsigned(1, "Issue to execute delay (internal "
86 dispatchWidth
= Param
.Unsigned(8, "Dispatch width")
87 issueWidth
= Param
.Unsigned(8, "Issue width")
88 wbWidth
= Param
.Unsigned(8, "Writeback width")
89 wbDepth
= Param
.Unsigned(1, "Writeback depth")
90 fuPool
= Param
.FUPool(DefaultFUPool(), "Functional Unit pool")
92 iewToCommitDelay
= Param
.Unsigned(1, "Issue/Execute/Writeback to commit "
94 renameToROBDelay
= Param
.Unsigned(1, "Rename to reorder buffer delay")
95 commitWidth
= Param
.Unsigned(8, "Commit width")
96 squashWidth
= Param
.Unsigned(8, "Squash width")
97 trapLatency
= Param
.Tick(13, "Trap latency")
98 fetchTrapLatency
= Param
.Tick(1, "Fetch trap latency")
100 backComSize
= Param
.Unsigned(5, "Time buffer size for backwards communication")
101 forwardComSize
= Param
.Unsigned(5, "Time buffer size for forward communication")
103 predType
= Param
.String("tournament", "Branch predictor type ('local', 'tournament')")
104 localPredictorSize
= Param
.Unsigned(2048, "Size of local predictor")
105 localCtrBits
= Param
.Unsigned(2, "Bits per counter")
106 localHistoryTableSize
= Param
.Unsigned(2048, "Size of local history table")
107 localHistoryBits
= Param
.Unsigned(11, "Bits for the local history")
108 globalPredictorSize
= Param
.Unsigned(8192, "Size of global predictor")
109 globalCtrBits
= Param
.Unsigned(2, "Bits per counter")
110 globalHistoryBits
= Param
.Unsigned(13, "Bits of history")
111 choicePredictorSize
= Param
.Unsigned(8192, "Size of choice predictor")
112 choiceCtrBits
= Param
.Unsigned(2, "Bits of choice counters")
114 BTBEntries
= Param
.Unsigned(4096, "Number of BTB entries")
115 BTBTagSize
= Param
.Unsigned(16, "Size of the BTB tags, in bits")
117 RASSize
= Param
.Unsigned(16, "RAS size")
119 LQEntries
= Param
.Unsigned(32, "Number of load queue entries")
120 SQEntries
= Param
.Unsigned(32, "Number of store queue entries")
121 LSQDepCheckShift
= Param
.Unsigned(4, "Number of places to shift addr before check")
122 LSQCheckLoads
= Param
.Bool(True,
123 "Should dependency violations be checked for loads & stores or just stores")
124 LFSTSize
= Param
.Unsigned(1024, "Last fetched store table size")
125 SSITSize
= Param
.Unsigned(1024, "Store set ID table size")
127 numRobs
= Param
.Unsigned(1, "Number of Reorder Buffers");
129 numPhysIntRegs
= Param
.Unsigned(256, "Number of physical integer registers")
130 numPhysFloatRegs
= Param
.Unsigned(256, "Number of physical floating point "
132 numIQEntries
= Param
.Unsigned(64, "Number of instruction queue entries")
133 numROBEntries
= Param
.Unsigned(192, "Number of reorder buffer entries")
135 instShiftAmt
= Param
.Unsigned(2, "Number of bits to shift instructions by")
137 smtNumFetchingThreads
= Param
.Unsigned(1, "SMT Number of Fetching Threads")
138 smtFetchPolicy
= Param
.String('SingleThread', "SMT Fetch policy")
139 smtLSQPolicy
= Param
.String('Partitioned', "SMT LSQ Sharing Policy")
140 smtLSQThreshold
= Param
.Int(100, "SMT LSQ Threshold Sharing Parameter")
141 smtIQPolicy
= Param
.String('Partitioned', "SMT IQ Sharing Policy")
142 smtIQThreshold
= Param
.Int(100, "SMT IQ Threshold Sharing Parameter")
143 smtROBPolicy
= Param
.String('Partitioned', "SMT ROB Sharing Policy")
144 smtROBThreshold
= Param
.Int(100, "SMT ROB Threshold Sharing Parameter")
145 smtCommitPolicy
= Param
.String('RoundRobin', "SMT Commit Policy")
147 def addPrivateSplitL1Caches(self
, ic
, dc
, iwc
= None, dwc
= None):
148 BaseCPU
.addPrivateSplitL1Caches(self
, ic
, dc
, iwc
, dwc
)
149 self
.icache
.tgts_per_mshr
= 20
150 self
.dcache
.tgts_per_mshr
= 20