src/cpu/o3/O3CPU.py

   1 # Copyright (c) 2016, 2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
  14 # All rights reserved.
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  27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Kevin Lim
  40
  41 from __future__ import print_function
  42
  43 from m5.defines import buildEnv
  44 from m5.params import *
  45 from m5.proxy import *
  46
  47 from m5.objects.BaseCPU import BaseCPU
  48 from m5.objects.FUPool import *
  49 from m5.objects.O3Checker import O3Checker
  50 from m5.objects.BranchPredictor import *
  51
  52 class FetchPolicy(ScopedEnum):
  53     vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
  54
  55 class SMTQueuePolicy(ScopedEnum):
  56     vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]
  57
  58 class CommitPolicy(ScopedEnum):
  59     vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ]
  60
  61 class DerivO3CPU(BaseCPU):
  62     type = 'DerivO3CPU'
  63     cxx_header = 'cpu/o3/deriv.hh'
  64
  65     @classmethod
  66     def memory_mode(cls):
  67         return 'timing'
  68
  69     @classmethod
  70     def require_caches(cls):
  71         return True
  72
  73     @classmethod
  74     def support_take_over(cls):
  75         return True
  76
  77     activity = Param.Unsigned(0, "Initial count")
  78
  79     cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
  80           "Constrains stores only. Loads are constrained by load FUs.")
  81
  82     decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
  83     renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
  84     iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
  85                                    "delay")
  86     commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
  87     fetchWidth = Param.Unsigned(8, "Fetch width")
  88     fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
  89     fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
  90                                     "per-thread")
  91
  92     renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
  93     iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
  94                                     "delay")
  95     commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
  96     fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
  97     decodeWidth = Param.Unsigned(8, "Decode width")
  98
  99     iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
 100                                     "delay")
 101     commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
 102     decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
 103     renameWidth = Param.Unsigned(8, "Rename width")
 104
 105     commitToIEWDelay = Param.Cycles(1, "Commit to "
 106                "Issue/Execute/Writeback delay")
 107     renameToIEWDelay = Param.Cycles(2, "Rename to "
 108                "Issue/Execute/Writeback delay")
 109     issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
 110               "to the IEW stage)")
 111     dispatchWidth = Param.Unsigned(8, "Dispatch width")
 112     issueWidth = Param.Unsigned(8, "Issue width")
 113     wbWidth = Param.Unsigned(8, "Writeback width")
 114     fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
 115
 116     iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
 117                "delay")
 118     renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
 119     commitWidth = Param.Unsigned(8, "Commit width")
 120     squashWidth = Param.Unsigned(8, "Squash width")
 121     trapLatency = Param.Cycles(13, "Trap latency")
 122     fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
 123
 124     backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
 125     forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
 126
 127     LQEntries = Param.Unsigned(32, "Number of load queue entries")
 128     SQEntries = Param.Unsigned(32, "Number of store queue entries")
 129     LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
 130     LSQCheckLoads = Param.Bool(True,
 131         "Should dependency violations be checked for loads & stores or just stores")
 132     store_set_clear_period = Param.Unsigned(250000,
 133             "Number of load/store insts before the dep predictor should be invalidated")
 134     LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
 135     SSITSize = Param.Unsigned(1024, "Store set ID table size")
 136
 137     numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
 138
 139     numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
 140     numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
 141                                       "registers")
 142     # most ISAs don't use condition-code regs, so default is 0
 143     _defaultNumPhysCCRegs = 0
 144     if buildEnv['TARGET_ISA'] in ('arm','x86'):
 145         # For x86, each CC reg is used to hold only a subset of the
 146         # flags, so we need 4-5 times the number of CC regs as
 147         # physical integer regs to be sure we don't run out.  In
 148         # typical real machines, CC regs are not explicitly renamed
 149         # (it's a side effect of int reg renaming), so they should
 150         # never be the bottleneck here.
 151         _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
 152     numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
 153                                       "registers")
 154     numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate "
 155                                       "registers")
 156     numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
 157                                    "Number of physical cc registers")
 158     numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
 159     numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
 160
 161     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
 162     smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
 163     smtLSQPolicy    = Param.SMTQueuePolicy('Partitioned',
 164                                            "SMT LSQ Sharing Policy")
 165     smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
 166     smtIQPolicy    = Param.SMTQueuePolicy('Partitioned',
 167                                           "SMT IQ Sharing Policy")
 168     smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
 169     smtROBPolicy   = Param.SMTQueuePolicy('Partitioned',
 170                                           "SMT ROB Sharing Policy")
 171     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
 172     smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy")
 173
 174     branchPred = Param.BranchPredictor(TournamentBP(numThreads =
 175                                                        Parent.numThreads),
 176                                        "Branch Predictor")
 177     needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
 178                           "Enable TSO Memory model")
 179
 180     def addCheckerCpu(self):
 181         if buildEnv['TARGET_ISA'] in ['arm']:
 182             from m5.objects.ArmTLB import ArmTLB
 183
 184             self.checker = O3Checker(workload=self.workload,
 185                                      exitOnError=False,
 186                                      updateOnError=True,
 187                                      warnOnlyOnLoadError=True)
 188             self.checker.itb = ArmTLB(size = self.itb.size)
 189             self.checker.dtb = ArmTLB(size = self.dtb.size)
 190             self.checker.cpu_id = self.cpu_id
 191
 192         else:
 193             print("ERROR: Checker only supported under ARM ISA!")
 194             exit(1)