3 # Copyright (c) 2006 The Regents of The University of Michigan
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 # Authors: Nathan Binkert
35 if 'O3CPU' in env['CPU_MODELS']:
36 SimObject('FUPool.py')
37 SimObject('FuncUnitConfig.py')
40 Source('base_dyn_inst.cc')
41 Source('bpred_unit.cc')
46 Source('free_list.cc')
49 Source('inst_queue.cc')
52 Source('mem_dep_unit.cc')
54 Source('rename_map.cc')
56 Source('scoreboard.cc')
57 Source('store_set.cc')
59 if env['TARGET_ISA'] == 'alpha':
60 Source('alpha/cpu.cc')
61 Source('alpha/cpu_builder.cc')
62 Source('alpha/dyn_inst.cc')
63 Source('alpha/thread_context.cc')
64 elif env['TARGET_ISA'] == 'mips':
66 Source('mips/cpu_builder.cc')
67 Source('mips/dyn_inst.cc')
68 Source('mips/thread_context.cc')
69 elif env['TARGET_ISA'] == 'sparc':
70 Source('sparc/cpu.cc')
71 Source('sparc/cpu_builder.cc')
72 Source('sparc/dyn_inst.cc')
73 Source('sparc/thread_context.cc')
75 sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
77 if env['USE_CHECKER']:
78 SimObject('O3Checker.py')
79 Source('checker_builder.cc')
81 if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
82 Source('2bit_local_pred.cc')
85 Source('tournament_pred.cc')