src/cpu/o3/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 import sys
  30
  31 Import('*')
  32
  33 if 'O3CPU' in env['CPU_MODELS']:
  34     SimObject('FUPool.py')
  35     SimObject('FuncUnitConfig.py')
  36     SimObject('O3CPU.py')
  37
  38     Source('base_dyn_inst.cc')
  39     Source('commit.cc')
  40     Source('cpu.cc')
  41     Source('decode.cc')
  42     Source('dyn_inst.cc')
  43     Source('fetch.cc')
  44     Source('free_list.cc')
  45     Source('fu_pool.cc')
  46     Source('iew.cc')
  47     Source('inst_queue.cc')
  48     Source('lsq.cc')
  49     Source('lsq_unit.cc')
  50     Source('mem_dep_unit.cc')
  51     Source('regfile.cc')
  52     Source('rename.cc')
  53     Source('rename_map.cc')
  54     Source('rob.cc')
  55     Source('scoreboard.cc')
  56     Source('store_set.cc')
  57     Source('thread_context.cc')
  58
  59     DebugFlag('CommitRate')
  60     DebugFlag('IEW')
  61     DebugFlag('IQ')
  62     DebugFlag('LSQ')
  63     DebugFlag('LSQUnit')
  64     DebugFlag('MemDepUnit')
  65     DebugFlag('O3CPU')
  66     DebugFlag('ROB')
  67     DebugFlag('Rename')
  68     DebugFlag('Scoreboard')
  69     DebugFlag('StoreSet')
  70     DebugFlag('Writeback')
  71
  72     CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
  73         'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
  74         'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
  75
  76     SimObject('O3Checker.py')
  77     Source('checker.cc')