src/cpu/o3/alpha/cpu_builder.cc

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <string>
  32
  33 #include "cpu/base.hh"
  34 #include "cpu/o3/alpha/cpu.hh"
  35 #include "cpu/o3/alpha/impl.hh"
  36 #include "cpu/o3/alpha/params.hh"
  37 #include "cpu/o3/fu_pool.hh"
  38 #include "sim/builder.hh"
  39
  40 class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
  41 {
  42   public:
  43     DerivO3CPU(AlphaSimpleParams *p)
  44         : AlphaO3CPU<AlphaSimpleImpl>(p)
  45     { }
  46 };
  47
  48 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
  49
  50     Param<int> clock;
  51     Param<int> numThreads;
  52 Param<int> activity;
  53
  54 #if FULL_SYSTEM
  55 SimObjectParam<System *> system;
  56 Param<int> cpu_id;
  57 SimObjectParam<AlphaITB *> itb;
  58 SimObjectParam<AlphaDTB *> dtb;
  59 #else
  60 SimObjectVectorParam<Process *> workload;
  61 #endif // FULL_SYSTEM
  62
  63 SimObjectParam<MemObject *> mem;
  64
  65 SimObjectParam<BaseCPU *> checker;
  66
  67 Param<Counter> max_insts_any_thread;
  68 Param<Counter> max_insts_all_threads;
  69 Param<Counter> max_loads_any_thread;
  70 Param<Counter> max_loads_all_threads;
  71
  72 Param<unsigned> cachePorts;
  73
  74 Param<unsigned> decodeToFetchDelay;
  75 Param<unsigned> renameToFetchDelay;
  76 Param<unsigned> iewToFetchDelay;
  77 Param<unsigned> commitToFetchDelay;
  78 Param<unsigned> fetchWidth;
  79
  80 Param<unsigned> renameToDecodeDelay;
  81 Param<unsigned> iewToDecodeDelay;
  82 Param<unsigned> commitToDecodeDelay;
  83 Param<unsigned> fetchToDecodeDelay;
  84 Param<unsigned> decodeWidth;
  85
  86 Param<unsigned> iewToRenameDelay;
  87 Param<unsigned> commitToRenameDelay;
  88 Param<unsigned> decodeToRenameDelay;
  89 Param<unsigned> renameWidth;
  90
  91 Param<unsigned> commitToIEWDelay;
  92 Param<unsigned> renameToIEWDelay;
  93 Param<unsigned> issueToExecuteDelay;
  94 Param<unsigned> dispatchWidth;
  95 Param<unsigned> issueWidth;
  96 Param<unsigned> wbWidth;
  97 Param<unsigned> wbDepth;
  98 SimObjectParam<FUPool *> fuPool;
  99
 100 Param<unsigned> iewToCommitDelay;
 101 Param<unsigned> renameToROBDelay;
 102 Param<unsigned> commitWidth;
 103 Param<unsigned> squashWidth;
 104 Param<Tick> trapLatency;
 105
 106 Param<unsigned> backComSize;
 107 Param<unsigned> forwardComSize;
 108
 109 Param<std::string> predType;
 110 Param<unsigned> localPredictorSize;
 111 Param<unsigned> localCtrBits;
 112 Param<unsigned> localHistoryTableSize;
 113 Param<unsigned> localHistoryBits;
 114 Param<unsigned> globalPredictorSize;
 115 Param<unsigned> globalCtrBits;
 116 Param<unsigned> globalHistoryBits;
 117 Param<unsigned> choicePredictorSize;
 118 Param<unsigned> choiceCtrBits;
 119
 120 Param<unsigned> BTBEntries;
 121 Param<unsigned> BTBTagSize;
 122
 123 Param<unsigned> RASSize;
 124
 125 Param<unsigned> LQEntries;
 126 Param<unsigned> SQEntries;
 127 Param<unsigned> LFSTSize;
 128 Param<unsigned> SSITSize;
 129
 130 Param<unsigned> numPhysIntRegs;
 131 Param<unsigned> numPhysFloatRegs;
 132 Param<unsigned> numIQEntries;
 133 Param<unsigned> numROBEntries;
 134
 135 Param<unsigned> smtNumFetchingThreads;
 136 Param<std::string>   smtFetchPolicy;
 137 Param<std::string>   smtLSQPolicy;
 138 Param<unsigned> smtLSQThreshold;
 139 Param<std::string>   smtIQPolicy;
 140 Param<unsigned> smtIQThreshold;
 141 Param<std::string>   smtROBPolicy;
 142 Param<unsigned> smtROBThreshold;
 143 Param<std::string>   smtCommitPolicy;
 144
 145 Param<unsigned> instShiftAmt;
 146
 147 Param<bool> defer_registration;
 148
 149 Param<bool> function_trace;
 150 Param<Tick> function_trace_start;
 151
 152 END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
 153
 154 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 155
 156     INIT_PARAM(clock, "clock speed"),
 157     INIT_PARAM(numThreads, "number of HW thread contexts"),
 158     INIT_PARAM_DFLT(activity, "Initial activity count", 0),
 159
 160 #if FULL_SYSTEM
 161     INIT_PARAM(system, "System object"),
 162     INIT_PARAM(cpu_id, "processor ID"),
 163     INIT_PARAM(itb, "Instruction translation buffer"),
 164     INIT_PARAM(dtb, "Data translation buffer"),
 165 #else
 166     INIT_PARAM(workload, "Processes to run"),
 167 #endif // FULL_SYSTEM
 168
 169     INIT_PARAM(mem, "Memory"),
 170
 171     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 172
 173     INIT_PARAM_DFLT(max_insts_any_thread,
 174                     "Terminate when any thread reaches this inst count",
 175                     0),
 176     INIT_PARAM_DFLT(max_insts_all_threads,
 177                     "Terminate when all threads have reached"
 178                     "this inst count",
 179                     0),
 180     INIT_PARAM_DFLT(max_loads_any_thread,
 181                     "Terminate when any thread reaches this load count",
 182                     0),
 183     INIT_PARAM_DFLT(max_loads_all_threads,
 184                     "Terminate when all threads have reached this load"
 185                     "count",
 186                     0),
 187
 188     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
 189
 190     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 191     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 192     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 193                "delay"),
 194     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 195     INIT_PARAM(fetchWidth, "Fetch width"),
 196     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 197     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 198                "delay"),
 199     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 200     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 201     INIT_PARAM(decodeWidth, "Decode width"),
 202
 203     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 204                "delay"),
 205     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 206     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 207     INIT_PARAM(renameWidth, "Rename width"),
 208
 209     INIT_PARAM(commitToIEWDelay, "Commit to "
 210                "Issue/Execute/Writeback delay"),
 211     INIT_PARAM(renameToIEWDelay, "Rename to "
 212                "Issue/Execute/Writeback delay"),
 213     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 214                "to the IEW stage)"),
 215     INIT_PARAM(dispatchWidth, "Dispatch width"),
 216     INIT_PARAM(issueWidth, "Issue width"),
 217     INIT_PARAM(wbWidth, "Writeback width"),
 218     INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
 219     INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
 220
 221     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 222                "delay"),
 223     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 224     INIT_PARAM(commitWidth, "Commit width"),
 225     INIT_PARAM(squashWidth, "Squash width"),
 226     INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
 227
 228     INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
 229     INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
 230
 231     INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
 232     INIT_PARAM(localPredictorSize, "Size of local predictor"),
 233     INIT_PARAM(localCtrBits, "Bits per counter"),
 234     INIT_PARAM(localHistoryTableSize, "Size of local history table"),
 235     INIT_PARAM(localHistoryBits, "Bits for the local history"),
 236     INIT_PARAM(globalPredictorSize, "Size of global predictor"),
 237     INIT_PARAM(globalCtrBits, "Bits per counter"),
 238     INIT_PARAM(globalHistoryBits, "Bits of history"),
 239     INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
 240     INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
 241
 242     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 243     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 244
 245     INIT_PARAM(RASSize, "RAS size"),
 246
 247     INIT_PARAM(LQEntries, "Number of load queue entries"),
 248     INIT_PARAM(SQEntries, "Number of store queue entries"),
 249     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 250     INIT_PARAM(SSITSize, "Store set ID table size"),
 251
 252     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 253     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 254                "registers"),
 255     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 256     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 257
 258     INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
 259     INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
 260     INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
 261     INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
 262     INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
 263     INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
 264     INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
 265     INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
 266     INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
 267
 268     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 269     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 270
 271     INIT_PARAM(function_trace, "Enable function trace"),
 272     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 273
 274 END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 275
 276 CREATE_SIM_OBJECT(DerivO3CPU)
 277 {
 278     DerivO3CPU *cpu;
 279
 280 #if FULL_SYSTEM
 281     // Full-system only supports a single thread for the moment.
 282     int actual_num_threads = 1;
 283 #else
 284     // In non-full-system mode, we infer the number of threads from
 285     // the workload if it's not explicitly specified.
 286     int actual_num_threads =
 287         (numThreads.isValid() && numThreads >= workload.size()) ?
 288          numThreads : workload.size();
 289
 290     if (workload.size() == 0) {
 291         fatal("Must specify at least one workload!");
 292     }
 293 #endif
 294
 295     AlphaSimpleParams *params = new AlphaSimpleParams;
 296
 297     params->clock = clock;
 298
 299     params->name = getInstanceName();
 300     params->numberOfThreads = actual_num_threads;
 301     params->activity = activity;
 302
 303 #if FULL_SYSTEM
 304     params->system = system;
 305     params->cpu_id = cpu_id;
 306     params->itb = itb;
 307     params->dtb = dtb;
 308 #else
 309     params->workload = workload;
 310 #endif // FULL_SYSTEM
 311
 312     params->mem = mem;
 313
 314     params->checker = checker;
 315
 316     params->max_insts_any_thread = max_insts_any_thread;
 317     params->max_insts_all_threads = max_insts_all_threads;
 318     params->max_loads_any_thread = max_loads_any_thread;
 319     params->max_loads_all_threads = max_loads_all_threads;
 320
 321     //
 322     // Caches
 323     //
 324     params->cachePorts = cachePorts;
 325
 326     params->decodeToFetchDelay = decodeToFetchDelay;
 327     params->renameToFetchDelay = renameToFetchDelay;
 328     params->iewToFetchDelay = iewToFetchDelay;
 329     params->commitToFetchDelay = commitToFetchDelay;
 330     params->fetchWidth = fetchWidth;
 331
 332     params->renameToDecodeDelay = renameToDecodeDelay;
 333     params->iewToDecodeDelay = iewToDecodeDelay;
 334     params->commitToDecodeDelay = commitToDecodeDelay;
 335     params->fetchToDecodeDelay = fetchToDecodeDelay;
 336     params->decodeWidth = decodeWidth;
 337
 338     params->iewToRenameDelay = iewToRenameDelay;
 339     params->commitToRenameDelay = commitToRenameDelay;
 340     params->decodeToRenameDelay = decodeToRenameDelay;
 341     params->renameWidth = renameWidth;
 342
 343     params->commitToIEWDelay = commitToIEWDelay;
 344     params->renameToIEWDelay = renameToIEWDelay;
 345     params->issueToExecuteDelay = issueToExecuteDelay;
 346     params->dispatchWidth = dispatchWidth;
 347     params->issueWidth = issueWidth;
 348     params->wbWidth = wbWidth;
 349     params->wbDepth = wbDepth;
 350     params->fuPool = fuPool;
 351
 352     params->iewToCommitDelay = iewToCommitDelay;
 353     params->renameToROBDelay = renameToROBDelay;
 354     params->commitWidth = commitWidth;
 355     params->squashWidth = squashWidth;
 356     params->trapLatency = trapLatency;
 357
 358     params->backComSize = backComSize;
 359     params->forwardComSize = forwardComSize;
 360
 361     params->predType = predType;
 362     params->localPredictorSize = localPredictorSize;
 363     params->localCtrBits = localCtrBits;
 364     params->localHistoryTableSize = localHistoryTableSize;
 365     params->localHistoryBits = localHistoryBits;
 366     params->globalPredictorSize = globalPredictorSize;
 367     params->globalCtrBits = globalCtrBits;
 368     params->globalHistoryBits = globalHistoryBits;
 369     params->choicePredictorSize = choicePredictorSize;
 370     params->choiceCtrBits = choiceCtrBits;
 371
 372     params->BTBEntries = BTBEntries;
 373     params->BTBTagSize = BTBTagSize;
 374
 375     params->RASSize = RASSize;
 376
 377     params->LQEntries = LQEntries;
 378     params->SQEntries = SQEntries;
 379
 380     params->SSITSize = SSITSize;
 381     params->LFSTSize = LFSTSize;
 382
 383     params->numPhysIntRegs = numPhysIntRegs;
 384     params->numPhysFloatRegs = numPhysFloatRegs;
 385     params->numIQEntries = numIQEntries;
 386     params->numROBEntries = numROBEntries;
 387
 388     params->smtNumFetchingThreads = smtNumFetchingThreads;
 389
 390     // Default smtFetchPolicy to "RoundRobin", if necessary.
 391     std::string round_robin_policy = "RoundRobin";
 392     std::string single_thread = "SingleThread";
 393
 394     if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
 395         params->smtFetchPolicy = round_robin_policy;
 396     else
 397         params->smtFetchPolicy = smtFetchPolicy;
 398
 399     params->smtIQPolicy    = smtIQPolicy;
 400     params->smtLSQPolicy    = smtLSQPolicy;
 401     params->smtLSQThreshold = smtLSQThreshold;
 402     params->smtROBPolicy   = smtROBPolicy;
 403     params->smtROBThreshold = smtROBThreshold;
 404     params->smtCommitPolicy = smtCommitPolicy;
 405
 406     params->instShiftAmt = 2;
 407
 408     params->deferRegistration = defer_registration;
 409
 410     params->functionTrace = function_trace;
 411     params->functionTraceStart = function_trace_start;
 412
 413     cpu = new DerivO3CPU(params);
 414
 415     return cpu;
 416 }
 417
 418 REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
 419