src/cpu/o3/alpha/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/use_checker.hh"
  32
  33 #include "arch/alpha/faults.hh"
  34 #include "arch/alpha/isa_traits.hh"
  35 #include "base/cprintf.hh"
  36 #include "base/statistics.hh"
  37 #include "base/timebuf.hh"
  38 #include "cpu/checker/thread_context.hh"
  39 #include "sim/sim_events.hh"
  40 #include "sim/stats.hh"
  41
  42 #include "cpu/o3/alpha/cpu.hh"
  43 #include "cpu/o3/alpha/params.hh"
  44 #include "cpu/o3/alpha/thread_context.hh"
  45 #include "cpu/o3/comm.hh"
  46 #include "cpu/o3/thread_state.hh"
  47
  48 #if FULL_SYSTEM
  49 #include "arch/alpha/osfpal.hh"
  50 #include "arch/isa_traits.hh"
  51 #include "arch/kernel_stats.hh"
  52 #include "cpu/quiesce_event.hh"
  53 #include "sim/sim_exit.hh"
  54 #include "sim/system.hh"
  55 #endif
  56
  57 template <class Impl>
  58 AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
  59 #if FULL_SYSTEM
  60     : FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
  61 #else
  62     : FullO3CPU<Impl>(params)
  63 #endif
  64 {
  65     DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
  66
  67     // Setup any thread state.
  68     this->thread.resize(this->numThreads);
  69
  70     for (int i = 0; i < this->numThreads; ++i) {
  71 #if FULL_SYSTEM
  72         // SMT is not supported in FS mode yet.
  73         assert(this->numThreads == 1);
  74         this->thread[i] = new Thread(this, 0);
  75         this->thread[i]->setStatus(ThreadContext::Suspended);
  76 #else
  77         if (i < params->workload.size()) {
  78             DPRINTF(O3CPU, "Workload[%i] process is %#x",
  79                     i, this->thread[i]);
  80             this->thread[i] = new Thread(this, i, params->workload[i], i);
  81
  82             this->thread[i]->setStatus(ThreadContext::Suspended);
  83
  84             //usedTids[i] = true;
  85             //threadMap[i] = i;
  86         } else {
  87             //Allocate Empty thread so M5 can use later
  88             //when scheduling threads to CPU
  89             Process* dummy_proc = NULL;
  90
  91             this->thread[i] = new Thread(this, i, dummy_proc, i);
  92             //usedTids[i] = false;
  93         }
  94 #endif // !FULL_SYSTEM
  95
  96         ThreadContext *tc;
  97
  98         // Setup the TC that will serve as the interface to the threads/CPU.
  99         AlphaTC<Impl> *alpha_tc =
 100             new AlphaTC<Impl>;
 101
 102         tc = alpha_tc;
 103
 104         // If we're using a checker, then the TC should be the
 105         // CheckerThreadContext.
 106 #if USE_CHECKER
 107         if (params->checker) {
 108             tc = new CheckerThreadContext<AlphaTC<Impl> >(
 109                 alpha_tc, this->checker);
 110         }
 111 #endif
 112
 113         alpha_tc->cpu = this;
 114         alpha_tc->thread = this->thread[i];
 115
 116 #if FULL_SYSTEM
 117         // Setup quiesce event.
 118         this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc);
 119
 120         Port *mem_port;
 121         FunctionalPort *phys_port;
 122         VirtualPort *virt_port;
 123         phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
 124                                                 name(), i));
 125         mem_port = this->system->physmem->getPort("functional");
 126         mem_port->setPeer(phys_port);
 127         phys_port->setPeer(mem_port);
 128
 129         virt_port = new VirtualPort(csprintf("%s-%d-vport",
 130                                              name(), i));
 131         mem_port = this->system->physmem->getPort("functional");
 132         mem_port->setPeer(virt_port);
 133         virt_port->setPeer(mem_port);
 134
 135         this->thread[i]->setPhysPort(phys_port);
 136         this->thread[i]->setVirtPort(virt_port);
 137 #endif
 138         // Give the thread the TC.
 139         this->thread[i]->tc = tc;
 140
 141         // Add the TC to the CPU's list of TC's.
 142         this->threadContexts.push_back(tc);
 143     }
 144
 145     for (int i=0; i < this->numThreads; i++) {
 146         this->thread[i]->setFuncExeInst(0);
 147     }
 148
 149     // Sets CPU pointers. These must be set at this level because the CPU
 150     // pointers are defined to be the highest level of CPU class.
 151     this->fetch.setCPU(this);
 152     this->decode.setCPU(this);
 153     this->rename.setCPU(this);
 154     this->iew.setCPU(this);
 155     this->commit.setCPU(this);
 156
 157     this->rob.setCPU(this);
 158     this->regFile.setCPU(this);
 159
 160     lockAddr = 0;
 161     lockFlag = false;
 162 }
 163
 164 template <class Impl>
 165 void
 166 AlphaO3CPU<Impl>::regStats()
 167 {
 168     // Register stats for everything that has stats.
 169     this->fullCPURegStats();
 170     this->fetch.regStats();
 171     this->decode.regStats();
 172     this->rename.regStats();
 173     this->iew.regStats();
 174     this->commit.regStats();
 175 }
 176
 177
 178 template <class Impl>
 179 TheISA::MiscReg
 180 AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 181 {
 182     return this->regFile.readMiscReg(misc_reg, tid);
 183 }
 184
 185 template <class Impl>
 186 TheISA::MiscReg
 187 AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
 188 {
 189     return this->regFile.readMiscRegWithEffect(misc_reg, tid);
 190 }
 191
 192 template <class Impl>
 193 void
 194 AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
 195 {
 196     this->regFile.setMiscReg(misc_reg, val, tid);
 197 }
 198
 199 template <class Impl>
 200 void
 201 AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
 202                                        unsigned tid)
 203 {
 204     this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
 205 }
 206
 207 template <class Impl>
 208 void
 209 AlphaO3CPU<Impl>::squashFromTC(unsigned tid)
 210 {
 211     this->thread[tid]->inSyscall = true;
 212     this->commit.generateTCEvent(tid);
 213 }
 214
 215 #if FULL_SYSTEM
 216
 217 template <class Impl>
 218 void
 219 AlphaO3CPU<Impl>::post_interrupt(int int_num, int index)
 220 {
 221     BaseCPU::post_interrupt(int_num, index);
 222
 223     if (this->thread[0]->status() == ThreadContext::Suspended) {
 224         DPRINTF(IPI,"Suspended Processor awoke\n");
 225         this->threadContexts[0]->activate();
 226     }
 227 }
 228
 229 template <class Impl>
 230 Fault
 231 AlphaO3CPU<Impl>::hwrei(unsigned tid)
 232 {
 233     // Need to clear the lock flag upon returning from an interrupt.
 234     this->setMiscReg(TheISA::Lock_Flag_DepTag, false, tid);
 235
 236     this->thread[tid]->kernelStats->hwrei();
 237
 238     this->checkInterrupts = true;
 239
 240     // FIXME: XXX check for interrupts? XXX
 241     return NoFault;
 242 }
 243
 244 template <class Impl>
 245 bool
 246 AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
 247 {
 248     if (this->thread[tid]->kernelStats)
 249         this->thread[tid]->kernelStats->callpal(palFunc,
 250                                                 this->threadContexts[tid]);
 251
 252     switch (palFunc) {
 253       case PAL::halt:
 254         halt();
 255         if (--System::numSystemsRunning == 0)
 256             exitSimLoop("all cpus halted");
 257         break;
 258
 259       case PAL::bpt:
 260       case PAL::bugchk:
 261         if (this->system->breakpoint())
 262             return false;
 263         break;
 264     }
 265
 266     return true;
 267 }
 268
 269 template <class Impl>
 270 void
 271 AlphaO3CPU<Impl>::processInterrupts()
 272 {
 273     // Check for interrupts here.  For now can copy the code that
 274     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 275     // is the one that handles the interrupts.
 276     // @todo: Possibly consolidate the interrupt checking code.
 277     // @todo: Allow other threads to handle interrupts.
 278
 279     // Check if there are any outstanding interrupts
 280     //Handle the interrupts
 281     Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
 282
 283     if (interrupt != NoFault) {
 284         this->checkInterrupts = false;
 285         this->trap(interrupt, 0);
 286     }
 287 }
 288
 289 #endif // FULL_SYSTEM
 290
 291 template <class Impl>
 292 void
 293 AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
 294 {
 295     // Pass the thread's TC into the invoke method.
 296     fault->invoke(this->threadContexts[tid]);
 297 }
 298
 299 #if !FULL_SYSTEM
 300
 301 template <class Impl>
 302 void
 303 AlphaO3CPU<Impl>::syscall(int64_t callnum, int tid)
 304 {
 305     DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
 306
 307     DPRINTF(Activity,"Activity: syscall() called.\n");
 308
 309     // Temporarily increase this by one to account for the syscall
 310     // instruction.
 311     ++(this->thread[tid]->funcExeInst);
 312
 313     // Execute the actual syscall.
 314     this->thread[tid]->syscall(callnum);
 315
 316     // Decrease funcExeInst by one as the normal commit will handle
 317     // incrementing it.
 318     --(this->thread[tid]->funcExeInst);
 319 }
 320
 321 template <class Impl>
 322 TheISA::IntReg
 323 AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
 324 {
 325     return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
 326 }
 327
 328 template <class Impl>
 329 void
 330 AlphaO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
 331 {
 332     this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
 333 }
 334
 335 template <class Impl>
 336 void
 337 AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
 338 {
 339     // check for error condition.  Alpha syscall convention is to
 340     // indicate success/failure in reg a3 (r19) and put the
 341     // return value itself in the standard return value reg (v0).
 342     if (return_value.successful()) {
 343         // no error
 344         this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
 345         this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
 346     } else {
 347         // got an error, return details
 348         this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid);
 349         this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
 350     }
 351 }
 352 #endif