src/cpu/o3/alpha_dyn_inst.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__
  30 #define __CPU_O3_CPU_ALPHA_DYN_INST_HH__
  31
  32 #include "cpu/base_dyn_inst.hh"
  33 #include "cpu/o3/alpha_cpu.hh"
  34 #include "cpu/o3/alpha_impl.hh"
  35 #include "cpu/inst_seq.hh"
  36
  37 /**
  38  * Mostly implementation specific AlphaDynInst.  It is templated in case there
  39  * are other implementations that are similar enough to be able to use this
  40  * class without changes.  This is mainly useful if there are multiple similar
  41  * CPU implementations of the same ISA.
  42  */
  43
  44 template <class Impl>
  45 class AlphaDynInst : public BaseDynInst<Impl>
  46 {
  47   public:
  48     /** Typedef for the CPU. */
  49     typedef typename Impl::FullCPU FullCPU;
  50
  51     /** Binary machine instruction type. */
  52     typedef TheISA::MachInst MachInst;
  53     /** Logical register index type. */
  54     typedef TheISA::RegIndex RegIndex;
  55     /** Integer register index type. */
  56     typedef TheISA::IntReg   IntReg;
  57     /** Misc register index type. */
  58     typedef TheISA::MiscReg  MiscReg;
  59
  60     enum {
  61         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  62         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
  63     };
  64
  65   public:
  66     /** BaseDynInst constructor given a binary instruction. */
  67     AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
  68                  FullCPU *cpu);
  69
  70     /** BaseDynInst constructor given a static inst pointer. */
  71     AlphaDynInst(StaticInstPtr &_staticInst);
  72
  73     /** Executes the instruction.*/
  74     Fault execute()
  75     {
  76         return this->fault = this->staticInst->execute(this, this->traceData);
  77     }
  78
  79   public:
  80     MiscReg readMiscReg(int misc_reg)
  81     {
  82         // Dummy function for now.
  83         // @todo: Fix this once reg file gets fixed.
  84         return 0;
  85     }
  86
  87     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
  88     {
  89         // Dummy function for now.
  90         // @todo: Fix this once reg file gets fixed.
  91         return 0;
  92     }
  93
  94     Fault setMiscReg(int misc_reg, const MiscReg &val)
  95     {
  96         // Dummy function for now.
  97         // @todo: Fix this once reg file gets fixed.
  98         return NoFault;
  99     }
 100
 101     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 102     {
 103         // Dummy function for now.
 104         // @todo: Fix this once reg file gets fixed.
 105         return NoFault;
 106     }
 107
 108 #if FULL_SYSTEM
 109     Fault hwrei();
 110     int readIntrFlag();
 111     void setIntrFlag(int val);
 112     bool inPalMode();
 113     void trap(Fault fault);
 114     bool simPalCheck(int palFunc);
 115 #else
 116     void syscall();
 117 #endif
 118
 119
 120
 121   private:
 122     /** Physical register index of the destination registers of this
 123      *  instruction.
 124      */
 125     PhysRegIndex _destRegIdx[MaxInstDestRegs];
 126
 127     /** Physical register index of the source registers of this
 128      *  instruction.
 129      */
 130     PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
 131
 132     /** Physical register index of the previous producers of the
 133      *  architected destinations.
 134      */
 135     PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
 136
 137   public:
 138
 139     // The register accessor methods provide the index of the
 140     // instruction's operand (e.g., 0 or 1), not the architectural
 141     // register index, to simplify the implementation of register
 142     // renaming.  We find the architectural register index by indexing
 143     // into the instruction's own operand index table.  Note that a
 144     // raw pointer to the StaticInst is provided instead of a
 145     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 146     // long as these methods don't copy the pointer into any long-term
 147     // storage (which is pretty hard to imagine they would have reason
 148     // to do).
 149
 150     uint64_t readIntReg(const StaticInst *si, int idx)
 151     {
 152         return this->cpu->readIntReg(_srcRegIdx[idx]);
 153     }
 154
 155     FloatReg readFloatReg(const StaticInst *si, int idx, int width)
 156     {
 157         return this->cpu->readFloatReg(_srcRegIdx[idx], width);
 158     }
 159
 160     FloatReg readFloatReg(const StaticInst *si, int idx)
 161     {
 162         return this->cpu->readFloatReg(_srcRegIdx[idx]);
 163     }
 164
 165     FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
 166     {
 167         return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
 168     }
 169
 170     FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
 171     {
 172         return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
 173     }
 174
 175     /** @todo: Make results into arrays so they can handle multiple dest
 176      *  registers.
 177      */
 178     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 179     {
 180         this->cpu->setIntReg(_destRegIdx[idx], val);
 181         this->instResult.integer = val;
 182     }
 183
 184     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
 185     {
 186         this->cpu->setFloatReg(_destRegIdx[idx], val, width);
 187         this->instResult.fp = val;
 188     }
 189
 190     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
 191     {
 192         this->cpu->setFloatReg(_destRegIdx[idx], val);
 193         this->instResult.dbl = val;
 194     }
 195
 196     void setFloatRegBits(const StaticInst *si, int idx,
 197             FloatRegBits val, int width)
 198     {
 199         this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
 200         this->instResult.integer = val;
 201     }
 202
 203     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
 204     {
 205         this->cpu->setFloatRegBits(_destRegIdx[idx], val);
 206         this->instResult.integer = val;
 207     }
 208
 209     /** Returns the physical register index of the i'th destination
 210      *  register.
 211      */
 212     PhysRegIndex renamedDestRegIdx(int idx) const
 213     {
 214         return _destRegIdx[idx];
 215     }
 216
 217     /** Returns the physical register index of the i'th source register. */
 218     PhysRegIndex renamedSrcRegIdx(int idx) const
 219     {
 220         return _srcRegIdx[idx];
 221     }
 222
 223     /** Returns the physical register index of the previous physical register
 224      *  that remapped to the same logical register index.
 225      */
 226     PhysRegIndex prevDestRegIdx(int idx) const
 227     {
 228         return _prevDestRegIdx[idx];
 229     }
 230
 231     /** Renames a destination register to a physical register.  Also records
 232      *  the previous physical register that the logical register mapped to.
 233      */
 234     void renameDestReg(int idx,
 235                        PhysRegIndex renamed_dest,
 236                        PhysRegIndex previous_rename)
 237     {
 238         _destRegIdx[idx] = renamed_dest;
 239         _prevDestRegIdx[idx] = previous_rename;
 240     }
 241
 242     /** Renames a source logical register to the physical register which
 243      *  has/will produce that logical register's result.
 244      *  @todo: add in whether or not the source register is ready.
 245      */
 246     void renameSrcReg(int idx, PhysRegIndex renamed_src)
 247     {
 248         _srcRegIdx[idx] = renamed_src;
 249     }
 250
 251   public:
 252     Fault calcEA()
 253     {
 254         return this->staticInst->eaCompInst()->execute(this, this->traceData);
 255     }
 256
 257     Fault memAccess()
 258     {
 259         return this->staticInst->memAccInst()->execute(this, this->traceData);
 260     }
 261 };
 262
 263 #endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__
 264