src/cpu/o3/alpha_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "cpu/o3/alpha_dyn_inst.hh"
  32
  33 template <class Impl>
  34 AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
  35                                  InstSeqNum seq_num, FullCPU *cpu)
  36     : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
  37 {
  38     initVars();
  39 }
  40
  41 template <class Impl>
  42 AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
  43     : BaseDynInst<Impl>(_staticInst)
  44 {
  45     initVars();
  46 }
  47
  48 template <class Impl>
  49 void
  50 AlphaDynInst<Impl>::initVars()
  51 {
  52     // Make sure to have the renamed register entries set to the same
  53     // as the normal register entries.  It will allow the IQ to work
  54     // without any modifications.
  55     for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
  56         _destRegIdx[i] = this->staticInst->destRegIdx(i);
  57     }
  58
  59     for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
  60         _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
  61         this->_readySrcRegIdx[i] = 0;
  62     }
  63 }
  64
  65 template <class Impl>
  66 Fault
  67 AlphaDynInst<Impl>::execute()
  68 {
  69     // @todo: Pretty convoluted way to avoid squashing from happening
  70     // when using the XC during an instruction's execution
  71     // (specifically for instructions that have side-effects that use
  72     // the XC).  Fix this.
  73     bool in_syscall = this->thread->inSyscall;
  74     this->thread->inSyscall = true;
  75
  76     this->fault = this->staticInst->execute(this, this->traceData);
  77
  78     this->thread->inSyscall = in_syscall;
  79
  80     return this->fault;
  81 }
  82
  83 template <class Impl>
  84 Fault
  85 AlphaDynInst<Impl>::initiateAcc()
  86 {
  87     // @todo: Pretty convoluted way to avoid squashing from happening
  88     // when using the XC during an instruction's execution
  89     // (specifically for instructions that have side-effects that use
  90     // the XC).  Fix this.
  91     bool in_syscall = this->thread->inSyscall;
  92     this->thread->inSyscall = true;
  93
  94     this->fault = this->staticInst->initiateAcc(this, this->traceData);
  95
  96     this->thread->inSyscall = in_syscall;
  97
  98     return this->fault;
  99 }
 100
 101 template <class Impl>
 102 Fault
 103 AlphaDynInst<Impl>::completeAcc(Packet *pkt)
 104 {
 105     if (this->isLoad()) {
 106         this->fault = this->staticInst->completeAcc(pkt, this,
 107                                                     this->traceData);
 108     } else if (this->isStore()) {
 109         this->fault = this->staticInst->completeAcc(pkt, this,
 110                                                     this->traceData);
 111     } else {
 112         panic("Unknown type!");
 113     }
 114
 115     return this->fault;
 116 }
 117
 118 #if FULL_SYSTEM
 119 template <class Impl>
 120 Fault
 121 AlphaDynInst<Impl>::hwrei()
 122 {
 123     // Can only do a hwrei when in pal mode.
 124     if (!this->cpu->inPalMode(this->readPC()))
 125         return new AlphaISA::UnimplementedOpcodeFault;
 126
 127     // Set the next PC based on the value of the EXC_ADDR IPR.
 128     this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
 129                                            this->threadNumber));
 130
 131     // Tell CPU to clear any state it needs to if a hwrei is taken.
 132     this->cpu->hwrei(this->threadNumber);
 133
 134     // FIXME: XXX check for interrupts? XXX
 135     return NoFault;
 136 }
 137
 138 template <class Impl>
 139 int
 140 AlphaDynInst<Impl>::readIntrFlag()
 141 {
 142     return this->cpu->readIntrFlag();
 143 }
 144
 145 template <class Impl>
 146 void
 147 AlphaDynInst<Impl>::setIntrFlag(int val)
 148 {
 149     this->cpu->setIntrFlag(val);
 150 }
 151
 152 template <class Impl>
 153 bool
 154 AlphaDynInst<Impl>::inPalMode()
 155 {
 156     return this->cpu->inPalMode(this->PC);
 157 }
 158
 159 template <class Impl>
 160 void
 161 AlphaDynInst<Impl>::trap(Fault fault)
 162 {
 163     this->cpu->trap(fault, this->threadNumber);
 164 }
 165
 166 template <class Impl>
 167 bool
 168 AlphaDynInst<Impl>::simPalCheck(int palFunc)
 169 {
 170     return this->cpu->simPalCheck(palFunc, this->threadNumber);
 171 }
 172 #else
 173 template <class Impl>
 174 void
 175 AlphaDynInst<Impl>::syscall(int64_t callnum)
 176 {
 177     this->cpu->syscall(callnum, this->threadNumber);
 178 }
 179 #endif
 180