src/cpu/o3/alpha_params.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
  30 #define __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
  31
  32 #include "cpu/o3/cpu.hh"
  33
  34 //Forward declarations
  35 class System;
  36 class AlphaITB;
  37 class AlphaDTB;
  38 class FunctionalMemory;
  39 class Process;
  40 class MemInterface;
  41
  42 /**
  43  * This file defines the parameters that will be used for the AlphaFullCPU.
  44  * This must be defined externally so that the Impl can have a params class
  45  * defined that it can pass to all of the individual stages.
  46  */
  47
  48 class AlphaSimpleParams : public BaseFullCPU::Params
  49 {
  50   public:
  51
  52 #if FULL_SYSTEM
  53     AlphaITB *itb; AlphaDTB *dtb;
  54 #else
  55     std::vector<Process *> workload;
  56     Process *process;
  57 #endif // FULL_SYSTEM
  58
  59     FunctionalMemory *mem;
  60
  61     //
  62     // Caches
  63     //
  64     MemInterface *icacheInterface;
  65     MemInterface *dcacheInterface;
  66
  67     //
  68     // Fetch
  69     //
  70     unsigned decodeToFetchDelay;
  71     unsigned renameToFetchDelay;
  72     unsigned iewToFetchDelay;
  73     unsigned commitToFetchDelay;
  74     unsigned fetchWidth;
  75
  76     //
  77     // Decode
  78     //
  79     unsigned renameToDecodeDelay;
  80     unsigned iewToDecodeDelay;
  81     unsigned commitToDecodeDelay;
  82     unsigned fetchToDecodeDelay;
  83     unsigned decodeWidth;
  84
  85     //
  86     // Rename
  87     //
  88     unsigned iewToRenameDelay;
  89     unsigned commitToRenameDelay;
  90     unsigned decodeToRenameDelay;
  91     unsigned renameWidth;
  92
  93     //
  94     // IEW
  95     //
  96     unsigned commitToIEWDelay;
  97     unsigned renameToIEWDelay;
  98     unsigned issueToExecuteDelay;
  99     unsigned issueWidth;
 100     unsigned executeWidth;
 101     unsigned executeIntWidth;
 102     unsigned executeFloatWidth;
 103     unsigned executeBranchWidth;
 104     unsigned executeMemoryWidth;
 105
 106     //
 107     // Commit
 108     //
 109     unsigned iewToCommitDelay;
 110     unsigned renameToROBDelay;
 111     unsigned commitWidth;
 112     unsigned squashWidth;
 113
 114     //
 115     // Branch predictor (BP & BTB)
 116     //
 117 /*
 118     unsigned localPredictorSize;
 119     unsigned localPredictorCtrBits;
 120 */
 121
 122     unsigned local_predictor_size;
 123     unsigned local_ctr_bits;
 124     unsigned local_history_table_size;
 125     unsigned local_history_bits;
 126     unsigned global_predictor_size;
 127     unsigned global_ctr_bits;
 128     unsigned global_history_bits;
 129     unsigned choice_predictor_size;
 130     unsigned choice_ctr_bits;
 131
 132     unsigned BTBEntries;
 133     unsigned BTBTagSize;
 134
 135     unsigned RASSize;
 136
 137     //
 138     // Load store queue
 139     //
 140     unsigned LQEntries;
 141     unsigned SQEntries;
 142
 143     //
 144     // Memory dependence
 145     //
 146     unsigned SSITSize;
 147     unsigned LFSTSize;
 148
 149     //
 150     // Miscellaneous
 151     //
 152     unsigned numPhysIntRegs;
 153     unsigned numPhysFloatRegs;
 154     unsigned numIQEntries;
 155     unsigned numROBEntries;
 156
 157     // Probably can get this from somewhere.
 158     unsigned instShiftAmt;
 159
 160     bool defReg;
 161 };
 162
 163 #endif // __CPU_O3_CPU_ALPHA_PARAMS_HH__