src/cpu/o3/bpred_unit.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_O3_BPRED_UNIT_HH__
  44 #define __CPU_O3_BPRED_UNIT_HH__
  45
  46 #include <list>
  47
  48 #include "base/statistics.hh"
  49 #include "base/types.hh"
  50 #include "cpu/pred/2bit_local.hh"
  51 #include "cpu/pred/btb.hh"
  52 #include "cpu/pred/ras.hh"
  53 #include "cpu/pred/tournament.hh"
  54 #include "cpu/inst_seq.hh"
  55
  56 struct DerivO3CPUParams;
  57
  58 /**
  59  * Basically a wrapper class to hold both the branch predictor
  60  * and the BTB.
  61  */
  62 template<class Impl>
  63 class BPredUnit
  64 {
  65   private:
  66     typedef typename Impl::DynInstPtr DynInstPtr;
  67
  68     enum PredType {
  69         Local,
  70         Tournament
  71     };
  72
  73     PredType predictor;
  74
  75     const std::string _name;
  76
  77   public:
  78
  79     /**
  80      * @param params The params object, that has the size of the BP and BTB.
  81      */
  82     BPredUnit(DerivO3CPUParams *params);
  83
  84     const std::string &name() const { return _name; }
  85
  86     /**
  87      * Registers statistics.
  88      */
  89     void regStats();
  90
  91     void switchOut();
  92
  93     void takeOverFrom();
  94
  95     /**
  96      * Predicts whether or not the instruction is a taken branch, and the
  97      * target of the branch if it is taken.
  98      * @param inst The branch instruction.
  99      * @param PC The predicted PC is passed back through this parameter.
 100      * @param tid The thread id.
 101      * @return Returns if the branch is taken or not.
 102      */
 103     bool predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid);
 104
 105     // @todo: Rename this function.
 106     void BPUncond(void * &bp_history);
 107
 108     /**
 109      * Tells the branch predictor to commit any updates until the given
 110      * sequence number.
 111      * @param done_sn The sequence number to commit any older updates up until.
 112      * @param tid The thread id.
 113      */
 114     void update(const InstSeqNum &done_sn, ThreadID tid);
 115
 116     /**
 117      * Squashes all outstanding updates until a given sequence number.
 118      * @param squashed_sn The sequence number to squash any younger updates up
 119      * until.
 120      * @param tid The thread id.
 121      */
 122     void squash(const InstSeqNum &squashed_sn, ThreadID tid);
 123
 124     /**
 125      * Squashes all outstanding updates until a given sequence number, and
 126      * corrects that sn's update with the proper address and taken/not taken.
 127      * @param squashed_sn The sequence number to squash any younger updates up
 128      * until.
 129      * @param corr_target The correct branch target.
 130      * @param actually_taken The correct branch direction.
 131      * @param tid The thread id.
 132      */
 133     void squash(const InstSeqNum &squashed_sn,
 134                 const TheISA::PCState &corr_target,
 135                 bool actually_taken, ThreadID tid);
 136
 137     /**
 138      * @param bp_history Pointer to the history object.  The predictor
 139      * will need to update any state and delete the object.
 140      */
 141     void BPSquash(void *bp_history);
 142
 143     /**
 144      * Looks up a given PC in the BP to see if it is taken or not taken.
 145      * @param inst_PC The PC to look up.
 146      * @param bp_history Pointer that will be set to an object that
 147      * has the branch predictor state associated with the lookup.
 148      * @return Whether the branch is taken or not taken.
 149      */
 150     bool BPLookup(Addr instPC, void * &bp_history);
 151
 152      /**
 153      * If a branch is not taken, because the BTB address is invalid or missing,
 154      * this function sets the appropriate counter in the global and local
 155      * predictors to not taken.
 156      * @param inst_PC The PC to look up the local predictor.
 157      * @param bp_history Pointer that will be set to an object that
 158      * has the branch predictor state associated with the lookup.
 159      */
 160     void BPBTBUpdate(Addr instPC, void * &bp_history);
 161
 162     /**
 163      * Looks up a given PC in the BTB to see if a matching entry exists.
 164      * @param inst_PC The PC to look up.
 165      * @return Whether the BTB contains the given PC.
 166      */
 167     bool BTBValid(Addr instPC)
 168     { return BTB.valid(instPC, 0); }
 169
 170     /**
 171      * Looks up a given PC in the BTB to get the predicted target.
 172      * @param inst_PC The PC to look up.
 173      * @return The address of the target of the branch.
 174      */
 175     TheISA::PCState BTBLookup(Addr instPC)
 176     { return BTB.lookup(instPC, 0); }
 177
 178     /**
 179      * Updates the BP with taken/not taken information.
 180      * @param inst_PC The branch's PC that will be updated.
 181      * @param taken Whether the branch was taken or not taken.
 182      * @param bp_history Pointer to the branch predictor state that is
 183      * associated with the branch lookup that is being updated.
 184      * @param squashed Set to true when this function is called during a
 185      * squash operation.
 186      * @todo Make this update flexible enough to handle a global predictor.
 187      */
 188     void BPUpdate(Addr instPC, bool taken, void *bp_history, bool squashed);
 189
 190     /**
 191      * Updates the BTB with the target of a branch.
 192      * @param inst_PC The branch's PC that will be updated.
 193      * @param target_PC The branch's target that will be added to the BTB.
 194      */
 195     void BTBUpdate(Addr instPC, const TheISA::PCState &target)
 196     { BTB.update(instPC, target, 0); }
 197
 198     void dump();
 199
 200   private:
 201     struct PredictorHistory {
 202         /**
 203          * Makes a predictor history struct that contains any
 204          * information needed to update the predictor, BTB, and RAS.
 205          */
 206         PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
 207                          bool pred_taken, void *bp_history,
 208                          ThreadID _tid)
 209             : seqNum(seq_num), pc(instPC), bpHistory(bp_history), RASTarget(0),
 210               RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0), pushedRAS(0),
 211               wasCall(0), wasReturn(0), validBTB(0)
 212         {}
 213
 214         bool operator==(const PredictorHistory &entry) const {
 215             return this->seqNum == entry.seqNum;
 216         }
 217
 218         /** The sequence number for the predictor history entry. */
 219         InstSeqNum seqNum;
 220
 221         /** The PC associated with the sequence number. */
 222         Addr pc;
 223
 224         /** Pointer to the history object passed back from the branch
 225          * predictor.  It is used to update or restore state of the
 226          * branch predictor.
 227          */
 228         void *bpHistory;
 229
 230         /** The RAS target (only valid if a return). */
 231         TheISA::PCState RASTarget;
 232
 233         /** The RAS index of the instruction (only valid if a call). */
 234         unsigned RASIndex;
 235
 236         /** The thread id. */
 237         ThreadID tid;
 238
 239         /** Whether or not it was predicted taken. */
 240         bool predTaken;
 241
 242         /** Whether or not the RAS was used. */
 243         bool usedRAS;
 244
 245         /* Wether or not the RAS was pushed */
 246         bool pushedRAS;
 247
 248         /** Whether or not the instruction was a call. */
 249         bool wasCall;
 250
 251         /** Whether or not the instruction was a return. */
 252         bool wasReturn;
 253         /** Whether or not the instruction had a valid BTB entry. */
 254         bool validBTB;
 255     };
 256
 257     typedef std::list<PredictorHistory> History;
 258     typedef typename History::iterator HistoryIt;
 259
 260     /**
 261      * The per-thread predictor history. This is used to update the predictor
 262      * as instructions are committed, or restore it to the proper state after
 263      * a squash.
 264      */
 265     History predHist[Impl::MaxThreads];
 266
 267     /** The local branch predictor. */
 268     LocalBP *localBP;
 269
 270     /** The tournament branch predictor. */
 271     TournamentBP *tournamentBP;
 272
 273     /** The BTB. */
 274     DefaultBTB BTB;
 275
 276     /** The per-thread return address stack. */
 277     ReturnAddrStack RAS[Impl::MaxThreads];
 278
 279     /** Stat for number of BP lookups. */
 280     Stats::Scalar lookups;
 281     /** Stat for number of conditional branches predicted. */
 282     Stats::Scalar condPredicted;
 283     /** Stat for number of conditional branches predicted incorrectly. */
 284     Stats::Scalar condIncorrect;
 285     /** Stat for number of BTB lookups. */
 286     Stats::Scalar BTBLookups;
 287     /** Stat for number of BTB hits. */
 288     Stats::Scalar BTBHits;
 289     /** Stat for number of times the BTB is correct. */
 290     Stats::Scalar BTBCorrect;
 291     /** Stat for number of times the RAS is used to get a target. */
 292     Stats::Scalar usedRAS;
 293     /** Stat for number of times the RAS is incorrect. */
 294     Stats::Scalar RASIncorrect;
 295 };
 296
 297 #endif // __CPU_O3_BPRED_UNIT_HH__