Merge zizzer:/bk/newmem
[gem5.git] / src / cpu / o3 / checker_builder.cc
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31 #include <string>
32
33 #include "cpu/checker/cpu_impl.hh"
34 #include "cpu/inst_seq.hh"
35 #include "cpu/o3/alpha_dyn_inst.hh"
36 #include "cpu/o3/alpha_impl.hh"
37 #include "sim/builder.hh"
38 #include "sim/process.hh"
39 #include "sim/sim_object.hh"
40
41 class MemObject;
42
43 template
44 class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
45
46 /**
47 * Specific non-templated derived class used for SimObject configuration.
48 */
49 class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
50 {
51 public:
52 O3Checker(Params *p)
53 : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
54 { }
55 };
56
57 ////////////////////////////////////////////////////////////////////////
58 //
59 // CheckerCPU Simulation Object
60 //
61 BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
62
63 Param<Counter> max_insts_any_thread;
64 Param<Counter> max_insts_all_threads;
65 Param<Counter> max_loads_any_thread;
66 Param<Counter> max_loads_all_threads;
67
68 #if FULL_SYSTEM
69 SimObjectParam<AlphaITB *> itb;
70 SimObjectParam<AlphaDTB *> dtb;
71 SimObjectParam<System *> system;
72 Param<int> cpu_id;
73 Param<Tick> profile;
74 #else
75 SimObjectParam<Process *> workload;
76 #endif // FULL_SYSTEM
77 Param<int> clock;
78
79 Param<bool> defer_registration;
80 Param<bool> exitOnError;
81 Param<bool> warnOnlyOnLoadError;
82 Param<bool> function_trace;
83 Param<Tick> function_trace_start;
84
85 END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
86
87 BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
88
89 INIT_PARAM(max_insts_any_thread,
90 "terminate when any thread reaches this inst count"),
91 INIT_PARAM(max_insts_all_threads,
92 "terminate when all threads have reached this inst count"),
93 INIT_PARAM(max_loads_any_thread,
94 "terminate when any thread reaches this load count"),
95 INIT_PARAM(max_loads_all_threads,
96 "terminate when all threads have reached this load count"),
97
98 #if FULL_SYSTEM
99 INIT_PARAM(itb, "Instruction TLB"),
100 INIT_PARAM(dtb, "Data TLB"),
101 INIT_PARAM(system, "system object"),
102 INIT_PARAM(cpu_id, "processor ID"),
103 INIT_PARAM(profile, ""),
104 #else
105 INIT_PARAM(workload, "processes to run"),
106 #endif // FULL_SYSTEM
107
108 INIT_PARAM(clock, "clock speed"),
109
110 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
111 INIT_PARAM(exitOnError, "exit on error"),
112 INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
113 "result errors", false),
114 INIT_PARAM(function_trace, "Enable function trace"),
115 INIT_PARAM(function_trace_start, "Cycle to start function trace")
116
117 END_INIT_SIM_OBJECT_PARAMS(O3Checker)
118
119
120 CREATE_SIM_OBJECT(O3Checker)
121 {
122 O3Checker::Params *params = new O3Checker::Params();
123 params->name = getInstanceName();
124 params->numberOfThreads = 1;
125 params->max_insts_any_thread = 0;
126 params->max_insts_all_threads = 0;
127 params->max_loads_any_thread = 0;
128 params->max_loads_all_threads = 0;
129 params->exitOnError = exitOnError;
130 params->warnOnlyOnLoadError = warnOnlyOnLoadError;
131 params->deferRegistration = defer_registration;
132 params->functionTrace = function_trace;
133 params->functionTraceStart = function_trace_start;
134 params->clock = clock;
135 // Hack to touch all parameters. Consider not deriving Checker
136 // from BaseCPU..it's not really a CPU in the end.
137 Counter temp;
138 temp = max_insts_any_thread;
139 temp = max_insts_all_threads;
140 temp = max_loads_any_thread;
141 temp = max_loads_all_threads;
142
143 #if FULL_SYSTEM
144 params->itb = itb;
145 params->dtb = dtb;
146 params->system = system;
147 params->cpu_id = cpu_id;
148 params->profile = profile;
149 #else
150 params->process = workload;
151 #endif
152
153 O3Checker *cpu = new O3Checker(params);
154 return cpu;
155 }
156
157 REGISTER_SIM_OBJECT("O3Checker", O3Checker)