src/cpu/o3/checker_builder.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <string>
  32
  33 #include "cpu/checker/cpu_impl.hh"
  34 #include "cpu/inst_seq.hh"
  35 #include "cpu/o3/alpha/dyn_inst.hh"
  36 #include "cpu/o3/alpha/impl.hh"
  37 #include "sim/builder.hh"
  38 #include "sim/process.hh"
  39 #include "sim/sim_object.hh"
  40
  41 class MemObject;
  42
  43 template
  44 class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
  45
  46 /**
  47  * Specific non-templated derived class used for SimObject configuration.
  48  */
  49 class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
  50 {
  51   public:
  52     O3Checker(Params *p)
  53         : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
  54     { }
  55 };
  56
  57 ////////////////////////////////////////////////////////////////////////
  58 //
  59 //  CheckerCPU Simulation Object
  60 //
  61 BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
  62
  63     Param<Counter> max_insts_any_thread;
  64     Param<Counter> max_insts_all_threads;
  65     Param<Counter> max_loads_any_thread;
  66     Param<Counter> max_loads_all_threads;
  67     Param<Tick> progress_interval;
  68
  69 #if FULL_SYSTEM
  70     SimObjectParam<TheISA::ITB *> itb;
  71     SimObjectParam<TheISA::DTB *> dtb;
  72     SimObjectParam<System *> system;
  73     Param<int> cpu_id;
  74     Param<Tick> profile;
  75 #else
  76     SimObjectParam<Process *> workload;
  77 #endif // FULL_SYSTEM
  78     Param<int> clock;
  79
  80     Param<bool> defer_registration;
  81     Param<bool> exitOnError;
  82     Param<bool> updateOnError;
  83     Param<bool> warnOnlyOnLoadError;
  84     Param<bool> function_trace;
  85     Param<Tick> function_trace_start;
  86
  87 END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
  88
  89 BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
  90
  91     INIT_PARAM(max_insts_any_thread,
  92                "terminate when any thread reaches this inst count"),
  93     INIT_PARAM(max_insts_all_threads,
  94                "terminate when all threads have reached this inst count"),
  95     INIT_PARAM(max_loads_any_thread,
  96                "terminate when any thread reaches this load count"),
  97     INIT_PARAM(max_loads_all_threads,
  98                "terminate when all threads have reached this load count"),
  99     INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
 100
 101 #if FULL_SYSTEM
 102     INIT_PARAM(itb, "Instruction TLB"),
 103     INIT_PARAM(dtb, "Data TLB"),
 104     INIT_PARAM(system, "system object"),
 105     INIT_PARAM(cpu_id, "processor ID"),
 106     INIT_PARAM(profile, ""),
 107 #else
 108     INIT_PARAM(workload, "processes to run"),
 109 #endif // FULL_SYSTEM
 110
 111     INIT_PARAM(clock, "clock speed"),
 112
 113     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 114     INIT_PARAM(exitOnError, "exit on error"),
 115     INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
 116     INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
 117                     "result errors", false),
 118     INIT_PARAM(function_trace, "Enable function trace"),
 119     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 120
 121 END_INIT_SIM_OBJECT_PARAMS(O3Checker)
 122
 123
 124 CREATE_SIM_OBJECT(O3Checker)
 125 {
 126     O3Checker::Params *params = new O3Checker::Params();
 127     params->name = getInstanceName();
 128     params->numberOfThreads = 1;
 129     params->max_insts_any_thread = 0;
 130     params->max_insts_all_threads = 0;
 131     params->max_loads_any_thread = 0;
 132     params->max_loads_all_threads = 0;
 133     params->exitOnError = exitOnError;
 134     params->updateOnError = updateOnError;
 135     params->warnOnlyOnLoadError = warnOnlyOnLoadError;
 136     params->deferRegistration = defer_registration;
 137     params->functionTrace = function_trace;
 138     params->functionTraceStart = function_trace_start;
 139     params->clock = clock;
 140     // Hack to touch all parameters.  Consider not deriving Checker
 141     // from BaseCPU..it's not really a CPU in the end.
 142     Counter temp;
 143     temp = max_insts_any_thread;
 144     temp = max_insts_all_threads;
 145     temp = max_loads_any_thread;
 146     temp = max_loads_all_threads;
 147     Tick temp2 = progress_interval;
 148     params->progress_interval = 0;
 149     temp2++;
 150
 151 #if FULL_SYSTEM
 152     params->itb = itb;
 153     params->dtb = dtb;
 154     params->system = system;
 155     params->cpu_id = cpu_id;
 156     params->profile = profile;
 157 #else
 158     params->process = workload;
 159 #endif
 160
 161     O3Checker *cpu = new O3Checker(params);
 162     return cpu;
 163 }
 164
 165 REGISTER_SIM_OBJECT("O3Checker", O3Checker)