src/cpu/o3/comm.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_O3_COMM_HH__
  44 #define __CPU_O3_COMM_HH__
  45
  46 #include <vector>
  47
  48 #include "arch/types.hh"
  49 #include "base/types.hh"
  50 #include "cpu/inst_seq.hh"
  51 #include "sim/faults.hh"
  52
  53 // Typedef for physical register index type. Although the Impl would be the
  54 // most likely location for this, there are a few classes that need this
  55 // typedef yet are not templated on the Impl. For now it will be defined here.
  56 typedef short int PhysRegIndex;
  57
  58 /** Struct that defines the information passed from fetch to decode. */
  59 template<class Impl>
  60 struct DefaultFetchDefaultDecode {
  61     typedef typename Impl::DynInstPtr DynInstPtr;
  62
  63     int size;
  64
  65     DynInstPtr insts[Impl::MaxWidth];
  66     Fault fetchFault;
  67     InstSeqNum fetchFaultSN;
  68     bool clearFetchFault;
  69 };
  70
  71 /** Struct that defines the information passed from decode to rename. */
  72 template<class Impl>
  73 struct DefaultDecodeDefaultRename {
  74     typedef typename Impl::DynInstPtr DynInstPtr;
  75
  76     int size;
  77
  78     DynInstPtr insts[Impl::MaxWidth];
  79 };
  80
  81 /** Struct that defines the information passed from rename to IEW. */
  82 template<class Impl>
  83 struct DefaultRenameDefaultIEW {
  84     typedef typename Impl::DynInstPtr DynInstPtr;
  85
  86     int size;
  87
  88     DynInstPtr insts[Impl::MaxWidth];
  89 };
  90
  91 /** Struct that defines the information passed from IEW to commit. */
  92 template<class Impl>
  93 struct DefaultIEWDefaultCommit {
  94     typedef typename Impl::DynInstPtr DynInstPtr;
  95
  96     int size;
  97
  98     DynInstPtr insts[Impl::MaxWidth];
  99
 100     bool squash[Impl::MaxThreads];
 101     bool branchMispredict[Impl::MaxThreads];
 102     DynInstPtr mispredictInst[Impl::MaxThreads];
 103     bool branchTaken[Impl::MaxThreads];
 104     Addr mispredPC[Impl::MaxThreads];
 105     TheISA::PCState pc[Impl::MaxThreads];
 106     InstSeqNum squashedSeqNum[Impl::MaxThreads];
 107
 108     bool includeSquashInst[Impl::MaxThreads];
 109 };
 110
 111 template<class Impl>
 112 struct IssueStruct {
 113     typedef typename Impl::DynInstPtr DynInstPtr;
 114
 115     int size;
 116
 117     DynInstPtr insts[Impl::MaxWidth];
 118 };
 119
 120 /** Struct that defines all backwards communication. */
 121 template<class Impl>
 122 struct TimeBufStruct {
 123     typedef typename Impl::DynInstPtr DynInstPtr;
 124     struct decodeComm {
 125         bool squash;
 126         bool predIncorrect;
 127         uint64_t branchAddr;
 128
 129         InstSeqNum doneSeqNum;
 130
 131         // @todo: Might want to package this kind of branch stuff into a single
 132         // struct as it is used pretty frequently.
 133         bool branchMispredict;
 134         DynInstPtr mispredictInst;
 135         bool branchTaken;
 136         Addr mispredPC;
 137         TheISA::PCState nextPC;
 138         DynInstPtr squashInst;
 139         unsigned branchCount;
 140     };
 141
 142     decodeComm decodeInfo[Impl::MaxThreads];
 143
 144     struct renameComm {
 145     };
 146
 147     renameComm renameInfo[Impl::MaxThreads];
 148
 149     struct iewComm {
 150         // Also eventually include skid buffer space.
 151         bool usedIQ;
 152         unsigned freeIQEntries;
 153         bool usedLSQ;
 154         unsigned freeLSQEntries;
 155
 156         unsigned iqCount;
 157         unsigned ldstqCount;
 158
 159         unsigned dispatched;
 160         unsigned dispatchedToLSQ;
 161     };
 162
 163     iewComm iewInfo[Impl::MaxThreads];
 164
 165     struct commitComm {
 166
 167         /////////////// For Decode, IEW, Rename, Fetch ///////////
 168         bool squash;
 169         bool robSquashing;
 170
 171         ////////// For Fetch & IEW /////////////
 172         // Represents the instruction that has either been retired or
 173         // squashed.  Similar to having a single bus that broadcasts the
 174         // retired or squashed sequence number.
 175         InstSeqNum doneSeqNum;
 176
 177         ////////////// For Rename /////////////////
 178         // Rename should re-read number of free rob entries
 179         bool usedROB;
 180         // Notify Rename that the ROB is empty
 181         bool emptyROB;
 182         // Tell Rename how many free entries it has in the ROB
 183         unsigned freeROBEntries;
 184
 185
 186         ///////////// For Fetch //////////////////
 187         // Provide fetch the instruction that mispredicted, if this
 188         // pointer is not-null a misprediction occured
 189         DynInstPtr mispredictInst;
 190         // Was the branch taken or not
 191         bool branchTaken;
 192         // The pc of the next instruction to execute. This is the next
 193         // instruction for a branch mispredict, but the same instruction for
 194         // order violation and the like
 195         TheISA::PCState pc;
 196
 197         // Instruction that caused the a non-mispredict squash
 198         DynInstPtr squashInst;
 199         // If an interrupt is pending and fetch should stall
 200         bool interruptPending;
 201         // If the interrupt ended up being cleared before being handled
 202         bool clearInterrupt;
 203
 204         //////////// For IEW //////////////////
 205         // Communication specifically to the IQ to tell the IQ that it can
 206         // schedule a non-speculative instruction.
 207         InstSeqNum nonSpecSeqNum;
 208
 209         // Hack for now to send back an uncached access to the IEW stage.
 210         bool uncached;
 211         DynInstPtr uncachedLoad;
 212
 213     };
 214
 215     commitComm commitInfo[Impl::MaxThreads];
 216
 217     bool decodeBlock[Impl::MaxThreads];
 218     bool decodeUnblock[Impl::MaxThreads];
 219     bool renameBlock[Impl::MaxThreads];
 220     bool renameUnblock[Impl::MaxThreads];
 221     bool iewBlock[Impl::MaxThreads];
 222     bool iewUnblock[Impl::MaxThreads];
 223     bool commitBlock[Impl::MaxThreads];
 224     bool commitUnblock[Impl::MaxThreads];
 225 };
 226
 227 #endif //__CPU_O3_COMM_HH__