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43 #ifndef __CPU_O3_COMM_HH__
44 #define __CPU_O3_COMM_HH__
48 #include "arch/types.hh"
49 #include "base/types.hh"
50 #include "cpu/inst_seq.hh"
51 #include "sim/faults.hh"
53 // Typedef for physical register index type. Although the Impl would be the
54 // most likely location for this, there are a few classes that need this
55 // typedef yet are not templated on the Impl. For now it will be defined here.
56 typedef short int PhysRegIndex;
58 /** Struct that defines the information passed from fetch to decode. */
60 struct DefaultFetchDefaultDecode {
61 typedef typename Impl::DynInstPtr DynInstPtr;
65 DynInstPtr insts[Impl::MaxWidth];
67 InstSeqNum fetchFaultSN;
71 /** Struct that defines the information passed from decode to rename. */
73 struct DefaultDecodeDefaultRename {
74 typedef typename Impl::DynInstPtr DynInstPtr;
78 DynInstPtr insts[Impl::MaxWidth];
81 /** Struct that defines the information passed from rename to IEW. */
83 struct DefaultRenameDefaultIEW {
84 typedef typename Impl::DynInstPtr DynInstPtr;
88 DynInstPtr insts[Impl::MaxWidth];
91 /** Struct that defines the information passed from IEW to commit. */
93 struct DefaultIEWDefaultCommit {
94 typedef typename Impl::DynInstPtr DynInstPtr;
98 DynInstPtr insts[Impl::MaxWidth];
99 DynInstPtr mispredictInst[Impl::MaxThreads];
100 Addr mispredPC[Impl::MaxThreads];
101 InstSeqNum squashedSeqNum[Impl::MaxThreads];
102 TheISA::PCState pc[Impl::MaxThreads];
104 bool squash[Impl::MaxThreads];
105 bool branchMispredict[Impl::MaxThreads];
106 bool branchTaken[Impl::MaxThreads];
107 bool includeSquashInst[Impl::MaxThreads];
112 typedef typename Impl::DynInstPtr DynInstPtr;
116 DynInstPtr insts[Impl::MaxWidth];
119 /** Struct that defines all backwards communication. */
121 struct TimeBufStruct {
122 typedef typename Impl::DynInstPtr DynInstPtr;
125 InstSeqNum doneSeqNum;
126 DynInstPtr mispredictInst;
127 DynInstPtr squashInst;
129 TheISA::PCState nextPC;
130 unsigned branchCount;
133 bool branchMispredict;
137 decodeComm decodeInfo[Impl::MaxThreads];
142 renameComm renameInfo[Impl::MaxThreads];
145 // Also eventually include skid buffer space.
147 unsigned freeIQEntries;
149 unsigned freeLSQEntries;
155 unsigned dispatchedToLSQ;
158 iewComm iewInfo[Impl::MaxThreads];
162 /////////////// For Decode, IEW, Rename, Fetch ///////////
166 ////////// For Fetch & IEW /////////////
167 // Represents the instruction that has either been retired or
168 // squashed. Similar to having a single bus that broadcasts the
169 // retired or squashed sequence number.
170 InstSeqNum doneSeqNum;
172 ////////////// For Rename /////////////////
173 // Rename should re-read number of free rob entries
175 // Notify Rename that the ROB is empty
177 // Tell Rename how many free entries it has in the ROB
178 unsigned freeROBEntries;
181 ///////////// For Fetch //////////////////
182 // Provide fetch the instruction that mispredicted, if this
183 // pointer is not-null a misprediction occured
184 DynInstPtr mispredictInst;
185 // Was the branch taken or not
187 // The pc of the next instruction to execute. This is the next
188 // instruction for a branch mispredict, but the same instruction for
189 // order violation and the like
192 // Instruction that caused the a non-mispredict squash
193 DynInstPtr squashInst;
194 // If an interrupt is pending and fetch should stall
195 bool interruptPending;
196 // If the interrupt ended up being cleared before being handled
199 //////////// For IEW //////////////////
200 // Communication specifically to the IQ to tell the IQ that it can
201 // schedule a non-speculative instruction.
202 InstSeqNum nonSpecSeqNum;
204 // Hack for now to send back an uncached access to the IEW stage.
206 DynInstPtr uncachedLoad;
210 commitComm commitInfo[Impl::MaxThreads];
212 bool decodeBlock[Impl::MaxThreads];
213 bool decodeUnblock[Impl::MaxThreads];
214 bool renameBlock[Impl::MaxThreads];
215 bool renameUnblock[Impl::MaxThreads];
216 bool iewBlock[Impl::MaxThreads];
217 bool iewUnblock[Impl::MaxThreads];
218 bool commitBlock[Impl::MaxThreads];
219 bool commitUnblock[Impl::MaxThreads];
222 #endif //__CPU_O3_COMM_HH__