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43 #ifndef __CPU_O3_COMM_HH__
44 #define __CPU_O3_COMM_HH__
48 #include "arch/types.hh"
49 #include "base/types.hh"
50 #include "cpu/inst_seq.hh"
51 #include "sim/faults.hh"
53 // Typedef for physical register index type. Although the Impl would be the
54 // most likely location for this, there are a few classes that need this
55 // typedef yet are not templated on the Impl. For now it will be defined here.
56 typedef short int PhysRegIndex;
58 /** Struct that defines the information passed from fetch to decode. */
60 struct DefaultFetchDefaultDecode {
61 typedef typename Impl::DynInstPtr DynInstPtr;
65 DynInstPtr insts[Impl::MaxWidth];
67 InstSeqNum fetchFaultSN;
71 /** Struct that defines the information passed from decode to rename. */
73 struct DefaultDecodeDefaultRename {
74 typedef typename Impl::DynInstPtr DynInstPtr;
78 DynInstPtr insts[Impl::MaxWidth];
81 /** Struct that defines the information passed from rename to IEW. */
83 struct DefaultRenameDefaultIEW {
84 typedef typename Impl::DynInstPtr DynInstPtr;
88 DynInstPtr insts[Impl::MaxWidth];
91 /** Struct that defines the information passed from IEW to commit. */
93 struct DefaultIEWDefaultCommit {
94 typedef typename Impl::DynInstPtr DynInstPtr;
98 DynInstPtr insts[Impl::MaxWidth];
99 DynInstPtr mispredictInst[Impl::MaxThreads];
100 Addr mispredPC[Impl::MaxThreads];
101 InstSeqNum squashedSeqNum[Impl::MaxThreads];
102 TheISA::PCState pc[Impl::MaxThreads];
104 bool squash[Impl::MaxThreads];
105 bool branchMispredict[Impl::MaxThreads];
106 bool branchTaken[Impl::MaxThreads];
107 bool includeSquashInst[Impl::MaxThreads];
112 typedef typename Impl::DynInstPtr DynInstPtr;
116 DynInstPtr insts[Impl::MaxWidth];
119 /** Struct that defines all backwards communication. */
121 struct TimeBufStruct {
122 typedef typename Impl::DynInstPtr DynInstPtr;
124 TheISA::PCState nextPC;
125 DynInstPtr mispredictInst;
126 DynInstPtr squashInst;
127 InstSeqNum doneSeqNum;
130 unsigned branchCount;
133 bool branchMispredict;
137 decodeComm decodeInfo[Impl::MaxThreads];
142 renameComm renameInfo[Impl::MaxThreads];
145 // Also eventually include skid buffer space.
146 unsigned freeIQEntries;
147 unsigned freeLSQEntries;
153 unsigned dispatchedToLSQ;
158 iewComm iewInfo[Impl::MaxThreads];
161 /////////////////////////////////////////////////////////////////////
162 // This code has been re-structured for better packing of variables
163 // instead of by stage which is the more logical way to arrange the
169 // As such each member is annotated with who consumes it
170 // e.g. bool variable name // *F,R for Fetch and Rename
171 /////////////////////////////////////////////////////////////////////
173 /// The pc of the next instruction to execute. This is the next
174 /// instruction for a branch mispredict, but the same instruction for
175 /// order violation and the like
176 TheISA::PCState pc; // *F
178 /// Provide fetch the instruction that mispredicted, if this
179 /// pointer is not-null a misprediction occured
180 DynInstPtr mispredictInst; // *F
182 /// Instruction that caused the a non-mispredict squash
183 DynInstPtr squashInst; // *F
185 /// Hack for now to send back an uncached access to the IEW stage.
186 DynInstPtr uncachedLoad; // *I
188 /// Communication specifically to the IQ to tell the IQ that it can
189 /// schedule a non-speculative instruction.
190 InstSeqNum nonSpecSeqNum; // *I
192 /// Represents the instruction that has either been retired or
193 /// squashed. Similar to having a single bus that broadcasts the
194 /// retired or squashed sequence number.
195 InstSeqNum doneSeqNum; // *F, I
197 /// Tell Rename how many free entries it has in the ROB
198 unsigned freeROBEntries; // *R
200 bool squash; // *F, D, R, I
201 bool robSquashing; // *F, D, R, I
203 /// Rename should re-read number of free rob entries
206 /// Notify Rename that the ROB is empty
209 /// Was the branch taken or not
210 bool branchTaken; // *F
211 /// If an interrupt is pending and fetch should stall
212 bool interruptPending; // *F
213 /// If the interrupt ended up being cleared before being handled
214 bool clearInterrupt; // *F
216 /// Hack for now to send back an uncached access to the IEW stage.
221 commitComm commitInfo[Impl::MaxThreads];
223 bool decodeBlock[Impl::MaxThreads];
224 bool decodeUnblock[Impl::MaxThreads];
225 bool renameBlock[Impl::MaxThreads];
226 bool renameUnblock[Impl::MaxThreads];
227 bool iewBlock[Impl::MaxThreads];
228 bool iewUnblock[Impl::MaxThreads];
229 bool commitBlock[Impl::MaxThreads];
230 bool commitUnblock[Impl::MaxThreads];
233 #endif //__CPU_O3_COMM_HH__