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31 #ifndef __CPU_O3_COMM_HH__
32 #define __CPU_O3_COMM_HH__
36 #include "sim/faults.hh"
37 #include "cpu/inst_seq.hh"
38 #include "sim/host.hh"
40 // Typedef for physical register index type. Although the Impl would be the
41 // most likely location for this, there are a few classes that need this
42 // typedef yet are not templated on the Impl. For now it will be defined here.
43 typedef short int PhysRegIndex;
45 /** Struct that defines the information passed from fetch to decode. */
47 struct DefaultFetchDefaultDecode {
48 typedef typename Impl::DynInstPtr DynInstPtr;
52 DynInstPtr insts[Impl::MaxWidth];
54 InstSeqNum fetchFaultSN;
58 /** Struct that defines the information passed from decode to rename. */
60 struct DefaultDecodeDefaultRename {
61 typedef typename Impl::DynInstPtr DynInstPtr;
65 DynInstPtr insts[Impl::MaxWidth];
68 /** Struct that defines the information passed from rename to IEW. */
70 struct DefaultRenameDefaultIEW {
71 typedef typename Impl::DynInstPtr DynInstPtr;
75 DynInstPtr insts[Impl::MaxWidth];
78 /** Struct that defines the information passed from IEW to commit. */
80 struct DefaultIEWDefaultCommit {
81 typedef typename Impl::DynInstPtr DynInstPtr;
85 DynInstPtr insts[Impl::MaxWidth];
87 bool squash[Impl::MaxThreads];
88 bool branchMispredict[Impl::MaxThreads];
89 bool branchTaken[Impl::MaxThreads];
90 bool squashDelaySlot[Impl::MaxThreads];
91 uint64_t mispredPC[Impl::MaxThreads];
92 uint64_t nextPC[Impl::MaxThreads];
93 uint64_t nextNPC[Impl::MaxThreads];
94 InstSeqNum squashedSeqNum[Impl::MaxThreads];
96 bool includeSquashInst[Impl::MaxThreads];
101 typedef typename Impl::DynInstPtr DynInstPtr;
105 DynInstPtr insts[Impl::MaxWidth];
108 /** Struct that defines all backwards communication. */
110 struct TimeBufStruct {
116 InstSeqNum doneSeqNum;
117 InstSeqNum bdelayDoneSeqNum;
119 // @todo: Might want to package this kind of branch stuff into a single
120 // struct as it is used pretty frequently.
121 bool branchMispredict;
127 unsigned branchCount;
130 decodeComm decodeInfo[Impl::MaxThreads];
135 renameComm renameInfo[Impl::MaxThreads];
138 // Also eventually include skid buffer space.
140 unsigned freeIQEntries;
142 unsigned freeLSQEntries;
148 unsigned dispatchedToLSQ;
151 iewComm iewInfo[Impl::MaxThreads];
155 unsigned freeROBEntries;
161 bool branchMispredict;
167 // Represents the instruction that has either been retired or
168 // squashed. Similar to having a single bus that broadcasts the
169 // retired or squashed sequence number.
170 InstSeqNum doneSeqNum;
172 InstSeqNum bdelayDoneSeqNum;
173 bool squashDelaySlot;
175 //Just in case we want to do a commit/squash on a cycle
176 //(necessary for multiple ROBs?)
178 InstSeqNum squashSeqNum;
180 // Communication specifically to the IQ to tell the IQ that it can
181 // schedule a non-speculative instruction.
182 InstSeqNum nonSpecSeqNum;
184 // Hack for now to send back an uncached access to the IEW stage.
185 typedef typename Impl::DynInstPtr DynInstPtr;
187 DynInstPtr uncachedLoad;
189 bool interruptPending;
193 commitComm commitInfo[Impl::MaxThreads];
195 bool decodeBlock[Impl::MaxThreads];
196 bool decodeUnblock[Impl::MaxThreads];
197 bool renameBlock[Impl::MaxThreads];
198 bool renameUnblock[Impl::MaxThreads];
199 bool iewBlock[Impl::MaxThreads];
200 bool iewUnblock[Impl::MaxThreads];
201 bool commitBlock[Impl::MaxThreads];
202 bool commitUnblock[Impl::MaxThreads];
205 #endif //__CPU_O3_COMM_HH__