src/cpu/o3/comm.hh

   1 /*
   2  * Copyright (c) 2011, 2016-2017 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_O3_COMM_HH__
  43 #define __CPU_O3_COMM_HH__
  44
  45 #include <vector>
  46
  47 #include "arch/types.hh"
  48 #include "base/types.hh"
  49 #include "cpu/inst_seq.hh"
  50 #include "sim/faults.hh"
  51
  52 /** Struct that defines the information passed from fetch to decode. */
  53 template<class Impl>
  54 struct DefaultFetchDefaultDecode {
  55     typedef typename Impl::DynInstPtr DynInstPtr;
  56
  57     int size;
  58
  59     DynInstPtr insts[Impl::MaxWidth];
  60     Fault fetchFault;
  61     InstSeqNum fetchFaultSN;
  62     bool clearFetchFault;
  63 };
  64
  65 /** Struct that defines the information passed from decode to rename. */
  66 template<class Impl>
  67 struct DefaultDecodeDefaultRename {
  68     typedef typename Impl::DynInstPtr DynInstPtr;
  69
  70     int size;
  71
  72     DynInstPtr insts[Impl::MaxWidth];
  73 };
  74
  75 /** Struct that defines the information passed from rename to IEW. */
  76 template<class Impl>
  77 struct DefaultRenameDefaultIEW {
  78     typedef typename Impl::DynInstPtr DynInstPtr;
  79
  80     int size;
  81
  82     DynInstPtr insts[Impl::MaxWidth];
  83 };
  84
  85 /** Struct that defines the information passed from IEW to commit. */
  86 template<class Impl>
  87 struct DefaultIEWDefaultCommit {
  88     typedef typename Impl::DynInstPtr DynInstPtr;
  89
  90     int size;
  91
  92     DynInstPtr insts[Impl::MaxWidth];
  93     DynInstPtr mispredictInst[Impl::MaxThreads];
  94     Addr mispredPC[Impl::MaxThreads];
  95     InstSeqNum squashedSeqNum[Impl::MaxThreads];
  96     TheISA::PCState pc[Impl::MaxThreads];
  97
  98     bool squash[Impl::MaxThreads];
  99     bool branchMispredict[Impl::MaxThreads];
 100     bool branchTaken[Impl::MaxThreads];
 101     bool includeSquashInst[Impl::MaxThreads];
 102 };
 103
 104 template<class Impl>
 105 struct IssueStruct {
 106     typedef typename Impl::DynInstPtr DynInstPtr;
 107
 108     int size;
 109
 110     DynInstPtr insts[Impl::MaxWidth];
 111 };
 112
 113 /** Struct that defines all backwards communication. */
 114 template<class Impl>
 115 struct TimeBufStruct {
 116     typedef typename Impl::DynInstPtr DynInstPtr;
 117     struct decodeComm {
 118         TheISA::PCState nextPC;
 119         DynInstPtr mispredictInst;
 120         DynInstPtr squashInst;
 121         InstSeqNum doneSeqNum;
 122         Addr mispredPC;
 123         uint64_t branchAddr;
 124         unsigned branchCount;
 125         bool squash;
 126         bool predIncorrect;
 127         bool branchMispredict;
 128         bool branchTaken;
 129     };
 130
 131     decodeComm decodeInfo[Impl::MaxThreads];
 132
 133     struct renameComm {
 134     };
 135
 136     renameComm renameInfo[Impl::MaxThreads];
 137
 138     struct iewComm {
 139         // Also eventually include skid buffer space.
 140         unsigned freeIQEntries;
 141         unsigned freeLQEntries;
 142         unsigned freeSQEntries;
 143         unsigned dispatchedToLQ;
 144         unsigned dispatchedToSQ;
 145
 146         unsigned iqCount;
 147         unsigned ldstqCount;
 148
 149         unsigned dispatched;
 150         bool usedIQ;
 151         bool usedLSQ;
 152     };
 153
 154     iewComm iewInfo[Impl::MaxThreads];
 155
 156     struct commitComm {
 157         /////////////////////////////////////////////////////////////////////
 158         // This code has been re-structured for better packing of variables
 159         // instead of by stage which is the more logical way to arrange the
 160         // data.
 161         // F = Fetch
 162         // D = Decode
 163         // I = IEW
 164         // R = Rename
 165         // As such each member is annotated with who consumes it
 166         // e.g. bool variable name // *F,R for Fetch and Rename
 167         /////////////////////////////////////////////////////////////////////
 168
 169         /// The pc of the next instruction to execute. This is the next
 170         /// instruction for a branch mispredict, but the same instruction for
 171         /// order violation and the like
 172         TheISA::PCState pc; // *F
 173
 174         /// Provide fetch the instruction that mispredicted, if this
 175         /// pointer is not-null a misprediction occured
 176         DynInstPtr mispredictInst;  // *F
 177
 178         /// Instruction that caused the a non-mispredict squash
 179         DynInstPtr squashInst; // *F
 180
 181         /// Hack for now to send back a strictly ordered access to the
 182         /// IEW stage.
 183         DynInstPtr strictlyOrderedLoad; // *I
 184
 185         /// Communication specifically to the IQ to tell the IQ that it can
 186         /// schedule a non-speculative instruction.
 187         InstSeqNum nonSpecSeqNum; // *I
 188
 189         /// Represents the instruction that has either been retired or
 190         /// squashed.  Similar to having a single bus that broadcasts the
 191         /// retired or squashed sequence number.
 192         InstSeqNum doneSeqNum; // *F, I
 193
 194         /// Tell Rename how many free entries it has in the ROB
 195         unsigned freeROBEntries; // *R
 196
 197         bool squash; // *F, D, R, I
 198         bool robSquashing; // *F, D, R, I
 199
 200         /// Rename should re-read number of free rob entries
 201         bool usedROB; // *R
 202
 203         /// Notify Rename that the ROB is empty
 204         bool emptyROB; // *R
 205
 206         /// Was the branch taken or not
 207         bool branchTaken; // *F
 208         /// If an interrupt is pending and fetch should stall
 209         bool interruptPending; // *F
 210         /// If the interrupt ended up being cleared before being handled
 211         bool clearInterrupt; // *F
 212
 213         /// Hack for now to send back an strictly ordered access to
 214         /// the IEW stage.
 215         bool strictlyOrdered; // *I
 216
 217     };
 218
 219     commitComm commitInfo[Impl::MaxThreads];
 220
 221     bool decodeBlock[Impl::MaxThreads];
 222     bool decodeUnblock[Impl::MaxThreads];
 223     bool renameBlock[Impl::MaxThreads];
 224     bool renameUnblock[Impl::MaxThreads];
 225     bool iewBlock[Impl::MaxThreads];
 226     bool iewUnblock[Impl::MaxThreads];
 227 };
 228
 229 #endif //__CPU_O3_COMM_HH__