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31 #ifndef __CPU_O3_COMM_HH__
32 #define __CPU_O3_COMM_HH__
36 #include "arch/faults.hh"
37 #include "arch/isa_traits.hh"
38 #include "cpu/inst_seq.hh"
39 #include "sim/host.hh"
41 // Typedef for physical register index type. Although the Impl would be the
42 // most likely location for this, there are a few classes that need this
43 // typedef yet are not templated on the Impl. For now it will be defined here.
44 typedef short int PhysRegIndex;
46 /** Struct that defines the information passed from fetch to decode. */
48 struct DefaultFetchDefaultDecode {
49 typedef typename Impl::DynInstPtr DynInstPtr;
53 DynInstPtr insts[Impl::MaxWidth];
55 InstSeqNum fetchFaultSN;
59 /** Struct that defines the information passed from decode to rename. */
61 struct DefaultDecodeDefaultRename {
62 typedef typename Impl::DynInstPtr DynInstPtr;
66 DynInstPtr insts[Impl::MaxWidth];
69 /** Struct that defines the information passed from rename to IEW. */
71 struct DefaultRenameDefaultIEW {
72 typedef typename Impl::DynInstPtr DynInstPtr;
76 DynInstPtr insts[Impl::MaxWidth];
79 /** Struct that defines the information passed from IEW to commit. */
81 struct DefaultIEWDefaultCommit {
82 typedef typename Impl::DynInstPtr DynInstPtr;
86 DynInstPtr insts[Impl::MaxWidth];
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
91 bool condDelaySlotBranch[Impl::MaxThreads];
92 uint64_t mispredPC[Impl::MaxThreads];
93 uint64_t nextPC[Impl::MaxThreads];
94 InstSeqNum squashedSeqNum[Impl::MaxThreads];
96 bool includeSquashInst[Impl::MaxThreads];
101 typedef typename Impl::DynInstPtr DynInstPtr;
105 DynInstPtr insts[Impl::MaxWidth];
108 /** Struct that defines all backwards communication. */
110 struct TimeBufStruct {
116 InstSeqNum doneSeqNum;
117 InstSeqNum bdelayDoneSeqNum;
119 // @todo: Might want to package this kind of branch stuff into a single
120 // struct as it is used pretty frequently.
121 bool branchMispredict;
126 unsigned branchCount;
129 decodeComm decodeInfo[Impl::MaxThreads];
134 renameComm renameInfo[Impl::MaxThreads];
137 // Also eventually include skid buffer space.
139 unsigned freeIQEntries;
141 unsigned freeLSQEntries;
147 unsigned dispatchedToLSQ;
150 iewComm iewInfo[Impl::MaxThreads];
154 unsigned freeROBEntries;
160 bool branchMispredict;
165 // Represents the instruction that has either been retired or
166 // squashed. Similar to having a single bus that broadcasts the
167 // retired or squashed sequence number.
168 InstSeqNum doneSeqNum;
170 InstSeqNum bdelayDoneSeqNum;
171 bool squashDelaySlot;
173 //Just in case we want to do a commit/squash on a cycle
174 //(necessary for multiple ROBs?)
176 InstSeqNum squashSeqNum;
178 // Communication specifically to the IQ to tell the IQ that it can
179 // schedule a non-speculative instruction.
180 InstSeqNum nonSpecSeqNum;
182 // Hack for now to send back an uncached access to the IEW stage.
183 typedef typename Impl::DynInstPtr DynInstPtr;
185 DynInstPtr uncachedLoad;
187 bool interruptPending;
191 commitComm commitInfo[Impl::MaxThreads];
193 bool decodeBlock[Impl::MaxThreads];
194 bool decodeUnblock[Impl::MaxThreads];
195 bool renameBlock[Impl::MaxThreads];
196 bool renameUnblock[Impl::MaxThreads];
197 bool iewBlock[Impl::MaxThreads];
198 bool iewUnblock[Impl::MaxThreads];
199 bool commitBlock[Impl::MaxThreads];
200 bool commitUnblock[Impl::MaxThreads];
203 #endif //__CPU_O3_COMM_HH__