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31 #ifndef __CPU_O3_COMM_HH__
32 #define __CPU_O3_COMM_HH__
36 #include "arch/types.hh"
37 #include "base/types.hh"
38 #include "cpu/inst_seq.hh"
39 #include "sim/faults.hh"
41 // Typedef for physical register index type. Although the Impl would be the
42 // most likely location for this, there are a few classes that need this
43 // typedef yet are not templated on the Impl. For now it will be defined here.
44 typedef short int PhysRegIndex;
46 /** Struct that defines the information passed from fetch to decode. */
48 struct DefaultFetchDefaultDecode {
49 typedef typename Impl::DynInstPtr DynInstPtr;
53 DynInstPtr insts[Impl::MaxWidth];
55 InstSeqNum fetchFaultSN;
59 /** Struct that defines the information passed from decode to rename. */
61 struct DefaultDecodeDefaultRename {
62 typedef typename Impl::DynInstPtr DynInstPtr;
66 DynInstPtr insts[Impl::MaxWidth];
69 /** Struct that defines the information passed from rename to IEW. */
71 struct DefaultRenameDefaultIEW {
72 typedef typename Impl::DynInstPtr DynInstPtr;
76 DynInstPtr insts[Impl::MaxWidth];
79 /** Struct that defines the information passed from IEW to commit. */
81 struct DefaultIEWDefaultCommit {
82 typedef typename Impl::DynInstPtr DynInstPtr;
86 DynInstPtr insts[Impl::MaxWidth];
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
91 Addr mispredPC[Impl::MaxThreads];
92 TheISA::PCState pc[Impl::MaxThreads];
93 InstSeqNum squashedSeqNum[Impl::MaxThreads];
95 bool includeSquashInst[Impl::MaxThreads];
100 typedef typename Impl::DynInstPtr DynInstPtr;
104 DynInstPtr insts[Impl::MaxWidth];
107 /** Struct that defines all backwards communication. */
109 struct TimeBufStruct {
115 InstSeqNum doneSeqNum;
117 // @todo: Might want to package this kind of branch stuff into a single
118 // struct as it is used pretty frequently.
119 bool branchMispredict;
122 TheISA::PCState nextPC;
124 unsigned branchCount;
127 decodeComm decodeInfo[Impl::MaxThreads];
132 renameComm renameInfo[Impl::MaxThreads];
135 // Also eventually include skid buffer space.
137 unsigned freeIQEntries;
139 unsigned freeLSQEntries;
145 unsigned dispatchedToLSQ;
148 iewComm iewInfo[Impl::MaxThreads];
152 unsigned freeROBEntries;
158 bool branchMispredict;
163 // Represents the instruction that has either been retired or
164 // squashed. Similar to having a single bus that broadcasts the
165 // retired or squashed sequence number.
166 InstSeqNum doneSeqNum;
168 //Just in case we want to do a commit/squash on a cycle
169 //(necessary for multiple ROBs?)
171 InstSeqNum squashSeqNum;
173 // Communication specifically to the IQ to tell the IQ that it can
174 // schedule a non-speculative instruction.
175 InstSeqNum nonSpecSeqNum;
177 // Hack for now to send back an uncached access to the IEW stage.
178 typedef typename Impl::DynInstPtr DynInstPtr;
180 DynInstPtr uncachedLoad;
182 bool interruptPending;
186 commitComm commitInfo[Impl::MaxThreads];
188 bool decodeBlock[Impl::MaxThreads];
189 bool decodeUnblock[Impl::MaxThreads];
190 bool renameBlock[Impl::MaxThreads];
191 bool renameUnblock[Impl::MaxThreads];
192 bool iewBlock[Impl::MaxThreads];
193 bool iewUnblock[Impl::MaxThreads];
194 bool commitBlock[Impl::MaxThreads];
195 bool commitUnblock[Impl::MaxThreads];
198 #endif //__CPU_O3_COMM_HH__