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44 #ifndef __CPU_O3_COMMIT_HH__
45 #define __CPU_O3_COMMIT_HH__
49 #include "base/statistics.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/inst_seq.hh"
52 #include "cpu/timebuf.hh"
54 struct DerivO3CPUParams;
60 * DefaultCommit handles single threaded and SMT commit. Its width is
61 * specified by the parameters; each cycle it tries to commit that
62 * many instructions. The SMT policy decides which thread it tries to
63 * commit instructions from. Non- speculative instructions must reach
64 * the head of the ROB before they are ready to execute; once they
65 * reach the head, commit will broadcast the instruction's sequence
66 * number to the previous stages so that they can issue/ execute the
67 * instruction. Only one non-speculative instruction is handled per
68 * cycle. Commit is responsible for handling all back-end initiated
69 * redirects. It receives the redirect, and then broadcasts it to all
70 * stages, indicating the sequence number they should squash until,
71 * and any necessary branch misprediction information as well. It
72 * priortizes redirects by instruction's age, only broadcasting a
73 * redirect if it corresponds to an instruction that should currently
74 * be in the ROB. This is done by tracking the sequence number of the
75 * youngest instruction in the ROB, which gets updated to any
76 * squashing instruction's sequence number, and only broadcasting a
77 * redirect if it corresponds to an older instruction. Commit also
78 * supports multiple cycle squashing, to model a ROB that can only
79 * remove a certain number of instructions per cycle.
85 // Typedefs from the Impl.
86 typedef typename Impl::O3CPU O3CPU;
87 typedef typename Impl::DynInstPtr DynInstPtr;
88 typedef typename Impl::CPUPol CPUPol;
90 typedef typename CPUPol::RenameMap RenameMap;
91 typedef typename CPUPol::ROB ROB;
93 typedef typename CPUPol::TimeStruct TimeStruct;
94 typedef typename CPUPol::FetchStruct FetchStruct;
95 typedef typename CPUPol::IEWStruct IEWStruct;
96 typedef typename CPUPol::RenameStruct RenameStruct;
98 typedef typename CPUPol::Fetch Fetch;
99 typedef typename CPUPol::IEW IEW;
101 typedef O3ThreadState<Impl> Thread;
103 /** Event class used to schedule a squash due to a trap (fault or
104 * interrupt) to happen on a specific cycle.
106 class TrapEvent : public Event {
108 DefaultCommit<Impl> *commit;
112 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
115 const char *description() const;
118 /** Overall commit status. Used to determine if the CPU can deschedule
119 * itself due to a lack of activity.
126 /** Individual thread status. */
135 /** Commit policy for SMT mode. */
143 /** Overall commit status. */
144 CommitStatus _status;
145 /** Next commit status, to be set at the end of the cycle. */
146 CommitStatus _nextStatus;
147 /** Per-thread status. */
148 ThreadStatus commitStatus[Impl::MaxThreads];
149 /** Commit policy used in SMT mode. */
150 CommitPolicy commitPolicy;
153 /** Construct a DefaultCommit with the given parameters. */
154 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
156 /** Returns the name of the DefaultCommit. */
157 std::string name() const;
159 /** Registers statistics. */
162 /** Sets the list of threads. */
163 void setThreads(std::vector<Thread *> &threads);
165 /** Sets the main time buffer pointer, used for backwards communication. */
166 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
168 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
170 /** Sets the pointer to the queue coming from rename. */
171 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
173 /** Sets the pointer to the queue coming from IEW. */
174 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
176 /** Sets the pointer to the IEW stage. */
177 void setIEWStage(IEW *iew_stage);
179 /** Skid buffer between rename and commit. */
180 std::queue<DynInstPtr> skidBuffer;
182 /** The pointer to the IEW stage. Used solely to ensure that
183 * various events (traps, interrupts, syscalls) do not occur until
184 * all stores have written back.
188 /** Sets pointer to list of active threads. */
189 void setActiveThreads(std::list<ThreadID> *at_ptr);
191 /** Sets pointer to the commited state rename map. */
192 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
194 /** Sets pointer to the ROB. */
195 void setROB(ROB *rob_ptr);
197 /** Initializes stage by sending back the number of free entries. */
200 /** Initializes the draining of commit. */
203 /** Resumes execution after draining. */
206 /** Completes the switch out of commit. */
209 /** Takes over from another CPU's thread. */
212 /** Ticks the commit stage, which tries to commit instructions. */
215 /** Handles any squashes that are sent from IEW, and adds instructions
216 * to the ROB and tries to commit instructions.
220 /** Returns the number of free ROB entries for a specific thread. */
221 size_t numROBFreeEntries(ThreadID tid);
223 /** Generates an event to schedule a squash due to a trap. */
224 void generateTrapEvent(ThreadID tid);
226 /** Records that commit needs to initiate a squash due to an
227 * external state update through the TC.
229 void generateTCEvent(ThreadID tid);
232 /** Updates the overall status of commit with the nextStatus, and
233 * tell the CPU if commit is active/inactive.
237 /** Sets the next status based on threads' statuses, which becomes the
238 * current status at the end of the cycle.
240 void setNextStatus();
242 /** Checks if the ROB is completed with squashing. This is for the case
243 * where the ROB can take multiple cycles to complete squashing.
245 bool robDoneSquashing();
247 /** Returns if any of the threads have the number of ROB entries changed
248 * on this cycle. Used to determine if the number of free ROB entries needs
249 * to be sent back to previous stages.
251 bool changedROBEntries();
253 /** Squashes all in flight instructions. */
254 void squashAll(ThreadID tid);
256 /** Handles squashing due to a trap. */
257 void squashFromTrap(ThreadID tid);
259 /** Handles squashing due to an TC write. */
260 void squashFromTC(ThreadID tid);
262 /** Handles squashing from instruction with SquashAfter set.
263 * This differs from the other squashes as it squashes following
264 * instructions instead of the current instruction and doesn't
265 * clean up various status bits about traps/tc writes pending.
267 void squashAfter(ThreadID tid, DynInstPtr &head_inst,
268 uint64_t squash_after_seq_num);
270 /** Handles processing an interrupt. */
271 void handleInterrupt();
273 /** Get fetch redirecting so we can handle an interrupt */
274 void propagateInterrupt();
276 /** Commits as many instructions as possible. */
279 /** Tries to commit the head ROB instruction passed in.
280 * @param head_inst The instruction to be committed.
282 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
284 /** Gets instructions from rename and inserts them into the ROB. */
287 /** Insert all instructions from rename into skidBuffer */
290 /** Marks completed instructions using information sent from IEW. */
291 void markCompletedInsts();
293 /** Gets the thread to commit, based on the SMT policy. */
294 ThreadID getCommittingThread();
296 /** Returns the thread ID to use based on a round robin policy. */
297 ThreadID roundRobin();
299 /** Returns the thread ID to use based on an oldest instruction policy. */
300 ThreadID oldestReady();
303 /** Reads the PC of a specific thread. */
304 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
306 /** Sets the PC of a specific thread. */
307 void pcState(const TheISA::PCState &val, ThreadID tid)
310 /** Returns the PC of a specific thread. */
311 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
313 /** Returns the next PC of a specific thread. */
314 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
316 /** Reads the micro PC of a specific thread. */
317 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
320 /** Time buffer interface. */
321 TimeBuffer<TimeStruct> *timeBuffer;
323 /** Wire to write information heading to previous stages. */
324 typename TimeBuffer<TimeStruct>::wire toIEW;
326 /** Wire to read information from IEW (for ROB). */
327 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
329 TimeBuffer<FetchStruct> *fetchQueue;
331 typename TimeBuffer<FetchStruct>::wire fromFetch;
333 /** IEW instruction queue interface. */
334 TimeBuffer<IEWStruct> *iewQueue;
336 /** Wire to read information from IEW queue. */
337 typename TimeBuffer<IEWStruct>::wire fromIEW;
339 /** Rename instruction queue interface, for ROB. */
340 TimeBuffer<RenameStruct> *renameQueue;
342 /** Wire to read information from rename queue. */
343 typename TimeBuffer<RenameStruct>::wire fromRename;
346 /** ROB interface. */
350 /** Pointer to O3CPU. */
353 /** Vector of all of the threads. */
354 std::vector<Thread *> thread;
356 /** Records that commit has written to the time buffer this cycle. Used for
357 * the CPU to determine if it can deschedule itself if there is no activity.
359 bool wroteToTimeBuffer;
361 /** Records if the number of ROB entries has changed this cycle. If it has,
362 * then the number of free entries must be re-broadcast.
364 bool changedROBNumEntries[Impl::MaxThreads];
366 /** A counter of how many threads are currently squashing. */
367 ThreadID squashCounter;
369 /** Records if a thread has to squash this cycle due to a trap. */
370 bool trapSquash[Impl::MaxThreads];
372 /** Records if a thread has to squash this cycle due to an XC write. */
373 bool tcSquash[Impl::MaxThreads];
375 /** Priority List used for Commit Policy */
376 std::list<ThreadID> priority_list;
378 /** IEW to Commit delay. */
379 Cycles iewToCommitDelay;
381 /** Commit to IEW delay. */
382 Cycles commitToIEWDelay;
384 /** Rename to ROB delay. */
385 Cycles renameToROBDelay;
387 Cycles fetchToCommitDelay;
389 /** Rename width, in instructions. Used so ROB knows how many
390 * instructions to get from the rename instruction queue.
392 unsigned renameWidth;
394 /** Commit width, in instructions. */
395 unsigned commitWidth;
397 /** Number of Reorder Buffers */
400 /** Number of Active Threads */
403 /** Is a drain pending. */
406 /** Is commit switched out. */
409 /** The latency to handle a trap. Used when scheduling trap
414 /** The interrupt fault. */
417 /** The commit PC state of each thread. Refers to the instruction that
418 * is currently being processed/committed.
420 TheISA::PCState pc[Impl::MaxThreads];
422 /** The sequence number of the youngest valid instruction in the ROB. */
423 InstSeqNum youngestSeqNum[Impl::MaxThreads];
425 /** The sequence number of the last commited instruction. */
426 InstSeqNum lastCommitedSeqNum[Impl::MaxThreads];
428 /** Records if there is a trap currently in flight. */
429 bool trapInFlight[Impl::MaxThreads];
431 /** Records if there were any stores committed this cycle. */
432 bool committedStores[Impl::MaxThreads];
434 /** Records if commit should check if the ROB is truly empty (see
436 bool checkEmptyROB[Impl::MaxThreads];
438 /** Pointer to the list of active threads. */
439 std::list<ThreadID> *activeThreads;
441 /** Rename map interface. */
442 RenameMap *renameMap[Impl::MaxThreads];
444 /** True if last committed microop can be followed by an interrupt */
445 bool canHandleInterrupts;
447 /** Updates commit stats based on this instruction. */
448 void updateComInstStats(DynInstPtr &inst);
450 /** Stat for the total number of squashed instructions discarded by commit.
452 Stats::Scalar commitSquashedInsts;
453 /** Stat for the total number of times commit is told to squash.
454 * @todo: Actually increment this stat.
456 Stats::Scalar commitSquashEvents;
457 /** Stat for the total number of times commit has had to stall due to a non-
458 * speculative instruction reaching the head of the ROB.
460 Stats::Scalar commitNonSpecStalls;
461 /** Stat for the total number of branch mispredicts that caused a squash. */
462 Stats::Scalar branchMispredicts;
463 /** Distribution of the number of committed instructions each cycle. */
464 Stats::Distribution numCommittedDist;
466 /** Total number of instructions committed. */
467 Stats::Vector instsCommitted;
468 /** Total number of ops (including micro ops) committed. */
469 Stats::Vector opsCommitted;
470 /** Total number of software prefetches committed. */
471 Stats::Vector statComSwp;
472 /** Stat for the total number of committed memory references. */
473 Stats::Vector statComRefs;
474 /** Stat for the total number of committed loads. */
475 Stats::Vector statComLoads;
476 /** Total number of committed memory barriers. */
477 Stats::Vector statComMembars;
478 /** Total number of committed branches. */
479 Stats::Vector statComBranches;
480 /** Total number of floating point instructions */
481 Stats::Vector statComFloating;
482 /** Total number of integer instructions */
483 Stats::Vector statComInteger;
484 /** Total number of function calls */
485 Stats::Vector statComFunctionCalls;
487 /** Number of cycles where the commit bandwidth limit is reached. */
488 Stats::Scalar commitEligibleSamples;
489 /** Number of instructions not committed due to bandwidth limits. */
490 Stats::Vector commitEligible;
493 #endif // __CPU_O3_COMMIT_HH__