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44 #ifndef __CPU_O3_COMMIT_HH__
45 #define __CPU_O3_COMMIT_HH__
49 #include "base/statistics.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/inst_seq.hh"
52 #include "cpu/timebuf.hh"
53 #include "enums/CommitPolicy.hh"
54 #include "sim/probe/probe.hh"
56 struct DerivO3CPUParams;
62 * DefaultCommit handles single threaded and SMT commit. Its width is
63 * specified by the parameters; each cycle it tries to commit that
64 * many instructions. The SMT policy decides which thread it tries to
65 * commit instructions from. Non- speculative instructions must reach
66 * the head of the ROB before they are ready to execute; once they
67 * reach the head, commit will broadcast the instruction's sequence
68 * number to the previous stages so that they can issue/ execute the
69 * instruction. Only one non-speculative instruction is handled per
70 * cycle. Commit is responsible for handling all back-end initiated
71 * redirects. It receives the redirect, and then broadcasts it to all
72 * stages, indicating the sequence number they should squash until,
73 * and any necessary branch misprediction information as well. It
74 * priortizes redirects by instruction's age, only broadcasting a
75 * redirect if it corresponds to an instruction that should currently
76 * be in the ROB. This is done by tracking the sequence number of the
77 * youngest instruction in the ROB, which gets updated to any
78 * squashing instruction's sequence number, and only broadcasting a
79 * redirect if it corresponds to an older instruction. Commit also
80 * supports multiple cycle squashing, to model a ROB that can only
81 * remove a certain number of instructions per cycle.
87 // Typedefs from the Impl.
88 typedef typename Impl::O3CPU O3CPU;
89 typedef typename Impl::DynInstPtr DynInstPtr;
90 typedef typename Impl::CPUPol CPUPol;
92 typedef typename CPUPol::RenameMap RenameMap;
93 typedef typename CPUPol::ROB ROB;
95 typedef typename CPUPol::TimeStruct TimeStruct;
96 typedef typename CPUPol::FetchStruct FetchStruct;
97 typedef typename CPUPol::IEWStruct IEWStruct;
98 typedef typename CPUPol::RenameStruct RenameStruct;
100 typedef typename CPUPol::Fetch Fetch;
101 typedef typename CPUPol::IEW IEW;
103 typedef O3ThreadState<Impl> Thread;
105 /** Overall commit status. Used to determine if the CPU can deschedule
106 * itself due to a lack of activity.
113 /** Individual thread status. */
120 SquashAfterPending, //< Committing instructions before a squash.
124 /** Overall commit status. */
125 CommitStatus _status;
126 /** Next commit status, to be set at the end of the cycle. */
127 CommitStatus _nextStatus;
128 /** Per-thread status. */
129 ThreadStatus commitStatus[Impl::MaxThreads];
130 /** Commit policy used in SMT mode. */
131 CommitPolicy commitPolicy;
134 ProbePointArg<DynInstPtr> *ppCommit;
135 ProbePointArg<DynInstPtr> *ppCommitStall;
136 /** To probe when an instruction is squashed */
137 ProbePointArg<DynInstPtr> *ppSquash;
139 /** Mark the thread as processing a trap. */
140 void processTrapEvent(ThreadID tid);
143 /** Construct a DefaultCommit with the given parameters. */
144 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
146 /** Returns the name of the DefaultCommit. */
147 std::string name() const;
149 /** Registers statistics. */
152 /** Registers probes. */
153 void regProbePoints();
155 /** Sets the list of threads. */
156 void setThreads(std::vector<Thread *> &threads);
158 /** Sets the main time buffer pointer, used for backwards communication. */
159 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
161 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
163 /** Sets the pointer to the queue coming from rename. */
164 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
166 /** Sets the pointer to the queue coming from IEW. */
167 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
169 /** Sets the pointer to the IEW stage. */
170 void setIEWStage(IEW *iew_stage);
172 /** The pointer to the IEW stage. Used solely to ensure that
173 * various events (traps, interrupts, syscalls) do not occur until
174 * all stores have written back.
178 /** Sets pointer to list of active threads. */
179 void setActiveThreads(std::list<ThreadID> *at_ptr);
181 /** Sets pointer to the commited state rename map. */
182 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
184 /** Sets pointer to the ROB. */
185 void setROB(ROB *rob_ptr);
187 /** Initializes stage by sending back the number of free entries. */
190 /** Clear all thread-specific states */
191 void clearStates(ThreadID tid);
193 /** Initializes the draining of commit. */
196 /** Resumes execution after draining. */
199 /** Perform sanity checks after a drain. */
200 void drainSanityCheck() const;
202 /** Has the stage drained? */
203 bool isDrained() const;
205 /** Takes over from another CPU's thread. */
208 /** Deschedules a thread from scheduling */
209 void deactivateThread(ThreadID tid);
211 /** Ticks the commit stage, which tries to commit instructions. */
214 /** Handles any squashes that are sent from IEW, and adds instructions
215 * to the ROB and tries to commit instructions.
219 /** Returns the number of free ROB entries for a specific thread. */
220 size_t numROBFreeEntries(ThreadID tid);
222 /** Generates an event to schedule a squash due to a trap. */
223 void generateTrapEvent(ThreadID tid, Fault inst_fault);
225 /** Records that commit needs to initiate a squash due to an
226 * external state update through the TC.
228 void generateTCEvent(ThreadID tid);
231 /** Updates the overall status of commit with the nextStatus, and
232 * tell the CPU if commit is active/inactive.
236 /** Returns if any of the threads have the number of ROB entries changed
237 * on this cycle. Used to determine if the number of free ROB entries needs
238 * to be sent back to previous stages.
240 bool changedROBEntries();
242 /** Squashes all in flight instructions. */
243 void squashAll(ThreadID tid);
245 /** Handles squashing due to a trap. */
246 void squashFromTrap(ThreadID tid);
248 /** Handles squashing due to an TC write. */
249 void squashFromTC(ThreadID tid);
251 /** Handles a squash from a squashAfter() request. */
252 void squashFromSquashAfter(ThreadID tid);
255 * Handle squashing from instruction with SquashAfter set.
257 * This differs from the other squashes as it squashes following
258 * instructions instead of the current instruction and doesn't
259 * clean up various status bits about traps/tc writes
260 * pending. Since there might have been instructions committed by
261 * the commit stage before the squashing instruction was reached
262 * and we can't commit and squash in the same cycle, we have to
263 * squash in two steps:
266 * <li>Immediately set the commit status of the thread of
267 * SquashAfterPending. This forces the thread to stop
268 * committing instructions in this cycle. The last
269 * instruction to be committed in this cycle will be the
270 * SquashAfter instruction.
271 * <li>In the next cycle, commit() checks for the
272 * SquashAfterPending state and squashes <i>all</i>
273 * in-flight instructions. Since the SquashAfter instruction
274 * was the last instruction to be committed in the previous
275 * cycle, this causes all subsequent instructions to be
279 * @param tid ID of the thread to squash.
280 * @param head_inst Instruction that requested the squash.
282 void squashAfter(ThreadID tid, const DynInstPtr &head_inst);
284 /** Handles processing an interrupt. */
285 void handleInterrupt();
287 /** Get fetch redirecting so we can handle an interrupt */
288 void propagateInterrupt();
290 /** Commits as many instructions as possible. */
293 /** Tries to commit the head ROB instruction passed in.
294 * @param head_inst The instruction to be committed.
296 bool commitHead(const DynInstPtr &head_inst, unsigned inst_num);
298 /** Gets instructions from rename and inserts them into the ROB. */
301 /** Marks completed instructions using information sent from IEW. */
302 void markCompletedInsts();
304 /** Gets the thread to commit, based on the SMT policy. */
305 ThreadID getCommittingThread();
307 /** Returns the thread ID to use based on a round robin policy. */
308 ThreadID roundRobin();
310 /** Returns the thread ID to use based on an oldest instruction policy. */
311 ThreadID oldestReady();
314 /** Reads the PC of a specific thread. */
315 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
317 /** Sets the PC of a specific thread. */
318 void pcState(const TheISA::PCState &val, ThreadID tid)
321 /** Returns the PC of a specific thread. */
322 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
324 /** Returns the next PC of a specific thread. */
325 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
327 /** Reads the micro PC of a specific thread. */
328 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
331 /** Time buffer interface. */
332 TimeBuffer<TimeStruct> *timeBuffer;
334 /** Wire to write information heading to previous stages. */
335 typename TimeBuffer<TimeStruct>::wire toIEW;
337 /** Wire to read information from IEW (for ROB). */
338 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
340 TimeBuffer<FetchStruct> *fetchQueue;
342 typename TimeBuffer<FetchStruct>::wire fromFetch;
344 /** IEW instruction queue interface. */
345 TimeBuffer<IEWStruct> *iewQueue;
347 /** Wire to read information from IEW queue. */
348 typename TimeBuffer<IEWStruct>::wire fromIEW;
350 /** Rename instruction queue interface, for ROB. */
351 TimeBuffer<RenameStruct> *renameQueue;
353 /** Wire to read information from rename queue. */
354 typename TimeBuffer<RenameStruct>::wire fromRename;
357 /** ROB interface. */
361 /** Pointer to O3CPU. */
364 /** Vector of all of the threads. */
365 std::vector<Thread *> thread;
367 /** Records that commit has written to the time buffer this cycle. Used for
368 * the CPU to determine if it can deschedule itself if there is no activity.
370 bool wroteToTimeBuffer;
372 /** Records if the number of ROB entries has changed this cycle. If it has,
373 * then the number of free entries must be re-broadcast.
375 bool changedROBNumEntries[Impl::MaxThreads];
377 /** Records if a thread has to squash this cycle due to a trap. */
378 bool trapSquash[Impl::MaxThreads];
380 /** Records if a thread has to squash this cycle due to an XC write. */
381 bool tcSquash[Impl::MaxThreads];
384 * Instruction passed to squashAfter().
386 * The squash after implementation needs to buffer the instruction
387 * that caused a squash since this needs to be passed to the fetch
388 * stage once squashing starts.
390 DynInstPtr squashAfterInst[Impl::MaxThreads];
392 /** Priority List used for Commit Policy */
393 std::list<ThreadID> priority_list;
395 /** IEW to Commit delay. */
396 const Cycles iewToCommitDelay;
398 /** Commit to IEW delay. */
399 const Cycles commitToIEWDelay;
401 /** Rename to ROB delay. */
402 const Cycles renameToROBDelay;
404 const Cycles fetchToCommitDelay;
406 /** Rename width, in instructions. Used so ROB knows how many
407 * instructions to get from the rename instruction queue.
409 const unsigned renameWidth;
411 /** Commit width, in instructions. */
412 const unsigned commitWidth;
414 /** Number of Reorder Buffers */
417 /** Number of Active Threads */
418 const ThreadID numThreads;
420 /** Is a drain pending? Commit is looking for an instruction boundary while
421 * there are no pending interrupts
425 /** Is a drain imminent? Commit has found an instruction boundary while no
426 * interrupts were present or in flight. This was the last architecturally
427 * committed instruction. Interrupts disabled and pipeline flushed.
428 * Waiting for structures to finish draining.
432 /** The latency to handle a trap. Used when scheduling trap
435 const Cycles trapLatency;
437 /** The interrupt fault. */
440 /** The commit PC state of each thread. Refers to the instruction that
441 * is currently being processed/committed.
443 TheISA::PCState pc[Impl::MaxThreads];
445 /** The sequence number of the youngest valid instruction in the ROB. */
446 InstSeqNum youngestSeqNum[Impl::MaxThreads];
448 /** The sequence number of the last commited instruction. */
449 InstSeqNum lastCommitedSeqNum[Impl::MaxThreads];
451 /** Records if there is a trap currently in flight. */
452 bool trapInFlight[Impl::MaxThreads];
454 /** Records if there were any stores committed this cycle. */
455 bool committedStores[Impl::MaxThreads];
457 /** Records if commit should check if the ROB is truly empty (see
459 bool checkEmptyROB[Impl::MaxThreads];
461 /** Pointer to the list of active threads. */
462 std::list<ThreadID> *activeThreads;
464 /** Rename map interface. */
465 RenameMap *renameMap[Impl::MaxThreads];
467 /** True if last committed microop can be followed by an interrupt */
468 bool canHandleInterrupts;
470 /** Have we had an interrupt pending and then seen it de-asserted because
471 of a masking change? In this case the variable is set and the next time
472 interrupts are enabled and pending the pipeline will squash to avoid
473 a possible livelock senario. */
474 bool avoidQuiesceLiveLock;
476 /** Updates commit stats based on this instruction. */
477 void updateComInstStats(const DynInstPtr &inst);
479 /** Stat for the total number of squashed instructions discarded by commit.
481 Stats::Scalar commitSquashedInsts;
482 /** Stat for the total number of times commit has had to stall due to a non-
483 * speculative instruction reaching the head of the ROB.
485 Stats::Scalar commitNonSpecStalls;
486 /** Stat for the total number of branch mispredicts that caused a squash. */
487 Stats::Scalar branchMispredicts;
488 /** Distribution of the number of committed instructions each cycle. */
489 Stats::Distribution numCommittedDist;
491 /** Total number of instructions committed. */
492 Stats::Vector instsCommitted;
493 /** Total number of ops (including micro ops) committed. */
494 Stats::Vector opsCommitted;
495 /** Total number of software prefetches committed. */
496 Stats::Vector statComSwp;
497 /** Stat for the total number of committed memory references. */
498 Stats::Vector statComRefs;
499 /** Stat for the total number of committed loads. */
500 Stats::Vector statComLoads;
501 /** Total number of committed memory barriers. */
502 Stats::Vector statComMembars;
503 /** Total number of committed branches. */
504 Stats::Vector statComBranches;
505 /** Total number of vector instructions */
506 Stats::Vector statComVector;
507 /** Total number of floating point instructions */
508 Stats::Vector statComFloating;
509 /** Total number of integer instructions */
510 Stats::Vector statComInteger;
511 /** Total number of function calls */
512 Stats::Vector statComFunctionCalls;
513 /** Committed instructions by instruction type (OpClass) */
514 Stats::Vector2d statCommittedInstType;
516 /** Number of cycles where the commit bandwidth limit is reached. */
517 Stats::Scalar commitEligibleSamples;
520 #endif // __CPU_O3_COMMIT_HH__