src/cpu/o3/commit.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_O3_COMMIT_HH__
  30 #define __CPU_O3_COMMIT_HH__
  31
  32 #include "arch/faults.hh"
  33 #include "base/statistics.hh"
  34 #include "base/timebuf.hh"
  35 #include "cpu/exetrace.hh"
  36 #include "cpu/inst_seq.hh"
  37 #include "mem/memory_interface.hh"
  38
  39 template <class>
  40 class O3ThreadState;
  41
  42 /**
  43  * DefaultCommit handles single threaded and SMT commit. Its width is
  44  * specified by the parameters; each cycle it tries to commit that
  45  * many instructions. The SMT policy decides which thread it tries to
  46  * commit instructions from. Non- speculative instructions must reach
  47  * the head of the ROB before they are ready to execute; once they
  48  * reach the head, commit will broadcast the instruction's sequence
  49  * number to the previous stages so that they can issue/ execute the
  50  * instruction. Only one non-speculative instruction is handled per
  51  * cycle. Commit is responsible for handling all back-end initiated
  52  * redirects.  It receives the redirect, and then broadcasts it to all
  53  * stages, indicating the sequence number they should squash until,
  54  * and any necessary branch misprediction information as well. It
  55  * priortizes redirects by instruction's age, only broadcasting a
  56  * redirect if it corresponds to an instruction that should currently
  57  * be in the ROB. This is done by tracking the sequence number of the
  58  * youngest instruction in the ROB, which gets updated to any
  59  * squashing instruction's sequence number, and only broadcasting a
  60  * redirect if it corresponds to an older instruction. Commit also
  61  * supports multiple cycle squashing, to model a ROB that can only
  62  * remove a certain number of instructions per cycle.
  63  */
  64 template<class Impl>
  65 class DefaultCommit
  66 {
  67   public:
  68     // Typedefs from the Impl.
  69     typedef typename Impl::FullCPU FullCPU;
  70     typedef typename Impl::DynInstPtr DynInstPtr;
  71     typedef typename Impl::Params Params;
  72     typedef typename Impl::CPUPol CPUPol;
  73
  74     typedef typename CPUPol::RenameMap RenameMap;
  75     typedef typename CPUPol::ROB ROB;
  76
  77     typedef typename CPUPol::TimeStruct TimeStruct;
  78     typedef typename CPUPol::FetchStruct FetchStruct;
  79     typedef typename CPUPol::IEWStruct IEWStruct;
  80     typedef typename CPUPol::RenameStruct RenameStruct;
  81
  82     typedef typename CPUPol::Fetch Fetch;
  83     typedef typename CPUPol::IEW IEW;
  84
  85     typedef O3ThreadState<Impl> Thread;
  86
  87     class TrapEvent : public Event {
  88       private:
  89         DefaultCommit<Impl> *commit;
  90         unsigned tid;
  91
  92       public:
  93         TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
  94
  95         void process();
  96         const char *description();
  97     };
  98
  99     /** Overall commit status. Used to determine if the CPU can deschedule
 100      * itself due to a lack of activity.
 101      */
 102     enum CommitStatus{
 103         Active,
 104         Inactive
 105     };
 106
 107     /** Individual thread status. */
 108     enum ThreadStatus {
 109         Running,
 110         Idle,
 111         ROBSquashing,
 112         TrapPending,
 113         FetchTrapPending
 114     };
 115
 116     /** Commit policy for SMT mode. */
 117     enum CommitPolicy {
 118         Aggressive,
 119         RoundRobin,
 120         OldestReady
 121     };
 122
 123   private:
 124     /** Overall commit status. */
 125     CommitStatus _status;
 126     /** Next commit status, to be set at the end of the cycle. */
 127     CommitStatus _nextStatus;
 128     /** Per-thread status. */
 129     ThreadStatus commitStatus[Impl::MaxThreads];
 130     /** Commit policy used in SMT mode. */
 131     CommitPolicy commitPolicy;
 132
 133   public:
 134     /** Construct a DefaultCommit with the given parameters. */
 135     DefaultCommit(Params *params);
 136
 137     /** Returns the name of the DefaultCommit. */
 138     std::string name() const;
 139
 140     /** Registers statistics. */
 141     void regStats();
 142
 143     /** Sets the CPU pointer. */
 144     void setCPU(FullCPU *cpu_ptr);
 145
 146     /** Sets the list of threads. */
 147     void setThreads(std::vector<Thread *> &threads);
 148
 149     /** Sets the main time buffer pointer, used for backwards communication. */
 150     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 151
 152     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 153
 154     /** Sets the pointer to the queue coming from rename. */
 155     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 156
 157     /** Sets the pointer to the queue coming from IEW. */
 158     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 159
 160     void setFetchStage(Fetch *fetch_stage);
 161
 162     Fetch *fetchStage;
 163
 164     /** Sets the poitner to the IEW stage. */
 165     void setIEWStage(IEW *iew_stage);
 166
 167     /** The pointer to the IEW stage. Used solely to ensure that
 168      * various events (traps, interrupts, syscalls) do not occur until
 169      * all stores have written back.
 170      */
 171     IEW *iewStage;
 172
 173     /** Sets pointer to list of active threads. */
 174     void setActiveThreads(std::list<unsigned> *at_ptr);
 175
 176     /** Sets pointer to the commited state rename map. */
 177     void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
 178
 179     /** Sets pointer to the ROB. */
 180     void setROB(ROB *rob_ptr);
 181
 182     /** Initializes stage by sending back the number of free entries. */
 183     void initStage();
 184
 185     void switchOut();
 186
 187     void doSwitchOut();
 188
 189     void takeOverFrom();
 190
 191     /** Ticks the commit stage, which tries to commit instructions. */
 192     void tick();
 193
 194     /** Handles any squashes that are sent from IEW, and adds instructions
 195      * to the ROB and tries to commit instructions.
 196      */
 197     void commit();
 198
 199     /** Returns the number of free ROB entries for a specific thread. */
 200     unsigned numROBFreeEntries(unsigned tid);
 201
 202     void generateXCEvent(unsigned tid);
 203
 204   private:
 205     /** Updates the overall status of commit with the nextStatus, and
 206      * tell the CPU if commit is active/inactive. */
 207     void updateStatus();
 208
 209     /** Sets the next status based on threads' statuses, which becomes the
 210      * current status at the end of the cycle.
 211      */
 212     void setNextStatus();
 213
 214     /** Checks if the ROB is completed with squashing. This is for the case
 215      * where the ROB can take multiple cycles to complete squashing.
 216      */
 217     bool robDoneSquashing();
 218
 219     /** Returns if any of the threads have the number of ROB entries changed
 220      * on this cycle. Used to determine if the number of free ROB entries needs
 221      * to be sent back to previous stages.
 222      */
 223     bool changedROBEntries();
 224
 225     void squashAll(unsigned tid);
 226
 227     void squashFromTrap(unsigned tid);
 228
 229     void squashFromXC(unsigned tid);
 230
 231     /** Commits as many instructions as possible. */
 232     void commitInsts();
 233
 234     /** Tries to commit the head ROB instruction passed in.
 235      * @param head_inst The instruction to be committed.
 236      */
 237     bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
 238
 239     void generateTrapEvent(unsigned tid);
 240
 241     /** Gets instructions from rename and inserts them into the ROB. */
 242     void getInsts();
 243
 244     /** Marks completed instructions using information sent from IEW. */
 245     void markCompletedInsts();
 246
 247     /** Gets the thread to commit, based on the SMT policy. */
 248     int getCommittingThread();
 249
 250     /** Returns the thread ID to use based on a round robin policy. */
 251     int roundRobin();
 252
 253     /** Returns the thread ID to use based on an oldest instruction policy. */
 254     int oldestReady();
 255
 256   public:
 257     /** Returns the PC of the head instruction of the ROB.
 258      * @todo: Probably remove this function as it returns only thread 0.
 259      */
 260     uint64_t readPC() { return PC[0]; }
 261
 262     uint64_t readPC(unsigned tid) { return PC[tid]; }
 263
 264     void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
 265
 266     uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
 267
 268     void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
 269
 270   private:
 271     /** Time buffer interface. */
 272     TimeBuffer<TimeStruct> *timeBuffer;
 273
 274     /** Wire to write information heading to previous stages. */
 275     typename TimeBuffer<TimeStruct>::wire toIEW;
 276
 277     /** Wire to read information from IEW (for ROB). */
 278     typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
 279
 280     TimeBuffer<FetchStruct> *fetchQueue;
 281
 282     typename TimeBuffer<FetchStruct>::wire fromFetch;
 283
 284     /** IEW instruction queue interface. */
 285     TimeBuffer<IEWStruct> *iewQueue;
 286
 287     /** Wire to read information from IEW queue. */
 288     typename TimeBuffer<IEWStruct>::wire fromIEW;
 289
 290     /** Rename instruction queue interface, for ROB. */
 291     TimeBuffer<RenameStruct> *renameQueue;
 292
 293     /** Wire to read information from rename queue. */
 294     typename TimeBuffer<RenameStruct>::wire fromRename;
 295
 296   public:
 297     /** ROB interface. */
 298     ROB *rob;
 299
 300   private:
 301     /** Pointer to FullCPU. */
 302     FullCPU *cpu;
 303
 304     /** Memory interface.  Used for d-cache accesses. */
 305     MemInterface *dcacheInterface;
 306
 307     std::vector<Thread *> thread;
 308
 309     Fault fetchFault;
 310
 311     int fetchTrapWait;
 312
 313     /** Records that commit has written to the time buffer this cycle. Used for
 314      * the CPU to determine if it can deschedule itself if there is no activity.
 315      */
 316     bool wroteToTimeBuffer;
 317
 318     /** Records if the number of ROB entries has changed this cycle. If it has,
 319      * then the number of free entries must be re-broadcast.
 320      */
 321     bool changedROBNumEntries[Impl::MaxThreads];
 322
 323     /** A counter of how many threads are currently squashing. */
 324     int squashCounter;
 325
 326     /** Records if a thread has to squash this cycle due to a trap. */
 327     bool trapSquash[Impl::MaxThreads];
 328
 329     /** Records if a thread has to squash this cycle due to an XC write. */
 330     bool xcSquash[Impl::MaxThreads];
 331
 332     /** Priority List used for Commit Policy */
 333     std::list<unsigned> priority_list;
 334
 335     /** IEW to Commit delay, in ticks. */
 336     unsigned iewToCommitDelay;
 337
 338     /** Commit to IEW delay, in ticks. */
 339     unsigned commitToIEWDelay;
 340
 341     /** Rename to ROB delay, in ticks. */
 342     unsigned renameToROBDelay;
 343
 344     unsigned fetchToCommitDelay;
 345
 346     /** Rename width, in instructions.  Used so ROB knows how many
 347      *  instructions to get from the rename instruction queue.
 348      */
 349     unsigned renameWidth;
 350
 351     /** IEW width, in instructions.  Used so ROB knows how many
 352      *  instructions to get from the IEW instruction queue.
 353      */
 354     unsigned iewWidth;
 355
 356     /** Commit width, in instructions. */
 357     unsigned commitWidth;
 358
 359     /** Number of Reorder Buffers */
 360     unsigned numRobs;
 361
 362     /** Number of Active Threads */
 363     unsigned numThreads;
 364
 365     bool switchPending;
 366     bool switchedOut;
 367
 368     Tick trapLatency;
 369
 370     Tick fetchTrapLatency;
 371
 372     Tick fetchFaultTick;
 373
 374     Addr PC[Impl::MaxThreads];
 375
 376     Addr nextPC[Impl::MaxThreads];
 377
 378     /** The sequence number of the youngest valid instruction in the ROB. */
 379     InstSeqNum youngestSeqNum[Impl::MaxThreads];
 380
 381     /** Pointer to the list of active threads. */
 382     std::list<unsigned> *activeThreads;
 383
 384     /** Rename map interface. */
 385     RenameMap *renameMap[Impl::MaxThreads];
 386
 387     void updateComInstStats(DynInstPtr &inst);
 388
 389     /** Stat for the total number of committed instructions. */
 390     Stats::Scalar<> commitCommittedInsts;
 391     /** Stat for the total number of squashed instructions discarded by commit.
 392      */
 393     Stats::Scalar<> commitSquashedInsts;
 394     /** Stat for the total number of times commit is told to squash.
 395      * @todo: Actually increment this stat.
 396      */
 397     Stats::Scalar<> commitSquashEvents;
 398     /** Stat for the total number of times commit has had to stall due to a non-
 399      * speculative instruction reaching the head of the ROB.
 400      */
 401     Stats::Scalar<> commitNonSpecStalls;
 402     /** Stat for the total number of branch mispredicts that caused a squash. */
 403     Stats::Scalar<> branchMispredicts;
 404     /** Distribution of the number of committed instructions each cycle. */
 405     Stats::Distribution<> numCommittedDist;
 406
 407     /** Total number of instructions committed. */
 408     Stats::Vector<> statComInst;
 409     /** Total number of software prefetches committed. */
 410     Stats::Vector<> statComSwp;
 411     /** Stat for the total number of committed memory references. */
 412     Stats::Vector<> statComRefs;
 413     /** Stat for the total number of committed loads. */
 414     Stats::Vector<> statComLoads;
 415     /** Total number of committed memory barriers. */
 416     Stats::Vector<> statComMembars;
 417     /** Total number of committed branches. */
 418     Stats::Vector<> statComBranches;
 419
 420     Stats::Scalar<> commitEligibleSamples;
 421     Stats::Vector<> commitEligible;
 422 };
 423
 424 #endif // __CPU_O3_COMMIT_HH__