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41 #ifndef __CPU_O3_COMMIT_IMPL_HH__
42 #define __CPU_O3_COMMIT_IMPL_HH__
48 #include "arch/utility.hh"
49 #include "base/cp_annotate.hh"
50 #include "base/loader/symtab.hh"
51 #include "base/logging.hh"
52 #include "config/the_isa.hh"
53 #include "cpu/checker/cpu.hh"
54 #include "cpu/o3/commit.hh"
55 #include "cpu/o3/thread_state.hh"
56 #include "cpu/base.hh"
57 #include "cpu/exetrace.hh"
58 #include "cpu/timebuf.hh"
59 #include "debug/Activity.hh"
60 #include "debug/Commit.hh"
61 #include "debug/CommitRate.hh"
62 #include "debug/Drain.hh"
63 #include "debug/ExecFaulting.hh"
64 #include "debug/O3PipeView.hh"
65 #include "params/DerivO3CPU.hh"
66 #include "sim/faults.hh"
67 #include "sim/full_system.hh"
73 DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
75 // This will get reset by commit if it was switched out at the
76 // time of this event processing.
77 trapSquash[tid] = true;
81 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
82 : commitPolicy(params->smtCommitPolicy),
84 iewToCommitDelay(params->iewToCommitDelay),
85 commitToIEWDelay(params->commitToIEWDelay),
86 renameToROBDelay(params->renameToROBDelay),
87 fetchToCommitDelay(params->commitToFetchDelay),
88 renameWidth(params->renameWidth),
89 commitWidth(params->commitWidth),
90 numThreads(params->numThreads),
93 trapLatency(params->trapLatency),
94 canHandleInterrupts(true),
95 avoidQuiesceLiveLock(false)
97 if (commitWidth > Impl::MaxWidth)
98 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
99 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
100 commitWidth, static_cast<int>(Impl::MaxWidth));
103 _nextStatus = Inactive;
105 if (commitPolicy == CommitPolicy::RoundRobin) {
106 //Set-Up Priority List
107 for (ThreadID tid = 0; tid < numThreads; tid++) {
108 priority_list.push_back(tid);
112 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
113 commitStatus[tid] = Idle;
114 changedROBNumEntries[tid] = false;
115 trapSquash[tid] = false;
116 tcSquash[tid] = false;
117 squashAfterInst[tid] = nullptr;
119 youngestSeqNum[tid] = 0;
120 lastCommitedSeqNum[tid] = 0;
121 trapInFlight[tid] = false;
122 committedStores[tid] = false;
123 checkEmptyROB[tid] = false;
124 renameMap[tid] = nullptr;
129 template <class Impl>
131 DefaultCommit<Impl>::name() const
133 return cpu->name() + ".commit";
136 template <class Impl>
138 DefaultCommit<Impl>::regProbePoints()
140 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
141 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
142 ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
145 template <class Impl>
147 DefaultCommit<Impl>::regStats()
149 using namespace Stats;
151 .name(name() + ".commitSquashedInsts")
152 .desc("The number of squashed insts skipped by commit")
153 .prereq(commitSquashedInsts);
156 .name(name() + ".commitNonSpecStalls")
157 .desc("The number of times commit has been forced to stall to "
158 "communicate backwards")
159 .prereq(commitNonSpecStalls);
162 .name(name() + ".branchMispredicts")
163 .desc("The number of times a branch was mispredicted")
164 .prereq(branchMispredicts);
167 .init(0,commitWidth,1)
168 .name(name() + ".committed_per_cycle")
169 .desc("Number of insts commited each cycle")
174 .init(cpu->numThreads)
175 .name(name() + ".committedInsts")
176 .desc("Number of instructions committed")
181 .init(cpu->numThreads)
182 .name(name() + ".committedOps")
183 .desc("Number of ops (including micro ops) committed")
188 .init(cpu->numThreads)
189 .name(name() + ".swp_count")
190 .desc("Number of s/w prefetches committed")
195 .init(cpu->numThreads)
196 .name(name() + ".refs")
197 .desc("Number of memory references committed")
202 .init(cpu->numThreads)
203 .name(name() + ".loads")
204 .desc("Number of loads committed")
209 .init(cpu->numThreads)
210 .name(name() + ".amos")
211 .desc("Number of atomic instructions committed")
216 .init(cpu->numThreads)
217 .name(name() + ".membars")
218 .desc("Number of memory barriers committed")
223 .init(cpu->numThreads)
224 .name(name() + ".branches")
225 .desc("Number of branches committed")
230 .init(cpu->numThreads)
231 .name(name() + ".fp_insts")
232 .desc("Number of committed floating point instructions.")
237 .init(cpu->numThreads)
238 .name(name() + ".vec_insts")
239 .desc("Number of committed Vector instructions.")
244 .init(cpu->numThreads)
245 .name(name()+".int_insts")
246 .desc("Number of committed integer instructions.")
251 .init(cpu->numThreads)
252 .name(name()+".function_calls")
253 .desc("Number of function calls committed.")
257 statCommittedInstType
258 .init(numThreads,Enums::Num_OpClass)
259 .name(name() + ".op_class")
260 .desc("Class of committed instruction")
261 .flags(total | pdf | dist)
263 statCommittedInstType.ysubnames(Enums::OpClassStrings);
265 commitEligibleSamples
266 .name(name() + ".bw_lim_events")
267 .desc("number cycles where commit BW limit reached")
271 template <class Impl>
273 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
278 template <class Impl>
280 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
284 // Setup wire to send information back to IEW.
285 toIEW = timeBuffer->getWire(0);
287 // Setup wire to read data from IEW (for the ROB).
288 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291 template <class Impl>
293 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
297 // Setup wire to get instructions from rename (for the ROB).
298 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301 template <class Impl>
303 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
305 renameQueue = rq_ptr;
307 // Setup wire to get instructions from rename (for the ROB).
308 fromRename = renameQueue->getWire(-renameToROBDelay);
311 template <class Impl>
313 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
317 // Setup wire to get instructions from IEW.
318 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321 template <class Impl>
323 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
325 iewStage = iew_stage;
330 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
332 activeThreads = at_ptr;
335 template <class Impl>
337 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
339 for (ThreadID tid = 0; tid < numThreads; tid++)
340 renameMap[tid] = &rm_ptr[tid];
343 template <class Impl>
345 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
350 template <class Impl>
352 DefaultCommit<Impl>::startupStage()
354 rob->setActiveThreads(activeThreads);
357 // Broadcast the number of free entries.
358 for (ThreadID tid = 0; tid < numThreads; tid++) {
359 toIEW->commitInfo[tid].usedROB = true;
360 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
361 toIEW->commitInfo[tid].emptyROB = true;
364 // Commit must broadcast the number of free entries it has at the
365 // start of the simulation, so it starts as active.
366 cpu->activateStage(O3CPU::CommitIdx);
368 cpu->activityThisCycle();
371 template <class Impl>
373 DefaultCommit<Impl>::clearStates(ThreadID tid)
375 commitStatus[tid] = Idle;
376 changedROBNumEntries[tid] = false;
377 checkEmptyROB[tid] = false;
378 trapInFlight[tid] = false;
379 committedStores[tid] = false;
380 trapSquash[tid] = false;
381 tcSquash[tid] = false;
383 lastCommitedSeqNum[tid] = 0;
384 squashAfterInst[tid] = NULL;
387 template <class Impl>
389 DefaultCommit<Impl>::drain()
394 template <class Impl>
396 DefaultCommit<Impl>::drainResume()
398 drainPending = false;
399 drainImminent = false;
402 template <class Impl>
404 DefaultCommit<Impl>::drainSanityCheck() const
407 rob->drainSanityCheck();
410 template <class Impl>
412 DefaultCommit<Impl>::isDrained() const
414 /* Make sure no one is executing microcode. There are two reasons
416 * - Hardware virtualized CPUs can't switch into the middle of a
417 * microcode sequence.
418 * - The current fetch implementation will most likely get very
419 * confused if it tries to start fetching an instruction that
420 * is executing in the middle of a ucode sequence that changes
421 * address mappings. This can happen on for example x86.
423 for (ThreadID tid = 0; tid < numThreads; tid++) {
424 if (pc[tid].microPC() != 0)
428 /* Make sure that all instructions have finished committing before
429 * declaring the system as drained. We want the pipeline to be
430 * completely empty when we declare the CPU to be drained. This
431 * makes debugging easier since CPU handover and restoring from a
432 * checkpoint with a different CPU should have the same timing.
434 return rob->isEmpty() &&
435 interrupt == NoFault;
438 template <class Impl>
440 DefaultCommit<Impl>::takeOverFrom()
443 _nextStatus = Inactive;
444 for (ThreadID tid = 0; tid < numThreads; tid++) {
445 commitStatus[tid] = Idle;
446 changedROBNumEntries[tid] = false;
447 trapSquash[tid] = false;
448 tcSquash[tid] = false;
449 squashAfterInst[tid] = NULL;
454 template <class Impl>
456 DefaultCommit<Impl>::deactivateThread(ThreadID tid)
458 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
459 priority_list.end(), tid);
461 if (thread_it != priority_list.end()) {
462 priority_list.erase(thread_it);
467 template <class Impl>
469 DefaultCommit<Impl>::updateStatus()
471 // reset ROB changed variable
472 list<ThreadID>::iterator threads = activeThreads->begin();
473 list<ThreadID>::iterator end = activeThreads->end();
475 while (threads != end) {
476 ThreadID tid = *threads++;
478 changedROBNumEntries[tid] = false;
480 // Also check if any of the threads has a trap pending
481 if (commitStatus[tid] == TrapPending ||
482 commitStatus[tid] == FetchTrapPending) {
483 _nextStatus = Active;
487 if (_nextStatus == Inactive && _status == Active) {
488 DPRINTF(Activity, "Deactivating stage.\n");
489 cpu->deactivateStage(O3CPU::CommitIdx);
490 } else if (_nextStatus == Active && _status == Inactive) {
491 DPRINTF(Activity, "Activating stage.\n");
492 cpu->activateStage(O3CPU::CommitIdx);
495 _status = _nextStatus;
498 template <class Impl>
500 DefaultCommit<Impl>::changedROBEntries()
502 list<ThreadID>::iterator threads = activeThreads->begin();
503 list<ThreadID>::iterator end = activeThreads->end();
505 while (threads != end) {
506 ThreadID tid = *threads++;
508 if (changedROBNumEntries[tid]) {
516 template <class Impl>
518 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
520 return rob->numFreeEntries(tid);
523 template <class Impl>
525 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
527 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
529 EventFunctionWrapper *trap = new EventFunctionWrapper(
530 [this, tid]{ processTrapEvent(tid); },
531 "Trap", true, Event::CPU_Tick_Pri);
533 Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
534 cpu->syscallRetryLatency : trapLatency;
536 cpu->schedule(trap, cpu->clockEdge(latency));
537 trapInFlight[tid] = true;
538 thread[tid]->trapPending = true;
541 template <class Impl>
543 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
545 assert(!trapInFlight[tid]);
546 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
548 tcSquash[tid] = true;
551 template <class Impl>
553 DefaultCommit<Impl>::squashAll(ThreadID tid)
555 // If we want to include the squashing instruction in the squash,
556 // then use one older sequence number.
557 // Hopefully this doesn't mess things up. Basically I want to squash
558 // all instructions of this thread.
559 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
560 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
562 // All younger instructions will be squashed. Set the sequence
563 // number as the youngest instruction in the ROB (0 in this case.
564 // Hopefully nothing breaks.)
565 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
567 rob->squash(squashed_inst, tid);
568 changedROBNumEntries[tid] = true;
570 // Send back the sequence number of the squashed instruction.
571 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
573 // Send back the squash signal to tell stages that they should
575 toIEW->commitInfo[tid].squash = true;
577 // Send back the rob squashing signal so other stages know that
578 // the ROB is in the process of squashing.
579 toIEW->commitInfo[tid].robSquashing = true;
581 toIEW->commitInfo[tid].mispredictInst = NULL;
582 toIEW->commitInfo[tid].squashInst = NULL;
584 toIEW->commitInfo[tid].pc = pc[tid];
587 template <class Impl>
589 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
593 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
595 thread[tid]->trapPending = false;
596 thread[tid]->noSquashFromTC = false;
597 trapInFlight[tid] = false;
599 trapSquash[tid] = false;
601 commitStatus[tid] = ROBSquashing;
602 cpu->activityThisCycle();
605 template <class Impl>
607 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
611 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
613 thread[tid]->noSquashFromTC = false;
614 assert(!thread[tid]->trapPending);
616 commitStatus[tid] = ROBSquashing;
617 cpu->activityThisCycle();
619 tcSquash[tid] = false;
622 template <class Impl>
624 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
626 DPRINTF(Commit, "Squashing after squash after request, "
627 "restarting at PC %s\n", pc[tid]);
630 // Make sure to inform the fetch stage of which instruction caused
631 // the squash. It'll try to re-fetch an instruction executing in
632 // microcode unless this is set.
633 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
634 squashAfterInst[tid] = NULL;
636 commitStatus[tid] = ROBSquashing;
637 cpu->activityThisCycle();
640 template <class Impl>
642 DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst)
644 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n",
645 tid, head_inst->seqNum);
647 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
648 commitStatus[tid] = SquashAfterPending;
649 squashAfterInst[tid] = head_inst;
652 template <class Impl>
654 DefaultCommit<Impl>::tick()
656 wroteToTimeBuffer = false;
657 _nextStatus = Inactive;
659 if (activeThreads->empty())
662 list<ThreadID>::iterator threads = activeThreads->begin();
663 list<ThreadID>::iterator end = activeThreads->end();
665 // Check if any of the threads are done squashing. Change the
666 // status if they are done.
667 while (threads != end) {
668 ThreadID tid = *threads++;
670 // Clear the bit saying if the thread has committed stores
672 committedStores[tid] = false;
674 if (commitStatus[tid] == ROBSquashing) {
676 if (rob->isDoneSquashing(tid)) {
677 commitStatus[tid] = Running;
679 DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any"
680 " insts this cycle.\n", tid);
682 toIEW->commitInfo[tid].robSquashing = true;
683 wroteToTimeBuffer = true;
690 markCompletedInsts();
692 threads = activeThreads->begin();
694 while (threads != end) {
695 ThreadID tid = *threads++;
697 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
698 // The ROB has more instructions it can commit. Its next status
700 _nextStatus = Active;
702 const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
704 DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
705 " ROB and ready to commit\n",
706 tid, inst->seqNum, inst->pcState());
708 } else if (!rob->isEmpty(tid)) {
709 const DynInstPtr &inst = rob->readHeadInst(tid);
711 ppCommitStall->notify(inst);
713 DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%llu] PC "
714 "%s is head of ROB and not ready\n",
715 tid, inst->seqNum, inst->pcState());
718 DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
719 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
723 if (wroteToTimeBuffer) {
724 DPRINTF(Activity, "Activity This Cycle.\n");
725 cpu->activityThisCycle();
731 template <class Impl>
733 DefaultCommit<Impl>::handleInterrupt()
735 // Verify that we still have an interrupt to handle
736 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
737 DPRINTF(Commit, "Pending interrupt is cleared by master before "
738 "it got handled. Restart fetching from the orig path.\n");
739 toIEW->commitInfo[0].clearInterrupt = true;
741 avoidQuiesceLiveLock = true;
745 // Wait until all in flight instructions are finished before enterring
747 if (canHandleInterrupts && cpu->instList.empty()) {
748 // Squash or record that I need to squash this cycle if
749 // an interrupt needed to be handled.
750 DPRINTF(Commit, "Interrupt detected.\n");
752 // Clear the interrupt now that it's going to be handled
753 toIEW->commitInfo[0].clearInterrupt = true;
755 assert(!thread[0]->noSquashFromTC);
756 thread[0]->noSquashFromTC = true;
759 cpu->checker->handlePendingInt();
762 // CPU will handle interrupt. Note that we ignore the local copy of
763 // interrupt. This is because the local copy may no longer be the
764 // interrupt that the interrupt controller thinks is being handled.
765 cpu->processInterrupts(cpu->getInterrupts());
767 thread[0]->noSquashFromTC = false;
769 commitStatus[0] = TrapPending;
773 // Generate trap squash event.
774 generateTrapEvent(0, interrupt);
776 avoidQuiesceLiveLock = false;
778 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
779 "flight, ROB is %sempty\n",
780 canHandleInterrupts ? "not " : "",
781 cpu->instList.empty() ? "" : "not " );
785 template <class Impl>
787 DefaultCommit<Impl>::propagateInterrupt()
789 // Don't propagate intterupts if we are currently handling a trap or
790 // in draining and the last observable instruction has been committed.
791 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
792 tcSquash[0] || drainImminent)
795 // Process interrupts if interrupts are enabled, not in PAL
796 // mode, and no other traps or external squashes are currently
798 // @todo: Allow other threads to handle interrupts.
800 // Get any interrupt that happened
801 interrupt = cpu->getInterrupts();
803 // Tell fetch that there is an interrupt pending. This
804 // will make fetch wait until it sees a non PAL-mode PC,
805 // at which point it stops fetching instructions.
806 if (interrupt != NoFault)
807 toIEW->commitInfo[0].interruptPending = true;
810 template <class Impl>
812 DefaultCommit<Impl>::commit()
815 // Check if we have a interrupt and get read to handle it
816 if (cpu->checkInterrupts(cpu->tcBase(0)))
817 propagateInterrupt();
820 ////////////////////////////////////
821 // Check for any possible squashes, handle them first
822 ////////////////////////////////////
823 list<ThreadID>::iterator threads = activeThreads->begin();
824 list<ThreadID>::iterator end = activeThreads->end();
826 int num_squashing_threads = 0;
828 while (threads != end) {
829 ThreadID tid = *threads++;
831 // Not sure which one takes priority. I think if we have
832 // both, that's a bad sign.
833 if (trapSquash[tid]) {
834 assert(!tcSquash[tid]);
837 // If the thread is trying to exit (i.e., an exit syscall was
838 // executed), this trapSquash was originated by the exit
839 // syscall earlier. In this case, schedule an exit event in
840 // the next cycle to fully terminate this thread
841 if (cpu->isThreadExiting(tid))
842 cpu->scheduleThreadExitEvent(tid);
843 } else if (tcSquash[tid]) {
844 assert(commitStatus[tid] != TrapPending);
846 } else if (commitStatus[tid] == SquashAfterPending) {
847 // A squash from the previous cycle of the commit stage (i.e.,
848 // commitInsts() called squashAfter) is pending. Squash the
850 squashFromSquashAfter(tid);
853 // Squashed sequence number must be older than youngest valid
854 // instruction in the ROB. This prevents squashes from younger
855 // instructions overriding squashes from older instructions.
856 if (fromIEW->squash[tid] &&
857 commitStatus[tid] != TrapPending &&
858 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
860 if (fromIEW->mispredictInst[tid]) {
862 "[tid:%i] Squashing due to branch mispred "
863 "PC:%#x [sn:%llu]\n",
865 fromIEW->mispredictInst[tid]->instAddr(),
866 fromIEW->squashedSeqNum[tid]);
869 "[tid:%i] Squashing due to order violation [sn:%llu]\n",
870 tid, fromIEW->squashedSeqNum[tid]);
873 DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n",
875 fromIEW->pc[tid].nextInstAddr());
877 commitStatus[tid] = ROBSquashing;
879 // If we want to include the squashing instruction in the squash,
880 // then use one older sequence number.
881 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
883 if (fromIEW->includeSquashInst[tid]) {
887 // All younger instructions will be squashed. Set the sequence
888 // number as the youngest instruction in the ROB.
889 youngestSeqNum[tid] = squashed_inst;
891 rob->squash(squashed_inst, tid);
892 changedROBNumEntries[tid] = true;
894 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
896 toIEW->commitInfo[tid].squash = true;
898 // Send back the rob squashing signal so other stages know that
899 // the ROB is in the process of squashing.
900 toIEW->commitInfo[tid].robSquashing = true;
902 toIEW->commitInfo[tid].mispredictInst =
903 fromIEW->mispredictInst[tid];
904 toIEW->commitInfo[tid].branchTaken =
905 fromIEW->branchTaken[tid];
906 toIEW->commitInfo[tid].squashInst =
907 rob->findInst(tid, squashed_inst);
908 if (toIEW->commitInfo[tid].mispredictInst) {
909 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
910 toIEW->commitInfo[tid].branchTaken = true;
915 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
918 if (commitStatus[tid] == ROBSquashing) {
919 num_squashing_threads++;
923 // If commit is currently squashing, then it will have activity for the
924 // next cycle. Set its next status as active.
925 if (num_squashing_threads) {
926 _nextStatus = Active;
929 if (num_squashing_threads != numThreads) {
930 // If we're not currently squashing, then get instructions.
933 // Try to commit any instructions.
937 //Check for any activity
938 threads = activeThreads->begin();
940 while (threads != end) {
941 ThreadID tid = *threads++;
943 if (changedROBNumEntries[tid]) {
944 toIEW->commitInfo[tid].usedROB = true;
945 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
947 wroteToTimeBuffer = true;
948 changedROBNumEntries[tid] = false;
949 if (rob->isEmpty(tid))
950 checkEmptyROB[tid] = true;
953 // ROB is only considered "empty" for previous stages if: a)
954 // ROB is empty, b) there are no outstanding stores, c) IEW
955 // stage has received any information regarding stores that
957 // c) is checked by making sure to not consider the ROB empty
958 // on the same cycle as when stores have been committed.
959 // @todo: Make this handle multi-cycle communication between
961 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
962 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
963 checkEmptyROB[tid] = false;
964 toIEW->commitInfo[tid].usedROB = true;
965 toIEW->commitInfo[tid].emptyROB = true;
966 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
967 wroteToTimeBuffer = true;
973 template <class Impl>
975 DefaultCommit<Impl>::commitInsts()
977 ////////////////////////////////////
979 // Note that commit will be handled prior to putting new
980 // instructions in the ROB so that the ROB only tries to commit
981 // instructions it has in this current cycle, and not instructions
982 // it is writing in during this cycle. Can't commit and squash
983 // things at the same time...
984 ////////////////////////////////////
986 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
988 unsigned num_committed = 0;
990 DynInstPtr head_inst;
992 // Commit as many instructions as possible until the commit bandwidth
993 // limit is reached, or it becomes impossible to commit any more.
994 while (num_committed < commitWidth) {
995 // Check for any interrupt that we've already squashed for
996 // and start processing it.
997 if (interrupt != NoFault)
1000 ThreadID commit_thread = getCommittingThread();
1002 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1005 head_inst = rob->readHeadInst(commit_thread);
1007 ThreadID tid = head_inst->threadNumber;
1009 assert(tid == commit_thread);
1012 "Trying to commit head instruction, [tid:%i] [sn:%llu]\n",
1013 tid, head_inst->seqNum);
1015 // If the head instruction is squashed, it is ready to retire
1016 // (be removed from the ROB) at any time.
1017 if (head_inst->isSquashed()) {
1019 DPRINTF(Commit, "Retiring squashed instruction from "
1022 rob->retireHead(commit_thread);
1024 ++commitSquashedInsts;
1025 // Notify potential listeners that this instruction is squashed
1026 ppSquash->notify(head_inst);
1028 // Record that the number of ROB entries has changed.
1029 changedROBNumEntries[tid] = true;
1031 pc[tid] = head_inst->pcState();
1033 // Increment the total number of non-speculative instructions
1035 // Hack for now: it really shouldn't happen until after the
1036 // commit is deemed to be successful, but this count is needed
1038 thread[tid]->funcExeInst++;
1040 // Try to commit the head instruction.
1041 bool commit_success = commitHead(head_inst, num_committed);
1043 if (commit_success) {
1045 statCommittedInstType[tid][head_inst->opClass()]++;
1046 ppCommit->notify(head_inst);
1048 changedROBNumEntries[tid] = true;
1050 // Set the doneSeqNum to the youngest committed instruction.
1051 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1054 canHandleInterrupts = !head_inst->isDelayedCommit();
1056 // at this point store conditionals should either have
1057 // been completed or predicated false
1058 assert(!head_inst->isStoreConditional() ||
1059 head_inst->isCompleted() ||
1060 !head_inst->readPredicate());
1062 // Updates misc. registers.
1063 head_inst->updateMiscRegs();
1065 // Check instruction execution if it successfully commits and
1066 // is not carrying a fault.
1068 cpu->checker->verify(head_inst);
1071 cpu->traceFunctions(pc[tid].instAddr());
1073 TheISA::advancePC(pc[tid], head_inst->staticInst);
1075 // Keep track of the last sequence number commited
1076 lastCommitedSeqNum[tid] = head_inst->seqNum;
1078 // If this is an instruction that doesn't play nicely with
1079 // others squash everything and restart fetch
1080 if (head_inst->isSquashAfter())
1081 squashAfter(tid, head_inst);
1084 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1085 !thread[tid]->trapPending) {
1086 // Last architectually committed instruction.
1087 // Squash the pipeline, stall fetch, and use
1088 // drainImminent to disable interrupts
1089 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1090 squashAfter(tid, head_inst);
1091 cpu->commitDrained(tid);
1092 drainImminent = true;
1096 bool onInstBoundary = !head_inst->isMicroop() ||
1097 head_inst->isLastMicroop() ||
1098 !head_inst->isDelayedCommit();
1100 if (onInstBoundary) {
1103 // Make sure we're not currently updating state while
1104 // handling PC events.
1105 assert(!thread[tid]->noSquashFromTC &&
1106 !thread[tid]->trapPending);
1108 oldpc = pc[tid].instAddr();
1109 thread[tid]->pcEventQueue.service(
1110 oldpc, thread[tid]->getTC());
1112 } while (oldpc != pc[tid].instAddr());
1115 "PC skip function event, stopping commit\n");
1120 // Check if an instruction just enabled interrupts and we've
1121 // previously had an interrupt pending that was not handled
1122 // because interrupts were subsequently disabled before the
1123 // pipeline reached a place to handle the interrupt. In that
1124 // case squash now to make sure the interrupt is handled.
1126 // If we don't do this, we might end up in a live lock situation
1127 if (!interrupt && avoidQuiesceLiveLock &&
1128 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1129 squashAfter(tid, head_inst);
1131 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1132 "[tid:%i] [sn:%llu].\n",
1133 head_inst->pcState(), tid ,head_inst->seqNum);
1139 DPRINTF(CommitRate, "%i\n", num_committed);
1140 numCommittedDist.sample(num_committed);
1142 if (num_committed == commitWidth) {
1143 commitEligibleSamples++;
1147 template <class Impl>
1149 DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
1153 ThreadID tid = head_inst->threadNumber;
1155 // If the instruction is not executed yet, then it will need extra
1156 // handling. Signal backwards that it should be executed.
1157 if (!head_inst->isExecuted()) {
1158 // Keep this number correct. We have not yet actually executed
1159 // and committed this instruction.
1160 thread[tid]->funcExeInst--;
1162 // Make sure we are only trying to commit un-executed instructions we
1163 // think are possible.
1164 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1165 || head_inst->isMemBarrier() || head_inst->isWriteBarrier()
1166 || head_inst->isAtomic()
1167 || (head_inst->isLoad() && head_inst->strictlyOrdered()));
1170 "Encountered a barrier or non-speculative "
1171 "instruction [tid:%i] [sn:%llu] "
1172 "at the head of the ROB, PC %s.\n",
1173 tid, head_inst->seqNum, head_inst->pcState());
1175 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1177 "[tid:%i] [sn:%llu] "
1178 "Waiting for all stores to writeback.\n",
1179 tid, head_inst->seqNum);
1183 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1185 // Change the instruction so it won't try to commit again until
1187 head_inst->clearCanCommit();
1189 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1190 DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1191 "Strictly ordered load, PC %s.\n",
1192 tid, head_inst->seqNum, head_inst->pcState());
1193 toIEW->commitInfo[tid].strictlyOrdered = true;
1194 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1196 ++commitNonSpecStalls;
1202 if (head_inst->isThreadSync()) {
1203 // Not handled for now.
1204 panic("Thread sync instructions are not handled yet.\n");
1207 // Check if the instruction caused a fault. If so, trap.
1208 Fault inst_fault = head_inst->getFault();
1210 // Stores mark themselves as completed.
1211 if (!head_inst->isStore() && inst_fault == NoFault) {
1212 head_inst->setCompleted();
1215 if (inst_fault != NoFault) {
1216 DPRINTF(Commit, "Inst [tid:%i] [sn:%llu] PC %s has a fault\n",
1217 tid, head_inst->seqNum, head_inst->pcState());
1219 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1221 "[tid:%i] [sn:%llu] "
1222 "Stores outstanding, fault must wait.\n",
1223 tid, head_inst->seqNum);
1227 head_inst->setCompleted();
1229 // If instruction has faulted, let the checker execute it and
1230 // check if it sees the same fault and control flow.
1232 // Need to check the instruction before its fault is processed
1233 cpu->checker->verify(head_inst);
1236 assert(!thread[tid]->noSquashFromTC);
1238 // Mark that we're in state update mode so that the trap's
1239 // execution doesn't generate extra squashes.
1240 thread[tid]->noSquashFromTC = true;
1242 // Execute the trap. Although it's slightly unrealistic in
1243 // terms of timing (as it doesn't wait for the full timing of
1244 // the trap event to complete before updating state), it's
1245 // needed to update the state as soon as possible. This
1246 // prevents external agents from changing any specific state
1247 // that the trap need.
1248 cpu->trap(inst_fault, tid,
1249 head_inst->notAnInst() ?
1250 StaticInst::nullStaticInstPtr :
1251 head_inst->staticInst);
1253 // Exit state update mode to avoid accidental updating.
1254 thread[tid]->noSquashFromTC = false;
1256 commitStatus[tid] = TrapPending;
1259 "[tid:%i] [sn:%llu] Committing instruction with fault\n",
1260 tid, head_inst->seqNum);
1261 if (head_inst->traceData) {
1262 if (DTRACE(ExecFaulting)) {
1263 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1264 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1265 head_inst->traceData->dump();
1267 delete head_inst->traceData;
1268 head_inst->traceData = NULL;
1271 // Generate trap squash event.
1272 generateTrapEvent(tid, inst_fault);
1276 updateComInstStats(head_inst);
1279 if (thread[tid]->profile) {
1280 thread[tid]->profilePC = head_inst->instAddr();
1281 ProfileNode *node = thread[tid]->profile->consume(
1282 thread[tid]->getTC(), head_inst->staticInst);
1285 thread[tid]->profileNode = node;
1287 if (CPA::available()) {
1288 if (head_inst->isControl()) {
1289 ThreadContext *tc = thread[tid]->getTC();
1290 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1295 "[tid:%i] [sn:%llu] Committing instruction with PC %s\n",
1296 tid, head_inst->seqNum, head_inst->pcState());
1297 if (head_inst->traceData) {
1298 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1299 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1300 head_inst->traceData->dump();
1301 delete head_inst->traceData;
1302 head_inst->traceData = NULL;
1304 if (head_inst->isReturn()) {
1306 "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n",
1307 tid, head_inst->seqNum, head_inst->pcState());
1310 // Update the commit rename map
1311 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1312 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1313 head_inst->renamedDestRegIdx(i));
1316 // Finally clear the head ROB entry.
1317 rob->retireHead(tid);
1320 if (DTRACE(O3PipeView)) {
1321 head_inst->commitTick = curTick() - head_inst->fetchTick;
1325 // If this was a store, record it for this cycle.
1326 if (head_inst->isStore() || head_inst->isAtomic())
1327 committedStores[tid] = true;
1329 // Return true to indicate that we have committed an instruction.
1333 template <class Impl>
1335 DefaultCommit<Impl>::getInsts()
1337 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1339 // Read any renamed instructions and place them into the ROB.
1340 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1342 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1343 const DynInstPtr &inst = fromRename->insts[inst_num];
1344 ThreadID tid = inst->threadNumber;
1346 if (!inst->isSquashed() &&
1347 commitStatus[tid] != ROBSquashing &&
1348 commitStatus[tid] != TrapPending) {
1349 changedROBNumEntries[tid] = true;
1351 DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n",
1352 inst->seqNum, tid, inst->pcState());
1354 rob->insertInst(inst);
1356 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1358 youngestSeqNum[tid] = inst->seqNum;
1360 DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1361 "Instruction PC %s was squashed, skipping.\n",
1362 inst->seqNum, tid, inst->pcState());
1367 template <class Impl>
1369 DefaultCommit<Impl>::markCompletedInsts()
1371 // Grab completed insts out of the IEW instruction queue, and mark
1372 // instructions completed within the ROB.
1373 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1374 assert(fromIEW->insts[inst_num]);
1375 if (!fromIEW->insts[inst_num]->isSquashed()) {
1376 DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%llu] ready "
1378 fromIEW->insts[inst_num]->threadNumber,
1379 fromIEW->insts[inst_num]->pcState(),
1380 fromIEW->insts[inst_num]->seqNum);
1382 // Mark the instruction as ready to commit.
1383 fromIEW->insts[inst_num]->setCanCommit();
1388 template <class Impl>
1390 DefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst)
1392 ThreadID tid = inst->threadNumber;
1394 if (!inst->isMicroop() || inst->isLastMicroop())
1395 instsCommitted[tid]++;
1396 opsCommitted[tid]++;
1398 // To match the old model, don't count nops and instruction
1399 // prefetches towards the total commit count.
1400 if (!inst->isNop() && !inst->isInstPrefetch()) {
1401 cpu->instDone(tid, inst);
1405 // Control Instructions
1407 if (inst->isControl())
1408 statComBranches[tid]++;
1411 // Memory references
1413 if (inst->isMemRef()) {
1416 if (inst->isLoad()) {
1417 statComLoads[tid]++;
1420 if (inst->isAtomic()) {
1425 if (inst->isMemBarrier()) {
1426 statComMembars[tid]++;
1429 // Integer Instruction
1430 if (inst->isInteger())
1431 statComInteger[tid]++;
1433 // Floating Point Instruction
1434 if (inst->isFloating())
1435 statComFloating[tid]++;
1436 // Vector Instruction
1437 if (inst->isVector())
1438 statComVector[tid]++;
1442 statComFunctionCalls[tid]++;
1446 ////////////////////////////////////////
1448 // SMT COMMIT POLICY MAINTAINED HERE //
1450 ////////////////////////////////////////
1451 template <class Impl>
1453 DefaultCommit<Impl>::getCommittingThread()
1455 if (numThreads > 1) {
1456 switch (commitPolicy) {
1458 case CommitPolicy::Aggressive:
1459 //If Policy is Aggressive, commit will call
1460 //this function multiple times per
1462 return oldestReady();
1464 case CommitPolicy::RoundRobin:
1465 return roundRobin();
1467 case CommitPolicy::OldestReady:
1468 return oldestReady();
1471 return InvalidThreadID;
1474 assert(!activeThreads->empty());
1475 ThreadID tid = activeThreads->front();
1477 if (commitStatus[tid] == Running ||
1478 commitStatus[tid] == Idle ||
1479 commitStatus[tid] == FetchTrapPending) {
1482 return InvalidThreadID;
1487 template<class Impl>
1489 DefaultCommit<Impl>::roundRobin()
1491 list<ThreadID>::iterator pri_iter = priority_list.begin();
1492 list<ThreadID>::iterator end = priority_list.end();
1494 while (pri_iter != end) {
1495 ThreadID tid = *pri_iter;
1497 if (commitStatus[tid] == Running ||
1498 commitStatus[tid] == Idle ||
1499 commitStatus[tid] == FetchTrapPending) {
1501 if (rob->isHeadReady(tid)) {
1502 priority_list.erase(pri_iter);
1503 priority_list.push_back(tid);
1512 return InvalidThreadID;
1515 template<class Impl>
1517 DefaultCommit<Impl>::oldestReady()
1519 unsigned oldest = 0;
1522 list<ThreadID>::iterator threads = activeThreads->begin();
1523 list<ThreadID>::iterator end = activeThreads->end();
1525 while (threads != end) {
1526 ThreadID tid = *threads++;
1528 if (!rob->isEmpty(tid) &&
1529 (commitStatus[tid] == Running ||
1530 commitStatus[tid] == Idle ||
1531 commitStatus[tid] == FetchTrapPending)) {
1533 if (rob->isHeadReady(tid)) {
1535 const DynInstPtr &head_inst = rob->readHeadInst(tid);
1540 } else if (head_inst->seqNum < oldest) {
1550 return InvalidThreadID;
1554 #endif//__CPU_O3_COMMIT_IMPL_HH__