2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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32 #include "base/loader/symtab.hh"
33 #include "base/timebuf.hh"
34 #include "cpu/checker/cpu.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/o3/commit.hh"
37 #include "cpu/o3/thread_state.hh"
42 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
44 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
46 this->setFlags(Event::AutoDelete);
51 DefaultCommit<Impl>::TrapEvent::process()
53 // This will get reset by commit if it was switched out at the
54 // time of this event processing.
55 commit->trapSquash[tid] = true;
60 DefaultCommit<Impl>::TrapEvent::description()
66 DefaultCommit<Impl>::DefaultCommit(Params *params)
67 : dcacheInterface(params->dcacheInterface),
69 iewToCommitDelay(params->iewToCommitDelay),
70 commitToIEWDelay(params->commitToIEWDelay),
71 renameToROBDelay(params->renameToROBDelay),
72 fetchToCommitDelay(params->commitToFetchDelay),
73 renameWidth(params->renameWidth),
74 iewWidth(params->executeWidth),
75 commitWidth(params->commitWidth),
76 numThreads(params->numberOfThreads),
78 trapLatency(params->trapLatency),
79 fetchTrapLatency(params->fetchTrapLatency)
82 _nextStatus = Inactive;
83 string policy = params->smtCommitPolicy;
85 //Convert string to lowercase
86 std::transform(policy.begin(), policy.end(), policy.begin(),
87 (int(*)(int)) tolower);
89 //Assign commit policy
90 if (policy == "aggressive"){
91 commitPolicy = Aggressive;
93 DPRINTF(Commit,"Commit Policy set to Aggressive.");
94 } else if (policy == "roundrobin"){
95 commitPolicy = RoundRobin;
97 //Set-Up Priority List
98 for (int tid=0; tid < numThreads; tid++) {
99 priority_list.push_back(tid);
102 DPRINTF(Commit,"Commit Policy set to Round Robin.");
103 } else if (policy == "oldestready"){
104 commitPolicy = OldestReady;
106 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
108 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
109 "RoundRobin,OldestReady}");
112 for (int i=0; i < numThreads; i++) {
113 commitStatus[i] = Idle;
114 changedROBNumEntries[i] = false;
115 trapSquash[i] = false;
123 template <class Impl>
125 DefaultCommit<Impl>::name() const
127 return cpu->name() + ".commit";
130 template <class Impl>
132 DefaultCommit<Impl>::regStats()
134 using namespace Stats;
136 .name(name() + ".commitCommittedInsts")
137 .desc("The number of committed instructions")
138 .prereq(commitCommittedInsts);
140 .name(name() + ".commitSquashedInsts")
141 .desc("The number of squashed insts skipped by commit")
142 .prereq(commitSquashedInsts);
144 .name(name() + ".commitSquashEvents")
145 .desc("The number of times commit is told to squash")
146 .prereq(commitSquashEvents);
148 .name(name() + ".commitNonSpecStalls")
149 .desc("The number of times commit has been forced to stall to "
150 "communicate backwards")
151 .prereq(commitNonSpecStalls);
153 .name(name() + ".branchMispredicts")
154 .desc("The number of times a branch was mispredicted")
155 .prereq(branchMispredicts);
157 .init(0,commitWidth,1)
158 .name(name() + ".COM:committed_per_cycle")
159 .desc("Number of insts commited each cycle")
164 .init(cpu->number_of_threads)
165 .name(name() + ".COM:count")
166 .desc("Number of instructions committed")
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:swp_count")
173 .desc("Number of s/w prefetches committed")
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:refs")
180 .desc("Number of memory references committed")
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:loads")
187 .desc("Number of loads committed")
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:membars")
194 .desc("Number of memory barriers committed")
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:branches")
201 .desc("Number of branches committed")
206 // Commit-Eligible instructions...
208 // -> The number of instructions eligible to commit in those
209 // cycles where we reached our commit BW limit (less the number
210 // actually committed)
212 // -> The average value is computed over ALL CYCLES... not just
213 // the BW limited cycles
215 // -> The standard deviation is computed only over cycles where
216 // we reached the BW limit
219 .init(cpu->number_of_threads)
220 .name(name() + ".COM:bw_limited")
221 .desc("number of insts not committed due to BW limits")
225 commitEligibleSamples
226 .name(name() + ".COM:bw_lim_events")
227 .desc("number cycles where commit BW limit reached")
231 template <class Impl>
233 DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
235 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
238 // Commit must broadcast the number of free entries it has at the start of
239 // the simulation, so it starts as active.
240 cpu->activateStage(FullCPU::CommitIdx);
242 trapLatency = cpu->cycles(trapLatency);
243 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
246 template <class Impl>
248 DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
253 template <class Impl>
255 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
257 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
260 // Setup wire to send information back to IEW.
261 toIEW = timeBuffer->getWire(0);
263 // Setup wire to read data from IEW (for the ROB).
264 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
267 template <class Impl>
269 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
271 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
274 // Setup wire to get instructions from rename (for the ROB).
275 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
278 template <class Impl>
280 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
282 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
283 renameQueue = rq_ptr;
285 // Setup wire to get instructions from rename (for the ROB).
286 fromRename = renameQueue->getWire(-renameToROBDelay);
289 template <class Impl>
291 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
293 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
296 // Setup wire to get instructions from IEW.
297 fromIEW = iewQueue->getWire(-iewToCommitDelay);
300 template <class Impl>
302 DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
304 fetchStage = fetch_stage;
307 template <class Impl>
309 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
311 iewStage = iew_stage;
316 DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
318 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
319 activeThreads = at_ptr;
322 template <class Impl>
324 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
326 DPRINTF(Commit, "Setting rename map pointers.\n");
328 for (int i=0; i < numThreads; i++) {
329 renameMap[i] = &rm_ptr[i];
333 template <class Impl>
335 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
337 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
341 template <class Impl>
343 DefaultCommit<Impl>::initStage()
345 rob->setActiveThreads(activeThreads);
348 // Broadcast the number of free entries.
349 for (int i=0; i < numThreads; i++) {
350 toIEW->commitInfo[i].usedROB = true;
351 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
354 cpu->activityThisCycle();
357 template <class Impl>
359 DefaultCommit<Impl>::switchOut()
361 switchPending = true;
364 template <class Impl>
366 DefaultCommit<Impl>::doSwitchOut()
369 switchPending = false;
373 template <class Impl>
375 DefaultCommit<Impl>::takeOverFrom()
379 _nextStatus = Inactive;
380 for (int i=0; i < numThreads; i++) {
381 commitStatus[i] = Idle;
382 changedROBNumEntries[i] = false;
383 trapSquash[i] = false;
390 template <class Impl>
392 DefaultCommit<Impl>::updateStatus()
394 // reset ROB changed variable
395 list<unsigned>::iterator threads = (*activeThreads).begin();
396 while (threads != (*activeThreads).end()) {
397 unsigned tid = *threads++;
398 changedROBNumEntries[tid] = false;
400 // Also check if any of the threads has a trap pending
401 if (commitStatus[tid] == TrapPending ||
402 commitStatus[tid] == FetchTrapPending) {
403 _nextStatus = Active;
407 if (_nextStatus == Inactive && _status == Active) {
408 DPRINTF(Activity, "Deactivating stage.\n");
409 cpu->deactivateStage(FullCPU::CommitIdx);
410 } else if (_nextStatus == Active && _status == Inactive) {
411 DPRINTF(Activity, "Activating stage.\n");
412 cpu->activateStage(FullCPU::CommitIdx);
415 _status = _nextStatus;
418 template <class Impl>
420 DefaultCommit<Impl>::setNextStatus()
424 list<unsigned>::iterator threads = (*activeThreads).begin();
426 while (threads != (*activeThreads).end()) {
427 unsigned tid = *threads++;
429 if (commitStatus[tid] == ROBSquashing) {
434 assert(squashes == squashCounter);
436 // If commit is currently squashing, then it will have activity for the
437 // next cycle. Set its next status as active.
439 _nextStatus = Active;
443 template <class Impl>
445 DefaultCommit<Impl>::changedROBEntries()
447 list<unsigned>::iterator threads = (*activeThreads).begin();
449 while (threads != (*activeThreads).end()) {
450 unsigned tid = *threads++;
452 if (changedROBNumEntries[tid]) {
460 template <class Impl>
462 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
464 return rob->numFreeEntries(tid);
467 template <class Impl>
469 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
473 TrapEvent *trap = new TrapEvent(this, tid);
475 trap->schedule(curTick + trapLatency);
477 thread[tid]->trapPending = true;
480 template <class Impl>
482 DefaultCommit<Impl>::generateXCEvent(unsigned tid)
484 DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
486 xcSquash[tid] = true;
489 template <class Impl>
491 DefaultCommit<Impl>::squashAll(unsigned tid)
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
498 0 : rob->readHeadInst(tid)->seqNum - 1;;
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
511 // Send back the squash signal to tell stages that they should
513 toIEW->commitInfo[tid].squash = true;
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
519 toIEW->commitInfo[tid].branchMispredict = false;
521 toIEW->commitInfo[tid].nextPC = PC[tid];
524 template <class Impl>
526 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
530 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
532 thread[tid]->trapPending = false;
533 thread[tid]->inSyscall = false;
535 trapSquash[tid] = false;
537 commitStatus[tid] = ROBSquashing;
538 cpu->activityThisCycle();
543 template <class Impl>
545 DefaultCommit<Impl>::squashFromXC(unsigned tid)
549 DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
551 thread[tid]->inSyscall = false;
552 assert(!thread[tid]->trapPending);
554 commitStatus[tid] = ROBSquashing;
555 cpu->activityThisCycle();
557 xcSquash[tid] = false;
562 template <class Impl>
564 DefaultCommit<Impl>::tick()
566 wroteToTimeBuffer = false;
567 _nextStatus = Inactive;
569 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
570 cpu->signalSwitched();
574 list<unsigned>::iterator threads = (*activeThreads).begin();
576 // Check if any of the threads are done squashing. Change the
577 // status if they are done.
578 while (threads != (*activeThreads).end()) {
579 unsigned tid = *threads++;
581 if (commitStatus[tid] == ROBSquashing) {
583 if (rob->isDoneSquashing(tid)) {
584 commitStatus[tid] = Running;
587 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
588 "insts this cycle.\n", tid);
595 markCompletedInsts();
597 threads = (*activeThreads).begin();
599 while (threads != (*activeThreads).end()) {
600 unsigned tid = *threads++;
602 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
603 // The ROB has more instructions it can commit. Its next status
605 _nextStatus = Active;
607 DynInstPtr inst = rob->readHeadInst(tid);
609 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
610 " ROB and ready to commit\n",
611 tid, inst->seqNum, inst->readPC());
613 } else if (!rob->isEmpty(tid)) {
614 DynInstPtr inst = rob->readHeadInst(tid);
616 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
617 "%#x is head of ROB and not ready\n",
618 tid, inst->seqNum, inst->readPC());
621 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
622 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
626 if (wroteToTimeBuffer) {
627 DPRINTF(Activity, "Activity This Cycle.\n");
628 cpu->activityThisCycle();
634 template <class Impl>
636 DefaultCommit<Impl>::commit()
639 //////////////////////////////////////
640 // Check for interrupts
641 //////////////////////////////////////
644 // Process interrupts if interrupts are enabled, not in PAL mode,
645 // and no other traps or external squashes are currently pending.
646 // @todo: Allow other threads to handle interrupts.
647 if (cpu->checkInterrupts &&
648 cpu->check_interrupts() &&
649 !cpu->inPalMode(readPC()) &&
652 // Tell fetch that there is an interrupt pending. This will
653 // make fetch wait until it sees a non PAL-mode PC, at which
654 // point it stops fetching instructions.
655 toIEW->commitInfo[0].interruptPending = true;
657 // Wait until the ROB is empty and all stores have drained in
658 // order to enter the interrupt.
659 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
660 // Not sure which thread should be the one to interrupt. For now
661 // always do thread 0.
662 assert(!thread[0]->inSyscall);
663 thread[0]->inSyscall = true;
665 // CPU will handle implementation of the interrupt.
666 cpu->processInterrupts();
668 // Now squash or record that I need to squash this cycle.
669 commitStatus[0] = TrapPending;
671 // Exit state update mode to avoid accidental updating.
672 thread[0]->inSyscall = false;
674 // Generate trap squash event.
675 generateTrapEvent(0);
677 toIEW->commitInfo[0].clearInterrupt = true;
679 DPRINTF(Commit, "Interrupt detected.\n");
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
684 #endif // FULL_SYSTEM
686 ////////////////////////////////////
687 // Check for any possible squashes, handle them first
688 ////////////////////////////////////
690 list<unsigned>::iterator threads = (*activeThreads).begin();
692 while (threads != (*activeThreads).end()) {
693 unsigned tid = *threads++;
695 if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
696 // Record the fault. Wait until it's empty in the ROB.
697 // Then handle the trap. Ignore it if there's already a
698 // trap pending as fetch will be redirected.
699 fetchFault = fromFetch->fetchFault;
700 fetchFaultTick = curTick + fetchTrapLatency;
701 commitStatus[0] = FetchTrapPending;
702 DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
703 "ROB empties without squashing the fault.\n");
707 // Fetch may tell commit to clear the trap if it's been squashed.
708 if (fromFetch->clearFetchFault) {
709 DPRINTF(Commit, "Received clear fetch fault signal\n");
711 if (commitStatus[0] == FetchTrapPending) {
712 DPRINTF(Commit, "Clearing fault from fetch\n");
713 commitStatus[0] = Running;
717 // Not sure which one takes priority. I think if we have
718 // both, that's a bad sign.
719 if (trapSquash[tid] == true) {
720 assert(!xcSquash[tid]);
722 } else if (xcSquash[tid] == true) {
726 // Squashed sequence number must be older than youngest valid
727 // instruction in the ROB. This prevents squashes from younger
728 // instructions overriding squashes from older instructions.
729 if (fromIEW->squash[tid] &&
730 commitStatus[tid] != TrapPending &&
731 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
733 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
735 fromIEW->mispredPC[tid],
736 fromIEW->squashedSeqNum[tid]);
738 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
740 fromIEW->nextPC[tid]);
742 commitStatus[tid] = ROBSquashing;
746 // If we want to include the squashing instruction in the squash,
747 // then use one older sequence number.
748 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
750 if (fromIEW->includeSquashInst[tid] == true)
753 // All younger instructions will be squashed. Set the sequence
754 // number as the youngest instruction in the ROB.
755 youngestSeqNum[tid] = squashed_inst;
757 rob->squash(squashed_inst, tid);
758 changedROBNumEntries[tid] = true;
760 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
762 toIEW->commitInfo[tid].squash = true;
764 // Send back the rob squashing signal so other stages know that
765 // the ROB is in the process of squashing.
766 toIEW->commitInfo[tid].robSquashing = true;
768 toIEW->commitInfo[tid].branchMispredict =
769 fromIEW->branchMispredict[tid];
771 toIEW->commitInfo[tid].branchTaken =
772 fromIEW->branchTaken[tid];
774 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
776 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
778 if (toIEW->commitInfo[tid].branchMispredict) {
787 if (squashCounter != numThreads) {
788 // If we're not currently squashing, then get instructions.
791 // Try to commit any instructions.
795 //Check for any activity
796 threads = (*activeThreads).begin();
798 while (threads != (*activeThreads).end()) {
799 unsigned tid = *threads++;
801 if (changedROBNumEntries[tid]) {
802 toIEW->commitInfo[tid].usedROB = true;
803 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
805 if (rob->isEmpty(tid)) {
806 toIEW->commitInfo[tid].emptyROB = true;
809 wroteToTimeBuffer = true;
810 changedROBNumEntries[tid] = false;
815 template <class Impl>
817 DefaultCommit<Impl>::commitInsts()
819 ////////////////////////////////////
821 // Note that commit will be handled prior to putting new
822 // instructions in the ROB so that the ROB only tries to commit
823 // instructions it has in this current cycle, and not instructions
824 // it is writing in during this cycle. Can't commit and squash
825 // things at the same time...
826 ////////////////////////////////////
828 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
830 unsigned num_committed = 0;
832 DynInstPtr head_inst;
834 // Commit as many instructions as possible until the commit bandwidth
835 // limit is reached, or it becomes impossible to commit any more.
836 while (num_committed < commitWidth) {
837 int commit_thread = getCommittingThread();
839 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
842 head_inst = rob->readHeadInst(commit_thread);
844 int tid = head_inst->threadNumber;
846 assert(tid == commit_thread);
848 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
849 head_inst->seqNum, tid);
851 // If the head instruction is squashed, it is ready to retire
852 // (be removed from the ROB) at any time.
853 if (head_inst->isSquashed()) {
855 DPRINTF(Commit, "Retiring squashed instruction from "
858 rob->retireHead(commit_thread);
860 ++commitSquashedInsts;
862 // Record that the number of ROB entries has changed.
863 changedROBNumEntries[tid] = true;
865 PC[tid] = head_inst->readPC();
866 nextPC[tid] = head_inst->readNextPC();
868 // Increment the total number of non-speculative instructions
870 // Hack for now: it really shouldn't happen until after the
871 // commit is deemed to be successful, but this count is needed
873 thread[tid]->funcExeInst++;
875 // Try to commit the head instruction.
876 bool commit_success = commitHead(head_inst, num_committed);
878 if (commit_success) {
881 changedROBNumEntries[tid] = true;
883 // Set the doneSeqNum to the youngest committed instruction.
884 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
886 ++commitCommittedInsts;
888 // To match the old model, don't count nops and instruction
889 // prefetches towards the total commit count.
890 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
894 PC[tid] = nextPC[tid];
895 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
900 // Debug statement. Checks to make sure we're not
901 // currently updating state while handling PC events.
903 assert(!thread[tid]->inSyscall &&
904 !thread[tid]->trapPending);
906 cpu->system->pcEventQueue.service(
907 thread[tid]->getXCProxy());
909 } while (oldpc != PC[tid]);
911 DPRINTF(Commit, "PC skip function event, stopping commit\n");
916 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
917 "[tid:%i] [sn:%i].\n",
918 head_inst->readPC(), tid ,head_inst->seqNum);
924 DPRINTF(CommitRate, "%i\n", num_committed);
925 numCommittedDist.sample(num_committed);
927 if (num_committed == commitWidth) {
932 template <class Impl>
934 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
938 int tid = head_inst->threadNumber;
940 // If the instruction is not executed yet, then it will need extra
941 // handling. Signal backwards that it should be executed.
942 if (!head_inst->isExecuted()) {
943 // Keep this number correct. We have not yet actually executed
944 // and committed this instruction.
945 thread[tid]->funcExeInst--;
947 head_inst->reachedCommit = true;
949 if (head_inst->isNonSpeculative() ||
950 head_inst->isMemBarrier() ||
951 head_inst->isWriteBarrier()) {
953 DPRINTF(Commit, "Encountered a barrier or non-speculative "
954 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
955 head_inst->seqNum, head_inst->readPC());
958 // Hack to make sure syscalls/memory barriers/quiesces
959 // aren't executed until all stores write back their data.
960 // This direct communication shouldn't be used for
961 // anything other than this.
962 if (inst_num > 0 || iewStage->hasStoresToWB())
964 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
965 head_inst->isQuiesce()) &&
966 iewStage->hasStoresToWB())
969 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
973 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
975 // Change the instruction so it won't try to commit again until
977 head_inst->clearCanCommit();
979 ++commitNonSpecStalls;
982 } else if (head_inst->isLoad()) {
983 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
984 head_inst->seqNum, head_inst->readPC());
986 // Send back the non-speculative instruction's sequence
987 // number. Tell the lsq to re-execute the load.
988 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
989 toIEW->commitInfo[tid].uncached = true;
990 toIEW->commitInfo[tid].uncachedLoad = head_inst;
992 head_inst->clearCanCommit();
996 panic("Trying to commit un-executed instruction "
997 "of unknown type!\n");
1001 if (head_inst->isThreadSync()) {
1002 // Not handled for now.
1003 panic("Thread sync instructions are not handled yet.\n");
1006 // Stores mark themselves as completed.
1007 if (!head_inst->isStore()) {
1008 head_inst->setCompleted();
1011 // Use checker prior to updating anything due to traps or PC
1014 cpu->checker->tick(head_inst);
1017 // Check if the instruction caused a fault. If so, trap.
1018 Fault inst_fault = head_inst->getFault();
1020 if (inst_fault != NoFault) {
1021 head_inst->setCompleted();
1023 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1024 head_inst->seqNum, head_inst->readPC());
1026 if (iewStage->hasStoresToWB() || inst_num > 0) {
1027 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1031 if (cpu->checker && head_inst->isStore()) {
1032 cpu->checker->tick(head_inst);
1035 assert(!thread[tid]->inSyscall);
1037 // Mark that we're in state update mode so that the trap's
1038 // execution doesn't generate extra squashes.
1039 thread[tid]->inSyscall = true;
1041 // DTB will sometimes need the machine instruction for when
1042 // faults happen. So we will set it here, prior to the DTB
1043 // possibly needing it for its fault.
1044 thread[tid]->setInst(
1045 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1047 // Execute the trap. Although it's slightly unrealistic in
1048 // terms of timing (as it doesn't wait for the full timing of
1049 // the trap event to complete before updating state), it's
1050 // needed to update the state as soon as possible. This
1051 // prevents external agents from changing any specific state
1052 // that the trap need.
1053 cpu->trap(inst_fault, tid);
1055 // Exit state update mode to avoid accidental updating.
1056 thread[tid]->inSyscall = false;
1058 commitStatus[tid] = TrapPending;
1060 // Generate trap squash event.
1061 generateTrapEvent(tid);
1064 #else // !FULL_SYSTEM
1065 panic("fault (%d) detected @ PC %08p", inst_fault,
1067 #endif // FULL_SYSTEM
1070 updateComInstStats(head_inst);
1072 if (head_inst->traceData) {
1073 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1074 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1075 head_inst->traceData->finalize();
1076 head_inst->traceData = NULL;
1079 // Update the commit rename map
1080 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1081 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1082 head_inst->renamedDestRegIdx(i));
1085 // Finally clear the head ROB entry.
1086 rob->retireHead(tid);
1088 // Return true to indicate that we have committed an instruction.
1092 template <class Impl>
1094 DefaultCommit<Impl>::getInsts()
1096 // Read any renamed instructions and place them into the ROB.
1097 int insts_to_process = min((int)renameWidth, fromRename->size);
1099 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1101 DynInstPtr inst = fromRename->insts[inst_num];
1102 int tid = inst->threadNumber;
1104 if (!inst->isSquashed() &&
1105 commitStatus[tid] != ROBSquashing) {
1106 changedROBNumEntries[tid] = true;
1108 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1109 inst->readPC(), inst->seqNum, tid);
1111 rob->insertInst(inst);
1113 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1115 youngestSeqNum[tid] = inst->seqNum;
1117 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1118 "squashed, skipping.\n",
1119 inst->readPC(), inst->seqNum, tid);
1124 template <class Impl>
1126 DefaultCommit<Impl>::markCompletedInsts()
1128 // Grab completed insts out of the IEW instruction queue, and mark
1129 // instructions completed within the ROB.
1130 for (int inst_num = 0;
1131 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1134 if (!fromIEW->insts[inst_num]->isSquashed()) {
1135 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1137 fromIEW->insts[inst_num]->threadNumber,
1138 fromIEW->insts[inst_num]->readPC(),
1139 fromIEW->insts[inst_num]->seqNum);
1141 // Mark the instruction as ready to commit.
1142 fromIEW->insts[inst_num]->setCanCommit();
1147 template <class Impl>
1149 DefaultCommit<Impl>::robDoneSquashing()
1151 list<unsigned>::iterator threads = (*activeThreads).begin();
1153 while (threads != (*activeThreads).end()) {
1154 unsigned tid = *threads++;
1156 if (!rob->isDoneSquashing(tid))
1163 template <class Impl>
1165 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1167 unsigned thread = inst->threadNumber;
1170 // Pick off the software prefetches
1173 if (inst->isDataPrefetch()) {
1174 statComSwp[thread]++;
1176 statComInst[thread]++;
1179 statComInst[thread]++;
1183 // Control Instructions
1185 if (inst->isControl())
1186 statComBranches[thread]++;
1189 // Memory references
1191 if (inst->isMemRef()) {
1192 statComRefs[thread]++;
1194 if (inst->isLoad()) {
1195 statComLoads[thread]++;
1199 if (inst->isMemBarrier()) {
1200 statComMembars[thread]++;
1204 ////////////////////////////////////////
1206 // SMT COMMIT POLICY MAINTAINED HERE //
1208 ////////////////////////////////////////
1209 template <class Impl>
1211 DefaultCommit<Impl>::getCommittingThread()
1213 if (numThreads > 1) {
1214 switch (commitPolicy) {
1217 //If Policy is Aggressive, commit will call
1218 //this function multiple times per
1220 return oldestReady();
1223 return roundRobin();
1226 return oldestReady();
1232 int tid = (*activeThreads).front();
1234 if (commitStatus[tid] == Running ||
1235 commitStatus[tid] == Idle ||
1236 commitStatus[tid] == FetchTrapPending) {
1244 template<class Impl>
1246 DefaultCommit<Impl>::roundRobin()
1248 list<unsigned>::iterator pri_iter = priority_list.begin();
1249 list<unsigned>::iterator end = priority_list.end();
1251 while (pri_iter != end) {
1252 unsigned tid = *pri_iter;
1254 if (commitStatus[tid] == Running ||
1255 commitStatus[tid] == Idle) {
1257 if (rob->isHeadReady(tid)) {
1258 priority_list.erase(pri_iter);
1259 priority_list.push_back(tid);
1271 template<class Impl>
1273 DefaultCommit<Impl>::oldestReady()
1275 unsigned oldest = 0;
1278 list<unsigned>::iterator threads = (*activeThreads).begin();
1280 while (threads != (*activeThreads).end()) {
1281 unsigned tid = *threads++;
1283 if (!rob->isEmpty(tid) &&
1284 (commitStatus[tid] == Running ||
1285 commitStatus[tid] == Idle ||
1286 commitStatus[tid] == FetchTrapPending)) {
1288 if (rob->isHeadReady(tid)) {
1290 DynInstPtr head_inst = rob->readHeadInst(tid);
1295 } else if (head_inst->seqNum < oldest) {