src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include "config/full_system.hh"
  33 #include "config/use_checker.hh"
  34
  35 #include <algorithm>
  36 #include <string>
  37
  38 #include "base/loader/symtab.hh"
  39 #include "base/timebuf.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "cpu/o3/commit.hh"
  42 #include "cpu/o3/thread_state.hh"
  43
  44 #if USE_CHECKER
  45 #include "cpu/checker/cpu.hh"
  46 #endif
  47
  48 template <class Impl>
  49 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  50                                           unsigned _tid)
  51     : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
  52 {
  53     this->setFlags(Event::AutoDelete);
  54 }
  55
  56 template <class Impl>
  57 void
  58 DefaultCommit<Impl>::TrapEvent::process()
  59 {
  60     // This will get reset by commit if it was switched out at the
  61     // time of this event processing.
  62     commit->trapSquash[tid] = true;
  63 }
  64
  65 template <class Impl>
  66 const char *
  67 DefaultCommit<Impl>::TrapEvent::description()
  68 {
  69     return "Trap event";
  70 }
  71
  72 template <class Impl>
  73 DefaultCommit<Impl>::DefaultCommit(Params *params)
  74     : squashCounter(0),
  75       iewToCommitDelay(params->iewToCommitDelay),
  76       commitToIEWDelay(params->commitToIEWDelay),
  77       renameToROBDelay(params->renameToROBDelay),
  78       fetchToCommitDelay(params->commitToFetchDelay),
  79       renameWidth(params->renameWidth),
  80       commitWidth(params->commitWidth),
  81       numThreads(params->numberOfThreads),
  82       drainPending(false),
  83       switchedOut(false),
  84       trapLatency(params->trapLatency)
  85 {
  86     _status = Active;
  87     _nextStatus = Inactive;
  88     std::string policy = params->smtCommitPolicy;
  89
  90     //Convert string to lowercase
  91     std::transform(policy.begin(), policy.end(), policy.begin(),
  92                    (int(*)(int)) tolower);
  93
  94     //Assign commit policy
  95     if (policy == "aggressive"){
  96         commitPolicy = Aggressive;
  97
  98         DPRINTF(Commit,"Commit Policy set to Aggressive.");
  99     } else if (policy == "roundrobin"){
 100         commitPolicy = RoundRobin;
 101
 102         //Set-Up Priority List
 103         for (int tid=0; tid < numThreads; tid++) {
 104             priority_list.push_back(tid);
 105         }
 106
 107         DPRINTF(Commit,"Commit Policy set to Round Robin.");
 108     } else if (policy == "oldestready"){
 109         commitPolicy = OldestReady;
 110
 111         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 112     } else {
 113         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 114                "RoundRobin,OldestReady}");
 115     }
 116
 117     for (int i=0; i < numThreads; i++) {
 118         commitStatus[i] = Idle;
 119         changedROBNumEntries[i] = false;
 120         trapSquash[i] = false;
 121         tcSquash[i] = false;
 122         PC[i] = nextPC[i] = nextNPC[i] = 0;
 123     }
 124 }
 125
 126 template <class Impl>
 127 std::string
 128 DefaultCommit<Impl>::name() const
 129 {
 130     return cpu->name() + ".commit";
 131 }
 132
 133 template <class Impl>
 134 void
 135 DefaultCommit<Impl>::regStats()
 136 {
 137     using namespace Stats;
 138     commitCommittedInsts
 139         .name(name() + ".commitCommittedInsts")
 140         .desc("The number of committed instructions")
 141         .prereq(commitCommittedInsts);
 142     commitSquashedInsts
 143         .name(name() + ".commitSquashedInsts")
 144         .desc("The number of squashed insts skipped by commit")
 145         .prereq(commitSquashedInsts);
 146     commitSquashEvents
 147         .name(name() + ".commitSquashEvents")
 148         .desc("The number of times commit is told to squash")
 149         .prereq(commitSquashEvents);
 150     commitNonSpecStalls
 151         .name(name() + ".commitNonSpecStalls")
 152         .desc("The number of times commit has been forced to stall to "
 153               "communicate backwards")
 154         .prereq(commitNonSpecStalls);
 155     branchMispredicts
 156         .name(name() + ".branchMispredicts")
 157         .desc("The number of times a branch was mispredicted")
 158         .prereq(branchMispredicts);
 159     numCommittedDist
 160         .init(0,commitWidth,1)
 161         .name(name() + ".COM:committed_per_cycle")
 162         .desc("Number of insts commited each cycle")
 163         .flags(Stats::pdf)
 164         ;
 165
 166     statComInst
 167         .init(cpu->number_of_threads)
 168         .name(name() + ".COM:count")
 169         .desc("Number of instructions committed")
 170         .flags(total)
 171         ;
 172
 173     statComSwp
 174         .init(cpu->number_of_threads)
 175         .name(name() + ".COM:swp_count")
 176         .desc("Number of s/w prefetches committed")
 177         .flags(total)
 178         ;
 179
 180     statComRefs
 181         .init(cpu->number_of_threads)
 182         .name(name() +  ".COM:refs")
 183         .desc("Number of memory references committed")
 184         .flags(total)
 185         ;
 186
 187     statComLoads
 188         .init(cpu->number_of_threads)
 189         .name(name() +  ".COM:loads")
 190         .desc("Number of loads committed")
 191         .flags(total)
 192         ;
 193
 194     statComMembars
 195         .init(cpu->number_of_threads)
 196         .name(name() +  ".COM:membars")
 197         .desc("Number of memory barriers committed")
 198         .flags(total)
 199         ;
 200
 201     statComBranches
 202         .init(cpu->number_of_threads)
 203         .name(name() + ".COM:branches")
 204         .desc("Number of branches committed")
 205         .flags(total)
 206         ;
 207
 208     commitEligible
 209         .init(cpu->number_of_threads)
 210         .name(name() + ".COM:bw_limited")
 211         .desc("number of insts not committed due to BW limits")
 212         .flags(total)
 213         ;
 214
 215     commitEligibleSamples
 216         .name(name() + ".COM:bw_lim_events")
 217         .desc("number cycles where commit BW limit reached")
 218         ;
 219 }
 220
 221 template <class Impl>
 222 void
 223 DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
 224 {
 225     DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
 226     cpu = cpu_ptr;
 227
 228     // Commit must broadcast the number of free entries it has at the start of
 229     // the simulation, so it starts as active.
 230     cpu->activateStage(O3CPU::CommitIdx);
 231
 232     trapLatency = cpu->cycles(trapLatency);
 233 }
 234
 235 template <class Impl>
 236 void
 237 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 238 {
 239     thread = threads;
 240 }
 241
 242 template <class Impl>
 243 void
 244 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 245 {
 246     DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
 247     timeBuffer = tb_ptr;
 248
 249     // Setup wire to send information back to IEW.
 250     toIEW = timeBuffer->getWire(0);
 251
 252     // Setup wire to read data from IEW (for the ROB).
 253     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 254 }
 255
 256 template <class Impl>
 257 void
 258 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 259 {
 260     DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
 261     fetchQueue = fq_ptr;
 262
 263     // Setup wire to get instructions from rename (for the ROB).
 264     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 265 }
 266
 267 template <class Impl>
 268 void
 269 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 270 {
 271     DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
 272     renameQueue = rq_ptr;
 273
 274     // Setup wire to get instructions from rename (for the ROB).
 275     fromRename = renameQueue->getWire(-renameToROBDelay);
 276 }
 277
 278 template <class Impl>
 279 void
 280 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 281 {
 282     DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
 283     iewQueue = iq_ptr;
 284
 285     // Setup wire to get instructions from IEW.
 286     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 287 }
 288
 289 template <class Impl>
 290 void
 291 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 292 {
 293     iewStage = iew_stage;
 294 }
 295
 296 template<class Impl>
 297 void
 298 DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 299 {
 300     DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
 301     activeThreads = at_ptr;
 302 }
 303
 304 template <class Impl>
 305 void
 306 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 307 {
 308     DPRINTF(Commit, "Setting rename map pointers.\n");
 309
 310     for (int i=0; i < numThreads; i++) {
 311         renameMap[i] = &rm_ptr[i];
 312     }
 313 }
 314
 315 template <class Impl>
 316 void
 317 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 318 {
 319     DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
 320     rob = rob_ptr;
 321 }
 322
 323 template <class Impl>
 324 void
 325 DefaultCommit<Impl>::initStage()
 326 {
 327     rob->setActiveThreads(activeThreads);
 328     rob->resetEntries();
 329
 330     // Broadcast the number of free entries.
 331     for (int i=0; i < numThreads; i++) {
 332         toIEW->commitInfo[i].usedROB = true;
 333         toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
 334     }
 335
 336     cpu->activityThisCycle();
 337 }
 338
 339 template <class Impl>
 340 bool
 341 DefaultCommit<Impl>::drain()
 342 {
 343     drainPending = true;
 344
 345     // If it's already drained, return true.
 346     if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 347         cpu->signalDrained();
 348         return true;
 349     }
 350
 351     return false;
 352 }
 353
 354 template <class Impl>
 355 void
 356 DefaultCommit<Impl>::switchOut()
 357 {
 358     switchedOut = true;
 359     drainPending = false;
 360     rob->switchOut();
 361 }
 362
 363 template <class Impl>
 364 void
 365 DefaultCommit<Impl>::resume()
 366 {
 367     drainPending = false;
 368 }
 369
 370 template <class Impl>
 371 void
 372 DefaultCommit<Impl>::takeOverFrom()
 373 {
 374     switchedOut = false;
 375     _status = Active;
 376     _nextStatus = Inactive;
 377     for (int i=0; i < numThreads; i++) {
 378         commitStatus[i] = Idle;
 379         changedROBNumEntries[i] = false;
 380         trapSquash[i] = false;
 381         tcSquash[i] = false;
 382     }
 383     squashCounter = 0;
 384     rob->takeOverFrom();
 385 }
 386
 387 template <class Impl>
 388 void
 389 DefaultCommit<Impl>::updateStatus()
 390 {
 391     // reset ROB changed variable
 392     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 393     while (threads != (*activeThreads).end()) {
 394         unsigned tid = *threads++;
 395         changedROBNumEntries[tid] = false;
 396
 397         // Also check if any of the threads has a trap pending
 398         if (commitStatus[tid] == TrapPending ||
 399             commitStatus[tid] == FetchTrapPending) {
 400             _nextStatus = Active;
 401         }
 402     }
 403
 404     if (_nextStatus == Inactive && _status == Active) {
 405         DPRINTF(Activity, "Deactivating stage.\n");
 406         cpu->deactivateStage(O3CPU::CommitIdx);
 407     } else if (_nextStatus == Active && _status == Inactive) {
 408         DPRINTF(Activity, "Activating stage.\n");
 409         cpu->activateStage(O3CPU::CommitIdx);
 410     }
 411
 412     _status = _nextStatus;
 413 }
 414
 415 template <class Impl>
 416 void
 417 DefaultCommit<Impl>::setNextStatus()
 418 {
 419     int squashes = 0;
 420
 421     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 422
 423     while (threads != (*activeThreads).end()) {
 424         unsigned tid = *threads++;
 425
 426         if (commitStatus[tid] == ROBSquashing) {
 427             squashes++;
 428         }
 429     }
 430
 431     squashCounter = squashes;
 432
 433     // If commit is currently squashing, then it will have activity for the
 434     // next cycle. Set its next status as active.
 435     if (squashCounter) {
 436         _nextStatus = Active;
 437     }
 438 }
 439
 440 template <class Impl>
 441 bool
 442 DefaultCommit<Impl>::changedROBEntries()
 443 {
 444     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 445
 446     while (threads != (*activeThreads).end()) {
 447         unsigned tid = *threads++;
 448
 449         if (changedROBNumEntries[tid]) {
 450             return true;
 451         }
 452     }
 453
 454     return false;
 455 }
 456
 457 template <class Impl>
 458 unsigned
 459 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
 460 {
 461     return rob->numFreeEntries(tid);
 462 }
 463
 464 template <class Impl>
 465 void
 466 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
 467 {
 468     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 469
 470     TrapEvent *trap = new TrapEvent(this, tid);
 471
 472     trap->schedule(curTick + trapLatency);
 473
 474     thread[tid]->trapPending = true;
 475 }
 476
 477 template <class Impl>
 478 void
 479 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
 480 {
 481     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 482
 483     tcSquash[tid] = true;
 484 }
 485
 486 template <class Impl>
 487 void
 488 DefaultCommit<Impl>::squashAll(unsigned tid)
 489 {
 490     // If we want to include the squashing instruction in the squash,
 491     // then use one older sequence number.
 492     // Hopefully this doesn't mess things up.  Basically I want to squash
 493     // all instructions of this thread.
 494     InstSeqNum squashed_inst = rob->isEmpty() ?
 495         0 : rob->readHeadInst(tid)->seqNum - 1;;
 496
 497     // All younger instructions will be squashed. Set the sequence
 498     // number as the youngest instruction in the ROB (0 in this case.
 499     // Hopefully nothing breaks.)
 500     youngestSeqNum[tid] = 0;
 501
 502     rob->squash(squashed_inst, tid);
 503     changedROBNumEntries[tid] = true;
 504
 505     // Send back the sequence number of the squashed instruction.
 506     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 507
 508     // Send back the squash signal to tell stages that they should
 509     // squash.
 510     toIEW->commitInfo[tid].squash = true;
 511
 512     // Send back the rob squashing signal so other stages know that
 513     // the ROB is in the process of squashing.
 514     toIEW->commitInfo[tid].robSquashing = true;
 515
 516     toIEW->commitInfo[tid].branchMispredict = false;
 517
 518     toIEW->commitInfo[tid].nextPC = PC[tid];
 519 }
 520
 521 template <class Impl>
 522 void
 523 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
 524 {
 525     squashAll(tid);
 526
 527     DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
 528
 529     thread[tid]->trapPending = false;
 530     thread[tid]->inSyscall = false;
 531
 532     trapSquash[tid] = false;
 533
 534     commitStatus[tid] = ROBSquashing;
 535     cpu->activityThisCycle();
 536 }
 537
 538 template <class Impl>
 539 void
 540 DefaultCommit<Impl>::squashFromTC(unsigned tid)
 541 {
 542     squashAll(tid);
 543
 544     DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
 545
 546     thread[tid]->inSyscall = false;
 547     assert(!thread[tid]->trapPending);
 548
 549     commitStatus[tid] = ROBSquashing;
 550     cpu->activityThisCycle();
 551
 552     tcSquash[tid] = false;
 553 }
 554
 555 template <class Impl>
 556 void
 557 DefaultCommit<Impl>::tick()
 558 {
 559     wroteToTimeBuffer = false;
 560     _nextStatus = Inactive;
 561
 562     if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 563         cpu->signalDrained();
 564         drainPending = false;
 565         return;
 566     }
 567
 568     if ((*activeThreads).size() <= 0)
 569         return;
 570
 571     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 572
 573     // Check if any of the threads are done squashing.  Change the
 574     // status if they are done.
 575     while (threads != (*activeThreads).end()) {
 576         unsigned tid = *threads++;
 577
 578         if (commitStatus[tid] == ROBSquashing) {
 579
 580             if (rob->isDoneSquashing(tid)) {
 581                 commitStatus[tid] = Running;
 582             } else {
 583                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 584                         " insts this cycle.\n", tid);
 585                 rob->doSquash(tid);
 586                 toIEW->commitInfo[tid].robSquashing = true;
 587                 wroteToTimeBuffer = true;
 588             }
 589         }
 590     }
 591
 592     commit();
 593
 594     markCompletedInsts();
 595
 596     threads = (*activeThreads).begin();
 597
 598     while (threads != (*activeThreads).end()) {
 599         unsigned tid = *threads++;
 600
 601         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 602             // The ROB has more instructions it can commit. Its next status
 603             // will be active.
 604             _nextStatus = Active;
 605
 606             DynInstPtr inst = rob->readHeadInst(tid);
 607
 608             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
 609                     " ROB and ready to commit\n",
 610                     tid, inst->seqNum, inst->readPC());
 611
 612         } else if (!rob->isEmpty(tid)) {
 613             DynInstPtr inst = rob->readHeadInst(tid);
 614
 615             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 616                     "%#x is head of ROB and not ready\n",
 617                     tid, inst->seqNum, inst->readPC());
 618         }
 619
 620         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 621                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 622     }
 623
 624
 625     if (wroteToTimeBuffer) {
 626         DPRINTF(Activity, "Activity This Cycle.\n");
 627         cpu->activityThisCycle();
 628     }
 629
 630     updateStatus();
 631 }
 632
 633 template <class Impl>
 634 void
 635 DefaultCommit<Impl>::commit()
 636 {
 637
 638     //////////////////////////////////////
 639     // Check for interrupts
 640     //////////////////////////////////////
 641
 642 #if FULL_SYSTEM
 643     // Process interrupts if interrupts are enabled, not in PAL mode,
 644     // and no other traps or external squashes are currently pending.
 645     // @todo: Allow other threads to handle interrupts.
 646     if (cpu->checkInterrupts &&
 647         cpu->check_interrupts() &&
 648         !cpu->inPalMode(readPC()) &&
 649         !trapSquash[0] &&
 650         !tcSquash[0]) {
 651         // Tell fetch that there is an interrupt pending.  This will
 652         // make fetch wait until it sees a non PAL-mode PC, at which
 653         // point it stops fetching instructions.
 654         toIEW->commitInfo[0].interruptPending = true;
 655
 656         // Wait until the ROB is empty and all stores have drained in
 657         // order to enter the interrupt.
 658         if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 659             // Not sure which thread should be the one to interrupt.  For now
 660             // always do thread 0.
 661             assert(!thread[0]->inSyscall);
 662             thread[0]->inSyscall = true;
 663
 664             // CPU will handle implementation of the interrupt.
 665             cpu->processInterrupts();
 666
 667             // Now squash or record that I need to squash this cycle.
 668             commitStatus[0] = TrapPending;
 669
 670             // Exit state update mode to avoid accidental updating.
 671             thread[0]->inSyscall = false;
 672
 673             // Generate trap squash event.
 674             generateTrapEvent(0);
 675
 676             toIEW->commitInfo[0].clearInterrupt = true;
 677
 678             DPRINTF(Commit, "Interrupt detected.\n");
 679         } else {
 680             DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 681         }
 682     }
 683 #endif // FULL_SYSTEM
 684
 685     ////////////////////////////////////
 686     // Check for any possible squashes, handle them first
 687     ////////////////////////////////////
 688
 689     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 690
 691     while (threads != (*activeThreads).end()) {
 692         unsigned tid = *threads++;
 693
 694         // Not sure which one takes priority.  I think if we have
 695         // both, that's a bad sign.
 696         if (trapSquash[tid] == true) {
 697             assert(!tcSquash[tid]);
 698             squashFromTrap(tid);
 699         } else if (tcSquash[tid] == true) {
 700             squashFromTC(tid);
 701         }
 702
 703         // Squashed sequence number must be older than youngest valid
 704         // instruction in the ROB. This prevents squashes from younger
 705         // instructions overriding squashes from older instructions.
 706         if (fromIEW->squash[tid] &&
 707             commitStatus[tid] != TrapPending &&
 708             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 709
 710             DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
 711                     tid,
 712                     fromIEW->mispredPC[tid],
 713                     fromIEW->squashedSeqNum[tid]);
 714
 715             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 716                     tid,
 717                     fromIEW->nextPC[tid]);
 718
 719             commitStatus[tid] = ROBSquashing;
 720
 721             // If we want to include the squashing instruction in the squash,
 722             // then use one older sequence number.
 723             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 724
 725 #if ISA_HAS_DELAY_SLOT
 726             InstSeqNum bdelay_done_seq_num;
 727             bool squash_bdelay_slot;
 728
 729             if (fromIEW->branchMispredict[tid]) {
 730                 if (fromIEW->branchTaken[tid] &&
 731                     fromIEW->condDelaySlotBranch[tid]) {
 732                     DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
 733                             "mispredicted as taken. Squashing after previous "
 734                             "inst, [sn:%i]\n",
 735                             tid, squashed_inst);
 736                      bdelay_done_seq_num = squashed_inst;
 737                      squash_bdelay_slot = true;
 738                 } else {
 739                     DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
 740                             "after delay slot [sn:%i]\n", tid, squashed_inst+1);
 741                     bdelay_done_seq_num = squashed_inst + 1;
 742                     squash_bdelay_slot = false;
 743                 }
 744             } else {
 745                 bdelay_done_seq_num = squashed_inst;
 746             }
 747 #endif
 748
 749             if (fromIEW->includeSquashInst[tid] == true) {
 750                 squashed_inst--;
 751 #if ISA_HAS_DELAY_SLOT
 752                 bdelay_done_seq_num--;
 753 #endif
 754             }
 755             // All younger instructions will be squashed. Set the sequence
 756             // number as the youngest instruction in the ROB.
 757             youngestSeqNum[tid] = squashed_inst;
 758
 759 #if ISA_HAS_DELAY_SLOT
 760             rob->squash(bdelay_done_seq_num, tid);
 761             toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
 762             toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
 763 #else
 764             rob->squash(squashed_inst, tid);
 765             toIEW->commitInfo[tid].squashDelaySlot = true;
 766 #endif
 767             changedROBNumEntries[tid] = true;
 768
 769             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 770
 771             toIEW->commitInfo[tid].squash = true;
 772
 773             // Send back the rob squashing signal so other stages know that
 774             // the ROB is in the process of squashing.
 775             toIEW->commitInfo[tid].robSquashing = true;
 776
 777             toIEW->commitInfo[tid].branchMispredict =
 778                 fromIEW->branchMispredict[tid];
 779
 780             toIEW->commitInfo[tid].branchTaken =
 781                 fromIEW->branchTaken[tid];
 782
 783             toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
 784
 785             toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
 786
 787             if (toIEW->commitInfo[tid].branchMispredict) {
 788                 ++branchMispredicts;
 789             }
 790         }
 791
 792     }
 793
 794     setNextStatus();
 795
 796     if (squashCounter != numThreads) {
 797         // If we're not currently squashing, then get instructions.
 798         getInsts();
 799
 800         // Try to commit any instructions.
 801         commitInsts();
 802     } else {
 803 #if ISA_HAS_DELAY_SLOT
 804         skidInsert();
 805 #endif
 806     }
 807
 808     //Check for any activity
 809     threads = (*activeThreads).begin();
 810
 811     while (threads != (*activeThreads).end()) {
 812         unsigned tid = *threads++;
 813
 814         if (changedROBNumEntries[tid]) {
 815             toIEW->commitInfo[tid].usedROB = true;
 816             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 817
 818             if (rob->isEmpty(tid)) {
 819                 toIEW->commitInfo[tid].emptyROB = true;
 820             }
 821
 822             wroteToTimeBuffer = true;
 823             changedROBNumEntries[tid] = false;
 824         }
 825     }
 826 }
 827
 828 template <class Impl>
 829 void
 830 DefaultCommit<Impl>::commitInsts()
 831 {
 832     ////////////////////////////////////
 833     // Handle commit
 834     // Note that commit will be handled prior to putting new
 835     // instructions in the ROB so that the ROB only tries to commit
 836     // instructions it has in this current cycle, and not instructions
 837     // it is writing in during this cycle.  Can't commit and squash
 838     // things at the same time...
 839     ////////////////////////////////////
 840
 841     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 842
 843     unsigned num_committed = 0;
 844
 845     DynInstPtr head_inst;
 846
 847     // Commit as many instructions as possible until the commit bandwidth
 848     // limit is reached, or it becomes impossible to commit any more.
 849     while (num_committed < commitWidth) {
 850         int commit_thread = getCommittingThread();
 851
 852         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 853             break;
 854
 855         head_inst = rob->readHeadInst(commit_thread);
 856
 857         int tid = head_inst->threadNumber;
 858
 859         assert(tid == commit_thread);
 860
 861         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 862                 head_inst->seqNum, tid);
 863
 864         // If the head instruction is squashed, it is ready to retire
 865         // (be removed from the ROB) at any time.
 866         if (head_inst->isSquashed()) {
 867
 868             DPRINTF(Commit, "Retiring squashed instruction from "
 869                     "ROB.\n");
 870
 871             rob->retireHead(commit_thread);
 872
 873             ++commitSquashedInsts;
 874
 875             // Record that the number of ROB entries has changed.
 876             changedROBNumEntries[tid] = true;
 877         } else {
 878             PC[tid] = head_inst->readPC();
 879             nextPC[tid] = head_inst->readNextPC();
 880             nextNPC[tid] = head_inst->readNextNPC();
 881
 882             // Increment the total number of non-speculative instructions
 883             // executed.
 884             // Hack for now: it really shouldn't happen until after the
 885             // commit is deemed to be successful, but this count is needed
 886             // for syscalls.
 887             thread[tid]->funcExeInst++;
 888
 889             // Try to commit the head instruction.
 890             bool commit_success = commitHead(head_inst, num_committed);
 891
 892             if (commit_success) {
 893                 ++num_committed;
 894
 895                 changedROBNumEntries[tid] = true;
 896
 897                 // Set the doneSeqNum to the youngest committed instruction.
 898                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 899
 900                 ++commitCommittedInsts;
 901
 902                 // To match the old model, don't count nops and instruction
 903                 // prefetches towards the total commit count.
 904                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 905                     cpu->instDone(tid);
 906                 }
 907
 908                 PC[tid] = nextPC[tid];
 909 #if ISA_HAS_DELAY_SLOT
 910                 nextPC[tid] = nextNPC[tid];
 911                 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
 912 #else
 913                 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
 914 #endif
 915
 916 #if FULL_SYSTEM
 917                 int count = 0;
 918                 Addr oldpc;
 919                 do {
 920                     // Debug statement.  Checks to make sure we're not
 921                     // currently updating state while handling PC events.
 922                     if (count == 0)
 923                         assert(!thread[tid]->inSyscall &&
 924                                !thread[tid]->trapPending);
 925                     oldpc = PC[tid];
 926                     cpu->system->pcEventQueue.service(
 927                         thread[tid]->getTC());
 928                     count++;
 929                 } while (oldpc != PC[tid]);
 930                 if (count > 1) {
 931                     DPRINTF(Commit, "PC skip function event, stopping commit\n");
 932                     break;
 933                 }
 934 #endif
 935             } else {
 936                 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
 937                         "[tid:%i] [sn:%i].\n",
 938                         head_inst->readPC(), tid ,head_inst->seqNum);
 939                 break;
 940             }
 941         }
 942     }
 943
 944     DPRINTF(CommitRate, "%i\n", num_committed);
 945     numCommittedDist.sample(num_committed);
 946
 947     if (num_committed == commitWidth) {
 948         commitEligibleSamples++;
 949     }
 950 }
 951
 952 template <class Impl>
 953 bool
 954 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 955 {
 956     assert(head_inst);
 957
 958     int tid = head_inst->threadNumber;
 959
 960     // If the instruction is not executed yet, then it will need extra
 961     // handling.  Signal backwards that it should be executed.
 962     if (!head_inst->isExecuted()) {
 963         // Keep this number correct.  We have not yet actually executed
 964         // and committed this instruction.
 965         thread[tid]->funcExeInst--;
 966
 967         head_inst->setAtCommit();
 968
 969         if (head_inst->isNonSpeculative() ||
 970             head_inst->isStoreConditional() ||
 971             head_inst->isMemBarrier() ||
 972             head_inst->isWriteBarrier()) {
 973
 974             DPRINTF(Commit, "Encountered a barrier or non-speculative "
 975                     "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
 976                     head_inst->seqNum, head_inst->readPC());
 977
 978 #if !FULL_SYSTEM
 979             // Hack to make sure syscalls/memory barriers/quiesces
 980             // aren't executed until all stores write back their data.
 981             // This direct communication shouldn't be used for
 982             // anything other than this.
 983             if (inst_num > 0 || iewStage->hasStoresToWB())
 984 #else
 985             if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
 986                     head_inst->isQuiesce()) &&
 987                 iewStage->hasStoresToWB())
 988 #endif
 989             {
 990                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
 991                 return false;
 992             }
 993
 994             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
 995
 996             // Change the instruction so it won't try to commit again until
 997             // it is executed.
 998             head_inst->clearCanCommit();
 999
1000             ++commitNonSpecStalls;
1001
1002             return false;
1003         } else if (head_inst->isLoad()) {
1004             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1005                     head_inst->seqNum, head_inst->readPC());
1006
1007             // Send back the non-speculative instruction's sequence
1008             // number.  Tell the lsq to re-execute the load.
1009             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1010             toIEW->commitInfo[tid].uncached = true;
1011             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1012
1013             head_inst->clearCanCommit();
1014
1015             return false;
1016         } else {
1017             panic("Trying to commit un-executed instruction "
1018                   "of unknown type!\n");
1019         }
1020     }
1021
1022     if (head_inst->isThreadSync()) {
1023         // Not handled for now.
1024         panic("Thread sync instructions are not handled yet.\n");
1025     }
1026
1027     // Stores mark themselves as completed.
1028     if (!head_inst->isStore()) {
1029         head_inst->setCompleted();
1030     }
1031
1032 #if USE_CHECKER
1033     // Use checker prior to updating anything due to traps or PC
1034     // based events.
1035     if (cpu->checker) {
1036         cpu->checker->verify(head_inst);
1037     }
1038 #endif
1039
1040     // Check if the instruction caused a fault.  If so, trap.
1041     Fault inst_fault = head_inst->getFault();
1042
1043     // DTB will sometimes need the machine instruction for when
1044     // faults happen.  So we will set it here, prior to the DTB
1045     // possibly needing it for its fault.
1046     thread[tid]->setInst(
1047         static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1048
1049     if (inst_fault != NoFault) {
1050         head_inst->setCompleted();
1051         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1052                 head_inst->seqNum, head_inst->readPC());
1053
1054         if (iewStage->hasStoresToWB() || inst_num > 0) {
1055             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1056             return false;
1057         }
1058
1059 #if USE_CHECKER
1060         if (cpu->checker && head_inst->isStore()) {
1061             cpu->checker->verify(head_inst);
1062         }
1063 #endif
1064
1065         assert(!thread[tid]->inSyscall);
1066
1067         // Mark that we're in state update mode so that the trap's
1068         // execution doesn't generate extra squashes.
1069         thread[tid]->inSyscall = true;
1070
1071         // Execute the trap.  Although it's slightly unrealistic in
1072         // terms of timing (as it doesn't wait for the full timing of
1073         // the trap event to complete before updating state), it's
1074         // needed to update the state as soon as possible.  This
1075         // prevents external agents from changing any specific state
1076         // that the trap need.
1077         cpu->trap(inst_fault, tid);
1078
1079         // Exit state update mode to avoid accidental updating.
1080         thread[tid]->inSyscall = false;
1081
1082         commitStatus[tid] = TrapPending;
1083
1084         // Generate trap squash event.
1085         generateTrapEvent(tid);
1086
1087         return false;
1088     }
1089
1090     updateComInstStats(head_inst);
1091
1092     if (head_inst->traceData) {
1093         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1094         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1095         head_inst->traceData->finalize();
1096         head_inst->traceData = NULL;
1097     }
1098
1099     // Update the commit rename map
1100     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1101         renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1102                                  head_inst->renamedDestRegIdx(i));
1103     }
1104
1105     // Finally clear the head ROB entry.
1106     rob->retireHead(tid);
1107
1108     // Return true to indicate that we have committed an instruction.
1109     return true;
1110 }
1111
1112 template <class Impl>
1113 void
1114 DefaultCommit<Impl>::getInsts()
1115 {
1116     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1117
1118 #if ISA_HAS_DELAY_SLOT
1119     // Read any renamed instructions and place them into the ROB.
1120     int insts_to_process = std::min((int)renameWidth,
1121                                (int)(fromRename->size + skidBuffer.size()));
1122     int rename_idx = 0;
1123
1124     DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1125             "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1126             skidBuffer.size());
1127 #else
1128     // Read any renamed instructions and place them into the ROB.
1129     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1130 #endif
1131
1132
1133     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1134         DynInstPtr inst;
1135
1136 #if ISA_HAS_DELAY_SLOT
1137         // Get insts from skidBuffer or from Rename
1138         if (skidBuffer.size() > 0) {
1139             DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1140             inst = skidBuffer.front();
1141             skidBuffer.pop();
1142         } else {
1143             DPRINTF(Commit, "Grabbing rename inst.\n");
1144             inst = fromRename->insts[rename_idx++];
1145         }
1146 #else
1147         inst = fromRename->insts[inst_num];
1148 #endif
1149         int tid = inst->threadNumber;
1150
1151         if (!inst->isSquashed() &&
1152             commitStatus[tid] != ROBSquashing) {
1153             changedROBNumEntries[tid] = true;
1154
1155             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1156                     inst->readPC(), inst->seqNum, tid);
1157
1158             rob->insertInst(inst);
1159
1160             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1161
1162             youngestSeqNum[tid] = inst->seqNum;
1163         } else {
1164             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1165                     "squashed, skipping.\n",
1166                     inst->readPC(), inst->seqNum, tid);
1167         }
1168     }
1169
1170 #if ISA_HAS_DELAY_SLOT
1171     if (rename_idx < fromRename->size) {
1172         DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1173
1174         for (;
1175              rename_idx < fromRename->size;
1176              rename_idx++) {
1177             DynInstPtr inst = fromRename->insts[rename_idx];
1178             int tid = inst->threadNumber;
1179
1180             if (!inst->isSquashed()) {
1181                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1182                         "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1183                 skidBuffer.push(inst);
1184             } else {
1185                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1186                         "squashed, skipping.\n",
1187                         inst->readPC(), inst->seqNum, tid);
1188             }
1189         }
1190     }
1191 #endif
1192
1193 }
1194
1195 template <class Impl>
1196 void
1197 DefaultCommit<Impl>::skidInsert()
1198 {
1199     DPRINTF(Commit, "Attempting to any instructions from rename into "
1200             "skidBuffer.\n");
1201
1202     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1203         DynInstPtr inst = fromRename->insts[inst_num];
1204         int tid = inst->threadNumber;
1205
1206         if (!inst->isSquashed()) {
1207             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1208                     "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1209             skidBuffer.push(inst);
1210         } else {
1211             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1212                     "squashed, skipping.\n",
1213                     inst->readPC(), inst->seqNum, tid);
1214         }
1215     }
1216 }
1217
1218 template <class Impl>
1219 void
1220 DefaultCommit<Impl>::markCompletedInsts()
1221 {
1222     // Grab completed insts out of the IEW instruction queue, and mark
1223     // instructions completed within the ROB.
1224     for (int inst_num = 0;
1225          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1226          ++inst_num)
1227     {
1228         if (!fromIEW->insts[inst_num]->isSquashed()) {
1229             DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1230                     "within ROB.\n",
1231                     fromIEW->insts[inst_num]->threadNumber,
1232                     fromIEW->insts[inst_num]->readPC(),
1233                     fromIEW->insts[inst_num]->seqNum);
1234
1235             // Mark the instruction as ready to commit.
1236             fromIEW->insts[inst_num]->setCanCommit();
1237         }
1238     }
1239 }
1240
1241 template <class Impl>
1242 bool
1243 DefaultCommit<Impl>::robDoneSquashing()
1244 {
1245     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1246
1247     while (threads != (*activeThreads).end()) {
1248         unsigned tid = *threads++;
1249
1250         if (!rob->isDoneSquashing(tid))
1251             return false;
1252     }
1253
1254     return true;
1255 }
1256
1257 template <class Impl>
1258 void
1259 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1260 {
1261     unsigned thread = inst->threadNumber;
1262
1263     //
1264     //  Pick off the software prefetches
1265     //
1266 #ifdef TARGET_ALPHA
1267     if (inst->isDataPrefetch()) {
1268         statComSwp[thread]++;
1269     } else {
1270         statComInst[thread]++;
1271     }
1272 #else
1273     statComInst[thread]++;
1274 #endif
1275
1276     //
1277     //  Control Instructions
1278     //
1279     if (inst->isControl())
1280         statComBranches[thread]++;
1281
1282     //
1283     //  Memory references
1284     //
1285     if (inst->isMemRef()) {
1286         statComRefs[thread]++;
1287
1288         if (inst->isLoad()) {
1289             statComLoads[thread]++;
1290         }
1291     }
1292
1293     if (inst->isMemBarrier()) {
1294         statComMembars[thread]++;
1295     }
1296 }
1297
1298 ////////////////////////////////////////
1299 //                                    //
1300 //  SMT COMMIT POLICY MAINTAINED HERE //
1301 //                                    //
1302 ////////////////////////////////////////
1303 template <class Impl>
1304 int
1305 DefaultCommit<Impl>::getCommittingThread()
1306 {
1307     if (numThreads > 1) {
1308         switch (commitPolicy) {
1309
1310           case Aggressive:
1311             //If Policy is Aggressive, commit will call
1312             //this function multiple times per
1313             //cycle
1314             return oldestReady();
1315
1316           case RoundRobin:
1317             return roundRobin();
1318
1319           case OldestReady:
1320             return oldestReady();
1321
1322           default:
1323             return -1;
1324         }
1325     } else {
1326         int tid = (*activeThreads).front();
1327
1328         if (commitStatus[tid] == Running ||
1329             commitStatus[tid] == Idle ||
1330             commitStatus[tid] == FetchTrapPending) {
1331             return tid;
1332         } else {
1333             return -1;
1334         }
1335     }
1336 }
1337
1338 template<class Impl>
1339 int
1340 DefaultCommit<Impl>::roundRobin()
1341 {
1342     std::list<unsigned>::iterator pri_iter = priority_list.begin();
1343     std::list<unsigned>::iterator end      = priority_list.end();
1344
1345     while (pri_iter != end) {
1346         unsigned tid = *pri_iter;
1347
1348         if (commitStatus[tid] == Running ||
1349             commitStatus[tid] == Idle ||
1350             commitStatus[tid] == FetchTrapPending) {
1351
1352             if (rob->isHeadReady(tid)) {
1353                 priority_list.erase(pri_iter);
1354                 priority_list.push_back(tid);
1355
1356                 return tid;
1357             }
1358         }
1359
1360         pri_iter++;
1361     }
1362
1363     return -1;
1364 }
1365
1366 template<class Impl>
1367 int
1368 DefaultCommit<Impl>::oldestReady()
1369 {
1370     unsigned oldest = 0;
1371     bool first = true;
1372
1373     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1374
1375     while (threads != (*activeThreads).end()) {
1376         unsigned tid = *threads++;
1377
1378         if (!rob->isEmpty(tid) &&
1379             (commitStatus[tid] == Running ||
1380              commitStatus[tid] == Idle ||
1381              commitStatus[tid] == FetchTrapPending)) {
1382
1383             if (rob->isHeadReady(tid)) {
1384
1385                 DynInstPtr head_inst = rob->readHeadInst(tid);
1386
1387                 if (first) {
1388                     oldest = tid;
1389                     first = false;
1390                 } else if (head_inst->seqNum < oldest) {
1391                     oldest = tid;
1392                 }
1393             }
1394         }
1395     }
1396
1397     if (!first) {
1398         return oldest;
1399     } else {
1400         return -1;
1401     }
1402 }