2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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31 #include "config/full_system.hh"
32 #include "config/use_checker.hh"
37 #include "base/loader/symtab.hh"
38 #include "base/timebuf.hh"
39 #include "cpu/exetrace.hh"
40 #include "cpu/o3/commit.hh"
41 #include "cpu/o3/thread_state.hh"
44 #include "cpu/checker/cpu.hh"
50 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
54 this->setFlags(Event::AutoDelete);
59 DefaultCommit<Impl>::TrapEvent::process()
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
68 DefaultCommit<Impl>::TrapEvent::description()
74 DefaultCommit<Impl>::DefaultCommit(Params *params)
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
85 trapLatency(params->trapLatency)
88 _nextStatus = Inactive;
89 string policy = params->smtCommitPolicy;
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
123 PC[i] = nextPC[i] = 0;
127 template <class Impl>
129 DefaultCommit<Impl>::name() const
131 return cpu->name() + ".commit";
134 template <class Impl>
136 DefaultCommit<Impl>::regStats()
138 using namespace Stats;
140 .name(name() + ".commitCommittedInsts")
141 .desc("The number of committed instructions")
142 .prereq(commitCommittedInsts);
144 .name(name() + ".commitSquashedInsts")
145 .desc("The number of squashed insts skipped by commit")
146 .prereq(commitSquashedInsts);
148 .name(name() + ".commitSquashEvents")
149 .desc("The number of times commit is told to squash")
150 .prereq(commitSquashEvents);
152 .name(name() + ".commitNonSpecStalls")
153 .desc("The number of times commit has been forced to stall to "
154 "communicate backwards")
155 .prereq(commitNonSpecStalls);
157 .name(name() + ".branchMispredicts")
158 .desc("The number of times a branch was mispredicted")
159 .prereq(branchMispredicts);
161 .init(0,commitWidth,1)
162 .name(name() + ".COM:committed_per_cycle")
163 .desc("Number of insts commited each cycle")
168 .init(cpu->number_of_threads)
169 .name(name() + ".COM:count")
170 .desc("Number of instructions committed")
175 .init(cpu->number_of_threads)
176 .name(name() + ".COM:swp_count")
177 .desc("Number of s/w prefetches committed")
182 .init(cpu->number_of_threads)
183 .name(name() + ".COM:refs")
184 .desc("Number of memory references committed")
189 .init(cpu->number_of_threads)
190 .name(name() + ".COM:loads")
191 .desc("Number of loads committed")
196 .init(cpu->number_of_threads)
197 .name(name() + ".COM:membars")
198 .desc("Number of memory barriers committed")
203 .init(cpu->number_of_threads)
204 .name(name() + ".COM:branches")
205 .desc("Number of branches committed")
210 .init(cpu->number_of_threads)
211 .name(name() + ".COM:bw_limited")
212 .desc("number of insts not committed due to BW limits")
216 commitEligibleSamples
217 .name(name() + ".COM:bw_lim_events")
218 .desc("number cycles where commit BW limit reached")
222 template <class Impl>
224 DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
226 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
229 // Commit must broadcast the number of free entries it has at the start of
230 // the simulation, so it starts as active.
231 cpu->activateStage(O3CPU::CommitIdx);
233 trapLatency = cpu->cycles(trapLatency);
236 template <class Impl>
238 DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
243 template <class Impl>
245 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
247 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
250 // Setup wire to send information back to IEW.
251 toIEW = timeBuffer->getWire(0);
253 // Setup wire to read data from IEW (for the ROB).
254 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
257 template <class Impl>
259 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
261 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
264 // Setup wire to get instructions from rename (for the ROB).
265 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
268 template <class Impl>
270 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
272 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
273 renameQueue = rq_ptr;
275 // Setup wire to get instructions from rename (for the ROB).
276 fromRename = renameQueue->getWire(-renameToROBDelay);
279 template <class Impl>
281 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
283 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
286 // Setup wire to get instructions from IEW.
287 fromIEW = iewQueue->getWire(-iewToCommitDelay);
290 template <class Impl>
292 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
294 iewStage = iew_stage;
299 DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
301 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
302 activeThreads = at_ptr;
305 template <class Impl>
307 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
309 DPRINTF(Commit, "Setting rename map pointers.\n");
311 for (int i=0; i < numThreads; i++) {
312 renameMap[i] = &rm_ptr[i];
316 template <class Impl>
318 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
320 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324 template <class Impl>
326 DefaultCommit<Impl>::initStage()
328 rob->setActiveThreads(activeThreads);
331 // Broadcast the number of free entries.
332 for (int i=0; i < numThreads; i++) {
333 toIEW->commitInfo[i].usedROB = true;
334 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
337 cpu->activityThisCycle();
340 template <class Impl>
342 DefaultCommit<Impl>::drain()
346 // If it's already drained, return true.
347 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
348 cpu->signalDrained();
355 template <class Impl>
357 DefaultCommit<Impl>::switchOut()
360 drainPending = false;
364 template <class Impl>
366 DefaultCommit<Impl>::resume()
368 drainPending = false;
371 template <class Impl>
373 DefaultCommit<Impl>::takeOverFrom()
377 _nextStatus = Inactive;
378 for (int i=0; i < numThreads; i++) {
379 commitStatus[i] = Idle;
380 changedROBNumEntries[i] = false;
381 trapSquash[i] = false;
388 template <class Impl>
390 DefaultCommit<Impl>::updateStatus()
392 // reset ROB changed variable
393 list<unsigned>::iterator threads = (*activeThreads).begin();
394 while (threads != (*activeThreads).end()) {
395 unsigned tid = *threads++;
396 changedROBNumEntries[tid] = false;
398 // Also check if any of the threads has a trap pending
399 if (commitStatus[tid] == TrapPending ||
400 commitStatus[tid] == FetchTrapPending) {
401 _nextStatus = Active;
405 if (_nextStatus == Inactive && _status == Active) {
406 DPRINTF(Activity, "Deactivating stage.\n");
407 cpu->deactivateStage(O3CPU::CommitIdx);
408 } else if (_nextStatus == Active && _status == Inactive) {
409 DPRINTF(Activity, "Activating stage.\n");
410 cpu->activateStage(O3CPU::CommitIdx);
413 _status = _nextStatus;
416 template <class Impl>
418 DefaultCommit<Impl>::setNextStatus()
422 list<unsigned>::iterator threads = (*activeThreads).begin();
424 while (threads != (*activeThreads).end()) {
425 unsigned tid = *threads++;
427 if (commitStatus[tid] == ROBSquashing) {
432 squashCounter = squashes;
434 // If commit is currently squashing, then it will have activity for the
435 // next cycle. Set its next status as active.
437 _nextStatus = Active;
441 template <class Impl>
443 DefaultCommit<Impl>::changedROBEntries()
445 list<unsigned>::iterator threads = (*activeThreads).begin();
447 while (threads != (*activeThreads).end()) {
448 unsigned tid = *threads++;
450 if (changedROBNumEntries[tid]) {
458 template <class Impl>
460 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
462 return rob->numFreeEntries(tid);
465 template <class Impl>
467 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
469 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
471 TrapEvent *trap = new TrapEvent(this, tid);
473 trap->schedule(curTick + trapLatency);
475 thread[tid]->trapPending = true;
478 template <class Impl>
480 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
482 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
484 tcSquash[tid] = true;
487 template <class Impl>
489 DefaultCommit<Impl>::squashAll(unsigned tid)
491 // If we want to include the squashing instruction in the squash,
492 // then use one older sequence number.
493 // Hopefully this doesn't mess things up. Basically I want to squash
494 // all instructions of this thread.
495 InstSeqNum squashed_inst = rob->isEmpty() ?
496 0 : rob->readHeadInst(tid)->seqNum - 1;;
498 // All younger instructions will be squashed. Set the sequence
499 // number as the youngest instruction in the ROB (0 in this case.
500 // Hopefully nothing breaks.)
501 youngestSeqNum[tid] = 0;
503 rob->squash(squashed_inst, tid);
504 changedROBNumEntries[tid] = true;
506 // Send back the sequence number of the squashed instruction.
507 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
509 // Send back the squash signal to tell stages that they should
511 toIEW->commitInfo[tid].squash = true;
513 // Send back the rob squashing signal so other stages know that
514 // the ROB is in the process of squashing.
515 toIEW->commitInfo[tid].robSquashing = true;
517 toIEW->commitInfo[tid].branchMispredict = false;
519 toIEW->commitInfo[tid].nextPC = PC[tid];
522 template <class Impl>
524 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
528 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
530 thread[tid]->trapPending = false;
531 thread[tid]->inSyscall = false;
533 trapSquash[tid] = false;
535 commitStatus[tid] = ROBSquashing;
536 cpu->activityThisCycle();
539 template <class Impl>
541 DefaultCommit<Impl>::squashFromTC(unsigned tid)
545 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
547 thread[tid]->inSyscall = false;
548 assert(!thread[tid]->trapPending);
550 commitStatus[tid] = ROBSquashing;
551 cpu->activityThisCycle();
553 tcSquash[tid] = false;
556 template <class Impl>
558 DefaultCommit<Impl>::tick()
560 wroteToTimeBuffer = false;
561 _nextStatus = Inactive;
563 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
564 cpu->signalDrained();
565 drainPending = false;
569 if ((*activeThreads).size() <= 0)
572 list<unsigned>::iterator threads = (*activeThreads).begin();
574 // Check if any of the threads are done squashing. Change the
575 // status if they are done.
576 while (threads != (*activeThreads).end()) {
577 unsigned tid = *threads++;
579 if (commitStatus[tid] == ROBSquashing) {
581 if (rob->isDoneSquashing(tid)) {
582 commitStatus[tid] = Running;
584 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
585 " insts this cycle.\n", tid);
587 toIEW->commitInfo[tid].robSquashing = true;
588 wroteToTimeBuffer = true;
595 markCompletedInsts();
597 threads = (*activeThreads).begin();
599 while (threads != (*activeThreads).end()) {
600 unsigned tid = *threads++;
602 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
603 // The ROB has more instructions it can commit. Its next status
605 _nextStatus = Active;
607 DynInstPtr inst = rob->readHeadInst(tid);
609 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
610 " ROB and ready to commit\n",
611 tid, inst->seqNum, inst->readPC());
613 } else if (!rob->isEmpty(tid)) {
614 DynInstPtr inst = rob->readHeadInst(tid);
616 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
617 "%#x is head of ROB and not ready\n",
618 tid, inst->seqNum, inst->readPC());
621 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
622 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
626 if (wroteToTimeBuffer) {
627 DPRINTF(Activity, "Activity This Cycle.\n");
628 cpu->activityThisCycle();
634 template <class Impl>
636 DefaultCommit<Impl>::commit()
639 //////////////////////////////////////
640 // Check for interrupts
641 //////////////////////////////////////
644 // Process interrupts if interrupts are enabled, not in PAL mode,
645 // and no other traps or external squashes are currently pending.
646 // @todo: Allow other threads to handle interrupts.
647 if (cpu->checkInterrupts &&
648 cpu->check_interrupts() &&
649 !cpu->inPalMode(readPC()) &&
652 // Tell fetch that there is an interrupt pending. This will
653 // make fetch wait until it sees a non PAL-mode PC, at which
654 // point it stops fetching instructions.
655 toIEW->commitInfo[0].interruptPending = true;
657 // Wait until the ROB is empty and all stores have drained in
658 // order to enter the interrupt.
659 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
660 // Not sure which thread should be the one to interrupt. For now
661 // always do thread 0.
662 assert(!thread[0]->inSyscall);
663 thread[0]->inSyscall = true;
665 // CPU will handle implementation of the interrupt.
666 cpu->processInterrupts();
668 // Now squash or record that I need to squash this cycle.
669 commitStatus[0] = TrapPending;
671 // Exit state update mode to avoid accidental updating.
672 thread[0]->inSyscall = false;
674 // Generate trap squash event.
675 generateTrapEvent(0);
677 toIEW->commitInfo[0].clearInterrupt = true;
679 DPRINTF(Commit, "Interrupt detected.\n");
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
684 #endif // FULL_SYSTEM
686 ////////////////////////////////////
687 // Check for any possible squashes, handle them first
688 ////////////////////////////////////
690 list<unsigned>::iterator threads = (*activeThreads).begin();
692 while (threads != (*activeThreads).end()) {
693 unsigned tid = *threads++;
695 // Not sure which one takes priority. I think if we have
696 // both, that's a bad sign.
697 if (trapSquash[tid] == true) {
698 assert(!tcSquash[tid]);
700 } else if (tcSquash[tid] == true) {
704 // Squashed sequence number must be older than youngest valid
705 // instruction in the ROB. This prevents squashes from younger
706 // instructions overriding squashes from older instructions.
707 if (fromIEW->squash[tid] &&
708 commitStatus[tid] != TrapPending &&
709 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
711 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
713 fromIEW->mispredPC[tid],
714 fromIEW->squashedSeqNum[tid]);
716 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
718 fromIEW->nextPC[tid]);
720 commitStatus[tid] = ROBSquashing;
722 // If we want to include the squashing instruction in the squash,
723 // then use one older sequence number.
724 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
726 if (fromIEW->includeSquashInst[tid] == true)
729 // All younger instructions will be squashed. Set the sequence
730 // number as the youngest instruction in the ROB.
731 youngestSeqNum[tid] = squashed_inst;
733 rob->squash(squashed_inst, tid);
734 changedROBNumEntries[tid] = true;
736 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
738 toIEW->commitInfo[tid].squash = true;
740 // Send back the rob squashing signal so other stages know that
741 // the ROB is in the process of squashing.
742 toIEW->commitInfo[tid].robSquashing = true;
744 toIEW->commitInfo[tid].branchMispredict =
745 fromIEW->branchMispredict[tid];
747 toIEW->commitInfo[tid].branchTaken =
748 fromIEW->branchTaken[tid];
750 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
752 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
754 if (toIEW->commitInfo[tid].branchMispredict) {
763 if (squashCounter != numThreads) {
764 // If we're not currently squashing, then get instructions.
767 // Try to commit any instructions.
771 //Check for any activity
772 threads = (*activeThreads).begin();
774 while (threads != (*activeThreads).end()) {
775 unsigned tid = *threads++;
777 if (changedROBNumEntries[tid]) {
778 toIEW->commitInfo[tid].usedROB = true;
779 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
781 if (rob->isEmpty(tid)) {
782 toIEW->commitInfo[tid].emptyROB = true;
785 wroteToTimeBuffer = true;
786 changedROBNumEntries[tid] = false;
791 template <class Impl>
793 DefaultCommit<Impl>::commitInsts()
795 ////////////////////////////////////
797 // Note that commit will be handled prior to putting new
798 // instructions in the ROB so that the ROB only tries to commit
799 // instructions it has in this current cycle, and not instructions
800 // it is writing in during this cycle. Can't commit and squash
801 // things at the same time...
802 ////////////////////////////////////
804 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
806 unsigned num_committed = 0;
808 DynInstPtr head_inst;
810 // Commit as many instructions as possible until the commit bandwidth
811 // limit is reached, or it becomes impossible to commit any more.
812 while (num_committed < commitWidth) {
813 int commit_thread = getCommittingThread();
815 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
818 head_inst = rob->readHeadInst(commit_thread);
820 int tid = head_inst->threadNumber;
822 assert(tid == commit_thread);
824 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
825 head_inst->seqNum, tid);
827 // If the head instruction is squashed, it is ready to retire
828 // (be removed from the ROB) at any time.
829 if (head_inst->isSquashed()) {
831 DPRINTF(Commit, "Retiring squashed instruction from "
834 rob->retireHead(commit_thread);
836 ++commitSquashedInsts;
838 // Record that the number of ROB entries has changed.
839 changedROBNumEntries[tid] = true;
841 PC[tid] = head_inst->readPC();
842 nextPC[tid] = head_inst->readNextPC();
844 // Increment the total number of non-speculative instructions
846 // Hack for now: it really shouldn't happen until after the
847 // commit is deemed to be successful, but this count is needed
849 thread[tid]->funcExeInst++;
851 // Try to commit the head instruction.
852 bool commit_success = commitHead(head_inst, num_committed);
854 if (commit_success) {
857 changedROBNumEntries[tid] = true;
859 // Set the doneSeqNum to the youngest committed instruction.
860 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
862 ++commitCommittedInsts;
864 // To match the old model, don't count nops and instruction
865 // prefetches towards the total commit count.
866 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
870 PC[tid] = nextPC[tid];
871 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
876 // Debug statement. Checks to make sure we're not
877 // currently updating state while handling PC events.
879 assert(!thread[tid]->inSyscall &&
880 !thread[tid]->trapPending);
882 cpu->system->pcEventQueue.service(
883 thread[tid]->getTC());
885 } while (oldpc != PC[tid]);
887 DPRINTF(Commit, "PC skip function event, stopping commit\n");
892 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
893 "[tid:%i] [sn:%i].\n",
894 head_inst->readPC(), tid ,head_inst->seqNum);
900 DPRINTF(CommitRate, "%i\n", num_committed);
901 numCommittedDist.sample(num_committed);
903 if (num_committed == commitWidth) {
904 commitEligibleSamples++;
908 template <class Impl>
910 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
914 int tid = head_inst->threadNumber;
916 // If the instruction is not executed yet, then it will need extra
917 // handling. Signal backwards that it should be executed.
918 if (!head_inst->isExecuted()) {
919 // Keep this number correct. We have not yet actually executed
920 // and committed this instruction.
921 thread[tid]->funcExeInst--;
923 head_inst->setAtCommit();
925 if (head_inst->isNonSpeculative() ||
926 head_inst->isStoreConditional() ||
927 head_inst->isMemBarrier() ||
928 head_inst->isWriteBarrier()) {
930 DPRINTF(Commit, "Encountered a barrier or non-speculative "
931 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
932 head_inst->seqNum, head_inst->readPC());
935 // Hack to make sure syscalls/memory barriers/quiesces
936 // aren't executed until all stores write back their data.
937 // This direct communication shouldn't be used for
938 // anything other than this.
939 if (inst_num > 0 || iewStage->hasStoresToWB())
941 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
942 head_inst->isQuiesce()) &&
943 iewStage->hasStoresToWB())
946 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
950 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
952 // Change the instruction so it won't try to commit again until
954 head_inst->clearCanCommit();
956 ++commitNonSpecStalls;
959 } else if (head_inst->isLoad()) {
960 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
961 head_inst->seqNum, head_inst->readPC());
963 // Send back the non-speculative instruction's sequence
964 // number. Tell the lsq to re-execute the load.
965 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
966 toIEW->commitInfo[tid].uncached = true;
967 toIEW->commitInfo[tid].uncachedLoad = head_inst;
969 head_inst->clearCanCommit();
973 panic("Trying to commit un-executed instruction "
974 "of unknown type!\n");
978 if (head_inst->isThreadSync()) {
979 // Not handled for now.
980 panic("Thread sync instructions are not handled yet.\n");
983 // Stores mark themselves as completed.
984 if (!head_inst->isStore()) {
985 head_inst->setCompleted();
989 // Use checker prior to updating anything due to traps or PC
992 cpu->checker->verify(head_inst);
996 // Check if the instruction caused a fault. If so, trap.
997 Fault inst_fault = head_inst->getFault();
999 if (inst_fault != NoFault) {
1000 head_inst->setCompleted();
1001 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1002 head_inst->seqNum, head_inst->readPC());
1004 if (iewStage->hasStoresToWB() || inst_num > 0) {
1005 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1010 if (cpu->checker && head_inst->isStore()) {
1011 cpu->checker->verify(head_inst);
1015 assert(!thread[tid]->inSyscall);
1017 // Mark that we're in state update mode so that the trap's
1018 // execution doesn't generate extra squashes.
1019 thread[tid]->inSyscall = true;
1021 // DTB will sometimes need the machine instruction for when
1022 // faults happen. So we will set it here, prior to the DTB
1023 // possibly needing it for its fault.
1024 thread[tid]->setInst(
1025 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1027 // Execute the trap. Although it's slightly unrealistic in
1028 // terms of timing (as it doesn't wait for the full timing of
1029 // the trap event to complete before updating state), it's
1030 // needed to update the state as soon as possible. This
1031 // prevents external agents from changing any specific state
1032 // that the trap need.
1033 cpu->trap(inst_fault, tid);
1035 // Exit state update mode to avoid accidental updating.
1036 thread[tid]->inSyscall = false;
1038 commitStatus[tid] = TrapPending;
1040 // Generate trap squash event.
1041 generateTrapEvent(tid);
1046 updateComInstStats(head_inst);
1048 if (head_inst->traceData) {
1049 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1050 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1051 head_inst->traceData->finalize();
1052 head_inst->traceData = NULL;
1055 // Update the commit rename map
1056 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1057 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1058 head_inst->renamedDestRegIdx(i));
1061 // Finally clear the head ROB entry.
1062 rob->retireHead(tid);
1064 // Return true to indicate that we have committed an instruction.
1068 template <class Impl>
1070 DefaultCommit<Impl>::getInsts()
1072 // Read any renamed instructions and place them into the ROB.
1073 int insts_to_process = min((int)renameWidth, fromRename->size);
1075 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1077 DynInstPtr inst = fromRename->insts[inst_num];
1078 int tid = inst->threadNumber;
1080 if (!inst->isSquashed() &&
1081 commitStatus[tid] != ROBSquashing) {
1082 changedROBNumEntries[tid] = true;
1084 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1085 inst->readPC(), inst->seqNum, tid);
1087 rob->insertInst(inst);
1089 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1091 youngestSeqNum[tid] = inst->seqNum;
1093 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1094 "squashed, skipping.\n",
1095 inst->readPC(), inst->seqNum, tid);
1100 template <class Impl>
1102 DefaultCommit<Impl>::markCompletedInsts()
1104 // Grab completed insts out of the IEW instruction queue, and mark
1105 // instructions completed within the ROB.
1106 for (int inst_num = 0;
1107 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1110 if (!fromIEW->insts[inst_num]->isSquashed()) {
1111 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1113 fromIEW->insts[inst_num]->threadNumber,
1114 fromIEW->insts[inst_num]->readPC(),
1115 fromIEW->insts[inst_num]->seqNum);
1117 // Mark the instruction as ready to commit.
1118 fromIEW->insts[inst_num]->setCanCommit();
1123 template <class Impl>
1125 DefaultCommit<Impl>::robDoneSquashing()
1127 list<unsigned>::iterator threads = (*activeThreads).begin();
1129 while (threads != (*activeThreads).end()) {
1130 unsigned tid = *threads++;
1132 if (!rob->isDoneSquashing(tid))
1139 template <class Impl>
1141 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1143 unsigned thread = inst->threadNumber;
1146 // Pick off the software prefetches
1149 if (inst->isDataPrefetch()) {
1150 statComSwp[thread]++;
1152 statComInst[thread]++;
1155 statComInst[thread]++;
1159 // Control Instructions
1161 if (inst->isControl())
1162 statComBranches[thread]++;
1165 // Memory references
1167 if (inst->isMemRef()) {
1168 statComRefs[thread]++;
1170 if (inst->isLoad()) {
1171 statComLoads[thread]++;
1175 if (inst->isMemBarrier()) {
1176 statComMembars[thread]++;
1180 ////////////////////////////////////////
1182 // SMT COMMIT POLICY MAINTAINED HERE //
1184 ////////////////////////////////////////
1185 template <class Impl>
1187 DefaultCommit<Impl>::getCommittingThread()
1189 if (numThreads > 1) {
1190 switch (commitPolicy) {
1193 //If Policy is Aggressive, commit will call
1194 //this function multiple times per
1196 return oldestReady();
1199 return roundRobin();
1202 return oldestReady();
1208 int tid = (*activeThreads).front();
1210 if (commitStatus[tid] == Running ||
1211 commitStatus[tid] == Idle ||
1212 commitStatus[tid] == FetchTrapPending) {
1220 template<class Impl>
1222 DefaultCommit<Impl>::roundRobin()
1224 list<unsigned>::iterator pri_iter = priority_list.begin();
1225 list<unsigned>::iterator end = priority_list.end();
1227 while (pri_iter != end) {
1228 unsigned tid = *pri_iter;
1230 if (commitStatus[tid] == Running ||
1231 commitStatus[tid] == Idle ||
1232 commitStatus[tid] == FetchTrapPending) {
1234 if (rob->isHeadReady(tid)) {
1235 priority_list.erase(pri_iter);
1236 priority_list.push_back(tid);
1248 template<class Impl>
1250 DefaultCommit<Impl>::oldestReady()
1252 unsigned oldest = 0;
1255 list<unsigned>::iterator threads = (*activeThreads).begin();
1257 while (threads != (*activeThreads).end()) {
1258 unsigned tid = *threads++;
1260 if (!rob->isEmpty(tid) &&
1261 (commitStatus[tid] == Running ||
1262 commitStatus[tid] == Idle ||
1263 commitStatus[tid] == FetchTrapPending)) {
1265 if (rob->isHeadReady(tid)) {
1267 DynInstPtr head_inst = rob->readHeadInst(tid);
1272 } else if (head_inst->seqNum < oldest) {