2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
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26 * this software without specific prior written permission.
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 #include "arch/utility.hh"
48 #include "base/cp_annotate.hh"
49 #include "base/loader/symtab.hh"
50 #include "cpu/timebuf.hh"
51 #include "config/full_system.hh"
52 #include "config/the_isa.hh"
53 #include "config/use_checker.hh"
54 #include "cpu/exetrace.hh"
55 #include "cpu/o3/commit.hh"
56 #include "cpu/o3/thread_state.hh"
57 #include "params/DerivO3CPU.hh"
60 #include "cpu/checker/cpu.hh"
66 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
68 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
70 this->setFlags(AutoDelete);
75 DefaultCommit<Impl>::TrapEvent::process()
77 // This will get reset by commit if it was switched out at the
78 // time of this event processing.
79 commit->trapSquash[tid] = true;
84 DefaultCommit<Impl>::TrapEvent::description() const
90 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
93 iewToCommitDelay(params->iewToCommitDelay),
94 commitToIEWDelay(params->commitToIEWDelay),
95 renameToROBDelay(params->renameToROBDelay),
96 fetchToCommitDelay(params->commitToFetchDelay),
97 renameWidth(params->renameWidth),
98 commitWidth(params->commitWidth),
99 numThreads(params->numThreads),
102 trapLatency(params->trapLatency)
105 _nextStatus = Inactive;
106 std::string policy = params->smtCommitPolicy;
108 //Convert string to lowercase
109 std::transform(policy.begin(), policy.end(), policy.begin(),
110 (int(*)(int)) tolower);
112 //Assign commit policy
113 if (policy == "aggressive"){
114 commitPolicy = Aggressive;
116 DPRINTF(Commit,"Commit Policy set to Aggressive.");
117 } else if (policy == "roundrobin"){
118 commitPolicy = RoundRobin;
120 //Set-Up Priority List
121 for (ThreadID tid = 0; tid < numThreads; tid++) {
122 priority_list.push_back(tid);
125 DPRINTF(Commit,"Commit Policy set to Round Robin.");
126 } else if (policy == "oldestready"){
127 commitPolicy = OldestReady;
129 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
131 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
132 "RoundRobin,OldestReady}");
135 for (ThreadID tid = 0; tid < numThreads; tid++) {
136 commitStatus[tid] = Idle;
137 changedROBNumEntries[tid] = false;
138 checkEmptyROB[tid] = false;
139 trapInFlight[tid] = false;
140 committedStores[tid] = false;
141 trapSquash[tid] = false;
142 tcSquash[tid] = false;
144 lastCommitedSeqNum[tid] = 0;
151 template <class Impl>
153 DefaultCommit<Impl>::name() const
155 return cpu->name() + ".commit";
158 template <class Impl>
160 DefaultCommit<Impl>::regStats()
162 using namespace Stats;
164 .name(name() + ".commitCommittedInsts")
165 .desc("The number of committed instructions")
166 .prereq(commitCommittedInsts);
168 .name(name() + ".commitSquashedInsts")
169 .desc("The number of squashed insts skipped by commit")
170 .prereq(commitSquashedInsts);
172 .name(name() + ".commitSquashEvents")
173 .desc("The number of times commit is told to squash")
174 .prereq(commitSquashEvents);
176 .name(name() + ".commitNonSpecStalls")
177 .desc("The number of times commit has been forced to stall to "
178 "communicate backwards")
179 .prereq(commitNonSpecStalls);
181 .name(name() + ".branchMispredicts")
182 .desc("The number of times a branch was mispredicted")
183 .prereq(branchMispredicts);
185 .init(0,commitWidth,1)
186 .name(name() + ".COM:committed_per_cycle")
187 .desc("Number of insts commited each cycle")
192 .init(cpu->numThreads)
193 .name(name() + ".COM:count")
194 .desc("Number of instructions committed")
199 .init(cpu->numThreads)
200 .name(name() + ".COM:swp_count")
201 .desc("Number of s/w prefetches committed")
206 .init(cpu->numThreads)
207 .name(name() + ".COM:refs")
208 .desc("Number of memory references committed")
213 .init(cpu->numThreads)
214 .name(name() + ".COM:loads")
215 .desc("Number of loads committed")
220 .init(cpu->numThreads)
221 .name(name() + ".COM:membars")
222 .desc("Number of memory barriers committed")
227 .init(cpu->numThreads)
228 .name(name() + ".COM:branches")
229 .desc("Number of branches committed")
234 .init(cpu->numThreads)
235 .name(name() + ".COM:fp_insts")
236 .desc("Number of committed floating point instructions.")
241 .init(cpu->numThreads)
242 .name(name()+".COM:int_insts")
243 .desc("Number of committed integer instructions.")
248 .init(cpu->numThreads)
249 .name(name()+".COM:function_calls")
250 .desc("Number of function calls committed.")
255 .init(cpu->numThreads)
256 .name(name() + ".COM:bw_limited")
257 .desc("number of insts not committed due to BW limits")
261 commitEligibleSamples
262 .name(name() + ".COM:bw_lim_events")
263 .desc("number cycles where commit BW limit reached")
267 template <class Impl>
269 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
274 template <class Impl>
276 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
280 // Setup wire to send information back to IEW.
281 toIEW = timeBuffer->getWire(0);
283 // Setup wire to read data from IEW (for the ROB).
284 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
287 template <class Impl>
289 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
293 // Setup wire to get instructions from rename (for the ROB).
294 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
297 template <class Impl>
299 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
301 renameQueue = rq_ptr;
303 // Setup wire to get instructions from rename (for the ROB).
304 fromRename = renameQueue->getWire(-renameToROBDelay);
307 template <class Impl>
309 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
313 // Setup wire to get instructions from IEW.
314 fromIEW = iewQueue->getWire(-iewToCommitDelay);
317 template <class Impl>
319 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
321 iewStage = iew_stage;
326 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
328 activeThreads = at_ptr;
331 template <class Impl>
333 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
335 for (ThreadID tid = 0; tid < numThreads; tid++)
336 renameMap[tid] = &rm_ptr[tid];
339 template <class Impl>
341 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
346 template <class Impl>
348 DefaultCommit<Impl>::initStage()
350 rob->setActiveThreads(activeThreads);
353 // Broadcast the number of free entries.
354 for (ThreadID tid = 0; tid < numThreads; tid++) {
355 toIEW->commitInfo[tid].usedROB = true;
356 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
357 toIEW->commitInfo[tid].emptyROB = true;
360 // Commit must broadcast the number of free entries it has at the
361 // start of the simulation, so it starts as active.
362 cpu->activateStage(O3CPU::CommitIdx);
364 cpu->activityThisCycle();
365 trapLatency = cpu->ticks(trapLatency);
368 template <class Impl>
370 DefaultCommit<Impl>::drain()
377 template <class Impl>
379 DefaultCommit<Impl>::switchOut()
382 drainPending = false;
386 template <class Impl>
388 DefaultCommit<Impl>::resume()
390 drainPending = false;
393 template <class Impl>
395 DefaultCommit<Impl>::takeOverFrom()
399 _nextStatus = Inactive;
400 for (ThreadID tid = 0; tid < numThreads; tid++) {
401 commitStatus[tid] = Idle;
402 changedROBNumEntries[tid] = false;
403 trapSquash[tid] = false;
404 tcSquash[tid] = false;
410 template <class Impl>
412 DefaultCommit<Impl>::updateStatus()
414 // reset ROB changed variable
415 list<ThreadID>::iterator threads = activeThreads->begin();
416 list<ThreadID>::iterator end = activeThreads->end();
418 while (threads != end) {
419 ThreadID tid = *threads++;
421 changedROBNumEntries[tid] = false;
423 // Also check if any of the threads has a trap pending
424 if (commitStatus[tid] == TrapPending ||
425 commitStatus[tid] == FetchTrapPending) {
426 _nextStatus = Active;
430 if (_nextStatus == Inactive && _status == Active) {
431 DPRINTF(Activity, "Deactivating stage.\n");
432 cpu->deactivateStage(O3CPU::CommitIdx);
433 } else if (_nextStatus == Active && _status == Inactive) {
434 DPRINTF(Activity, "Activating stage.\n");
435 cpu->activateStage(O3CPU::CommitIdx);
438 _status = _nextStatus;
441 template <class Impl>
443 DefaultCommit<Impl>::setNextStatus()
447 list<ThreadID>::iterator threads = activeThreads->begin();
448 list<ThreadID>::iterator end = activeThreads->end();
450 while (threads != end) {
451 ThreadID tid = *threads++;
453 if (commitStatus[tid] == ROBSquashing) {
458 squashCounter = squashes;
460 // If commit is currently squashing, then it will have activity for the
461 // next cycle. Set its next status as active.
463 _nextStatus = Active;
467 template <class Impl>
469 DefaultCommit<Impl>::changedROBEntries()
471 list<ThreadID>::iterator threads = activeThreads->begin();
472 list<ThreadID>::iterator end = activeThreads->end();
474 while (threads != end) {
475 ThreadID tid = *threads++;
477 if (changedROBNumEntries[tid]) {
485 template <class Impl>
487 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
489 return rob->numFreeEntries(tid);
492 template <class Impl>
494 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
496 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
498 TrapEvent *trap = new TrapEvent(this, tid);
500 cpu->schedule(trap, curTick() + trapLatency);
501 trapInFlight[tid] = true;
504 template <class Impl>
506 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
508 assert(!trapInFlight[tid]);
509 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
511 tcSquash[tid] = true;
514 template <class Impl>
516 DefaultCommit<Impl>::squashAll(ThreadID tid)
518 // If we want to include the squashing instruction in the squash,
519 // then use one older sequence number.
520 // Hopefully this doesn't mess things up. Basically I want to squash
521 // all instructions of this thread.
522 InstSeqNum squashed_inst = rob->isEmpty() ?
523 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
525 // All younger instructions will be squashed. Set the sequence
526 // number as the youngest instruction in the ROB (0 in this case.
527 // Hopefully nothing breaks.)
528 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
530 rob->squash(squashed_inst, tid);
531 changedROBNumEntries[tid] = true;
533 // Send back the sequence number of the squashed instruction.
534 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
536 // Send back the squash signal to tell stages that they should
538 toIEW->commitInfo[tid].squash = true;
540 // Send back the rob squashing signal so other stages know that
541 // the ROB is in the process of squashing.
542 toIEW->commitInfo[tid].robSquashing = true;
544 toIEW->commitInfo[tid].mispredictInst = NULL;
545 toIEW->commitInfo[tid].squashInst = NULL;
547 toIEW->commitInfo[tid].pc = pc[tid];
550 template <class Impl>
552 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
556 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
558 thread[tid]->trapPending = false;
559 thread[tid]->inSyscall = false;
560 trapInFlight[tid] = false;
562 trapSquash[tid] = false;
564 commitStatus[tid] = ROBSquashing;
565 cpu->activityThisCycle();
568 template <class Impl>
570 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
574 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
576 thread[tid]->inSyscall = false;
577 assert(!thread[tid]->trapPending);
579 commitStatus[tid] = ROBSquashing;
580 cpu->activityThisCycle();
582 tcSquash[tid] = false;
585 template <class Impl>
587 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
588 uint64_t squash_after_seq_num)
590 youngestSeqNum[tid] = squash_after_seq_num;
592 rob->squash(squash_after_seq_num, tid);
593 changedROBNumEntries[tid] = true;
595 // Send back the sequence number of the squashed instruction.
596 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
598 toIEW->commitInfo[tid].squashInst = head_inst;
599 // Send back the squash signal to tell stages that they should squash.
600 toIEW->commitInfo[tid].squash = true;
602 // Send back the rob squashing signal so other stages know that
603 // the ROB is in the process of squashing.
604 toIEW->commitInfo[tid].robSquashing = true;
606 toIEW->commitInfo[tid].mispredictInst = NULL;
608 toIEW->commitInfo[tid].pc = pc[tid];
609 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
610 tid, squash_after_seq_num);
611 commitStatus[tid] = ROBSquashing;
614 template <class Impl>
616 DefaultCommit<Impl>::tick()
618 wroteToTimeBuffer = false;
619 _nextStatus = Inactive;
621 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
622 cpu->signalDrained();
623 drainPending = false;
627 if (activeThreads->empty())
630 list<ThreadID>::iterator threads = activeThreads->begin();
631 list<ThreadID>::iterator end = activeThreads->end();
633 // Check if any of the threads are done squashing. Change the
634 // status if they are done.
635 while (threads != end) {
636 ThreadID tid = *threads++;
638 // Clear the bit saying if the thread has committed stores
640 committedStores[tid] = false;
642 if (commitStatus[tid] == ROBSquashing) {
644 if (rob->isDoneSquashing(tid)) {
645 commitStatus[tid] = Running;
647 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
648 " insts this cycle.\n", tid);
650 toIEW->commitInfo[tid].robSquashing = true;
651 wroteToTimeBuffer = true;
658 markCompletedInsts();
660 threads = activeThreads->begin();
662 while (threads != end) {
663 ThreadID tid = *threads++;
665 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
666 // The ROB has more instructions it can commit. Its next status
668 _nextStatus = Active;
670 DynInstPtr inst = rob->readHeadInst(tid);
672 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
673 " ROB and ready to commit\n",
674 tid, inst->seqNum, inst->pcState());
676 } else if (!rob->isEmpty(tid)) {
677 DynInstPtr inst = rob->readHeadInst(tid);
679 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
680 "%s is head of ROB and not ready\n",
681 tid, inst->seqNum, inst->pcState());
684 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
685 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
689 if (wroteToTimeBuffer) {
690 DPRINTF(Activity, "Activity This Cycle.\n");
691 cpu->activityThisCycle();
698 template <class Impl>
700 DefaultCommit<Impl>::handleInterrupt()
702 // Verify that we still have an interrupt to handle
703 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
704 DPRINTF(Commit, "Pending interrupt is cleared by master before "
705 "it got handled. Restart fetching from the orig path.\n");
706 toIEW->commitInfo[0].clearInterrupt = true;
711 // Wait until the ROB is empty and all stores have drained in
712 // order to enter the interrupt.
713 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
714 // Squash or record that I need to squash this cycle if
715 // an interrupt needed to be handled.
716 DPRINTF(Commit, "Interrupt detected.\n");
718 // Clear the interrupt now that it's going to be handled
719 toIEW->commitInfo[0].clearInterrupt = true;
721 assert(!thread[0]->inSyscall);
722 thread[0]->inSyscall = true;
724 // CPU will handle interrupt.
725 cpu->processInterrupts(interrupt);
727 thread[0]->inSyscall = false;
729 commitStatus[0] = TrapPending;
731 // Generate trap squash event.
732 generateTrapEvent(0);
736 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
740 template <class Impl>
742 DefaultCommit<Impl>::propagateInterrupt()
744 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
748 // Process interrupts if interrupts are enabled, not in PAL
749 // mode, and no other traps or external squashes are currently
751 // @todo: Allow other threads to handle interrupts.
753 // Get any interrupt that happened
754 interrupt = cpu->getInterrupts();
756 // Tell fetch that there is an interrupt pending. This
757 // will make fetch wait until it sees a non PAL-mode PC,
758 // at which point it stops fetching instructions.
759 if (interrupt != NoFault)
760 toIEW->commitInfo[0].interruptPending = true;
763 #endif // FULL_SYSTEM
765 template <class Impl>
767 DefaultCommit<Impl>::commit()
771 // Check for any interrupt that we've already squashed for and start processing it.
772 if (interrupt != NoFault)
775 // Check if we have a interrupt and get read to handle it
776 if (cpu->checkInterrupts(cpu->tcBase(0)))
777 propagateInterrupt();
778 #endif // FULL_SYSTEM
780 ////////////////////////////////////
781 // Check for any possible squashes, handle them first
782 ////////////////////////////////////
783 list<ThreadID>::iterator threads = activeThreads->begin();
784 list<ThreadID>::iterator end = activeThreads->end();
786 while (threads != end) {
787 ThreadID tid = *threads++;
789 // Not sure which one takes priority. I think if we have
790 // both, that's a bad sign.
791 if (trapSquash[tid] == true) {
792 assert(!tcSquash[tid]);
794 } else if (tcSquash[tid] == true) {
795 assert(commitStatus[tid] != TrapPending);
799 // Squashed sequence number must be older than youngest valid
800 // instruction in the ROB. This prevents squashes from younger
801 // instructions overriding squashes from older instructions.
802 if (fromIEW->squash[tid] &&
803 commitStatus[tid] != TrapPending &&
804 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
806 if (fromIEW->mispredictInst[tid]) {
808 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
810 fromIEW->mispredictInst[tid]->instAddr(),
811 fromIEW->squashedSeqNum[tid]);
814 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
815 tid, fromIEW->squashedSeqNum[tid]);
818 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
820 fromIEW->pc[tid].nextInstAddr());
822 commitStatus[tid] = ROBSquashing;
824 // If we want to include the squashing instruction in the squash,
825 // then use one older sequence number.
826 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
828 if (fromIEW->includeSquashInst[tid] == true) {
832 // All younger instructions will be squashed. Set the sequence
833 // number as the youngest instruction in the ROB.
834 youngestSeqNum[tid] = squashed_inst;
836 rob->squash(squashed_inst, tid);
837 changedROBNumEntries[tid] = true;
839 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
841 toIEW->commitInfo[tid].squash = true;
843 // Send back the rob squashing signal so other stages know that
844 // the ROB is in the process of squashing.
845 toIEW->commitInfo[tid].robSquashing = true;
847 toIEW->commitInfo[tid].mispredictInst =
848 fromIEW->mispredictInst[tid];
849 toIEW->commitInfo[tid].branchTaken =
850 fromIEW->branchTaken[tid];
851 toIEW->commitInfo[tid].squashInst = NULL;
853 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
855 if (toIEW->commitInfo[tid].mispredictInst) {
864 if (squashCounter != numThreads) {
865 // If we're not currently squashing, then get instructions.
868 // Try to commit any instructions.
872 //Check for any activity
873 threads = activeThreads->begin();
875 while (threads != end) {
876 ThreadID tid = *threads++;
878 if (changedROBNumEntries[tid]) {
879 toIEW->commitInfo[tid].usedROB = true;
880 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
882 wroteToTimeBuffer = true;
883 changedROBNumEntries[tid] = false;
884 if (rob->isEmpty(tid))
885 checkEmptyROB[tid] = true;
888 // ROB is only considered "empty" for previous stages if: a)
889 // ROB is empty, b) there are no outstanding stores, c) IEW
890 // stage has received any information regarding stores that
892 // c) is checked by making sure to not consider the ROB empty
893 // on the same cycle as when stores have been committed.
894 // @todo: Make this handle multi-cycle communication between
896 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
897 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
898 checkEmptyROB[tid] = false;
899 toIEW->commitInfo[tid].usedROB = true;
900 toIEW->commitInfo[tid].emptyROB = true;
901 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
902 wroteToTimeBuffer = true;
908 template <class Impl>
910 DefaultCommit<Impl>::commitInsts()
912 ////////////////////////////////////
914 // Note that commit will be handled prior to putting new
915 // instructions in the ROB so that the ROB only tries to commit
916 // instructions it has in this current cycle, and not instructions
917 // it is writing in during this cycle. Can't commit and squash
918 // things at the same time...
919 ////////////////////////////////////
921 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
923 unsigned num_committed = 0;
925 DynInstPtr head_inst;
927 // Commit as many instructions as possible until the commit bandwidth
928 // limit is reached, or it becomes impossible to commit any more.
929 while (num_committed < commitWidth) {
930 int commit_thread = getCommittingThread();
932 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
935 head_inst = rob->readHeadInst(commit_thread);
937 ThreadID tid = head_inst->threadNumber;
939 assert(tid == commit_thread);
941 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
942 head_inst->seqNum, tid);
944 // If the head instruction is squashed, it is ready to retire
945 // (be removed from the ROB) at any time.
946 if (head_inst->isSquashed()) {
948 DPRINTF(Commit, "Retiring squashed instruction from "
951 rob->retireHead(commit_thread);
953 ++commitSquashedInsts;
955 // Record that the number of ROB entries has changed.
956 changedROBNumEntries[tid] = true;
958 pc[tid] = head_inst->pcState();
960 // Increment the total number of non-speculative instructions
962 // Hack for now: it really shouldn't happen until after the
963 // commit is deemed to be successful, but this count is needed
965 thread[tid]->funcExeInst++;
967 // Try to commit the head instruction.
968 bool commit_success = commitHead(head_inst, num_committed);
970 if (commit_success) {
973 changedROBNumEntries[tid] = true;
975 // Set the doneSeqNum to the youngest committed instruction.
976 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
978 ++commitCommittedInsts;
980 // To match the old model, don't count nops and instruction
981 // prefetches towards the total commit count.
982 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
986 // Updates misc. registers.
987 head_inst->updateMiscRegs();
989 TheISA::advancePC(pc[tid], head_inst->staticInst);
991 // Keep track of the last sequence number commited
992 lastCommitedSeqNum[tid] = head_inst->seqNum;
994 // If this is an instruction that doesn't play nicely with
995 // others squash everything and restart fetch
996 if (head_inst->isSquashAfter())
997 squashAfter(tid, head_inst, head_inst->seqNum);
1001 // Debug statement. Checks to make sure we're not
1002 // currently updating state while handling PC events.
1003 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1005 oldpc = pc[tid].instAddr();
1006 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1008 } while (oldpc != pc[tid].instAddr());
1011 "PC skip function event, stopping commit\n");
1015 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1016 "[tid:%i] [sn:%i].\n",
1017 head_inst->pcState(), tid ,head_inst->seqNum);
1023 DPRINTF(CommitRate, "%i\n", num_committed);
1024 numCommittedDist.sample(num_committed);
1026 if (num_committed == commitWidth) {
1027 commitEligibleSamples++;
1031 template <class Impl>
1033 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1037 ThreadID tid = head_inst->threadNumber;
1039 // If the instruction is not executed yet, then it will need extra
1040 // handling. Signal backwards that it should be executed.
1041 if (!head_inst->isExecuted()) {
1042 // Keep this number correct. We have not yet actually executed
1043 // and committed this instruction.
1044 thread[tid]->funcExeInst--;
1046 if (head_inst->isNonSpeculative() ||
1047 head_inst->isStoreConditional() ||
1048 head_inst->isMemBarrier() ||
1049 head_inst->isWriteBarrier()) {
1051 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1052 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1053 head_inst->seqNum, head_inst->pcState());
1055 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1056 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1060 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1062 // Change the instruction so it won't try to commit again until
1064 head_inst->clearCanCommit();
1066 ++commitNonSpecStalls;
1069 } else if (head_inst->isLoad()) {
1070 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1071 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1075 assert(head_inst->uncacheable());
1076 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1077 head_inst->seqNum, head_inst->pcState());
1079 // Send back the non-speculative instruction's sequence
1080 // number. Tell the lsq to re-execute the load.
1081 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1082 toIEW->commitInfo[tid].uncached = true;
1083 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1085 head_inst->clearCanCommit();
1089 panic("Trying to commit un-executed instruction "
1090 "of unknown type!\n");
1094 if (head_inst->isThreadSync()) {
1095 // Not handled for now.
1096 panic("Thread sync instructions are not handled yet.\n");
1099 // Check if the instruction caused a fault. If so, trap.
1100 Fault inst_fault = head_inst->getFault();
1102 // Stores mark themselves as completed.
1103 if (!head_inst->isStore() && inst_fault == NoFault) {
1104 head_inst->setCompleted();
1108 // Use checker prior to updating anything due to traps or PC
1111 cpu->checker->verify(head_inst);
1115 if (inst_fault != NoFault) {
1116 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1117 head_inst->seqNum, head_inst->pcState());
1119 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1120 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1124 head_inst->setCompleted();
1127 if (cpu->checker && head_inst->isStore()) {
1128 cpu->checker->verify(head_inst);
1132 assert(!thread[tid]->inSyscall);
1134 // Mark that we're in state update mode so that the trap's
1135 // execution doesn't generate extra squashes.
1136 thread[tid]->inSyscall = true;
1138 // Execute the trap. Although it's slightly unrealistic in
1139 // terms of timing (as it doesn't wait for the full timing of
1140 // the trap event to complete before updating state), it's
1141 // needed to update the state as soon as possible. This
1142 // prevents external agents from changing any specific state
1143 // that the trap need.
1144 cpu->trap(inst_fault, tid, head_inst->staticInst);
1146 // Exit state update mode to avoid accidental updating.
1147 thread[tid]->inSyscall = false;
1149 commitStatus[tid] = TrapPending;
1151 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1153 if (head_inst->traceData) {
1154 if (DTRACE(ExecFaulting)) {
1155 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1156 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1157 head_inst->traceData->dump();
1159 delete head_inst->traceData;
1160 head_inst->traceData = NULL;
1163 // Generate trap squash event.
1164 generateTrapEvent(tid);
1168 updateComInstStats(head_inst);
1171 if (thread[tid]->profile) {
1172 thread[tid]->profilePC = head_inst->instAddr();
1173 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1174 head_inst->staticInst);
1177 thread[tid]->profileNode = node;
1179 if (CPA::available()) {
1180 if (head_inst->isControl()) {
1181 ThreadContext *tc = thread[tid]->getTC();
1182 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1186 DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
1188 if (head_inst->traceData) {
1189 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1190 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1191 head_inst->traceData->dump();
1192 delete head_inst->traceData;
1193 head_inst->traceData = NULL;
1196 // Update the commit rename map
1197 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1198 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1199 head_inst->renamedDestRegIdx(i));
1202 // Finally clear the head ROB entry.
1203 rob->retireHead(tid);
1205 // If this was a store, record it for this cycle.
1206 if (head_inst->isStore())
1207 committedStores[tid] = true;
1209 // Return true to indicate that we have committed an instruction.
1213 template <class Impl>
1215 DefaultCommit<Impl>::getInsts()
1217 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1219 // Read any renamed instructions and place them into the ROB.
1220 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1222 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1225 inst = fromRename->insts[inst_num];
1226 ThreadID tid = inst->threadNumber;
1228 if (!inst->isSquashed() &&
1229 commitStatus[tid] != ROBSquashing &&
1230 commitStatus[tid] != TrapPending) {
1231 changedROBNumEntries[tid] = true;
1233 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1234 inst->pcState(), inst->seqNum, tid);
1236 rob->insertInst(inst);
1238 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1240 youngestSeqNum[tid] = inst->seqNum;
1242 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1243 "squashed, skipping.\n",
1244 inst->pcState(), inst->seqNum, tid);
1249 template <class Impl>
1251 DefaultCommit<Impl>::skidInsert()
1253 DPRINTF(Commit, "Attempting to any instructions from rename into "
1256 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1257 DynInstPtr inst = fromRename->insts[inst_num];
1259 if (!inst->isSquashed()) {
1260 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1261 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1262 inst->threadNumber);
1263 skidBuffer.push(inst);
1265 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1266 "squashed, skipping.\n",
1267 inst->pcState(), inst->seqNum, inst->threadNumber);
1272 template <class Impl>
1274 DefaultCommit<Impl>::markCompletedInsts()
1276 // Grab completed insts out of the IEW instruction queue, and mark
1277 // instructions completed within the ROB.
1278 for (int inst_num = 0;
1279 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1282 if (!fromIEW->insts[inst_num]->isSquashed()) {
1283 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1285 fromIEW->insts[inst_num]->threadNumber,
1286 fromIEW->insts[inst_num]->pcState(),
1287 fromIEW->insts[inst_num]->seqNum);
1289 // Mark the instruction as ready to commit.
1290 fromIEW->insts[inst_num]->setCanCommit();
1295 template <class Impl>
1297 DefaultCommit<Impl>::robDoneSquashing()
1299 list<ThreadID>::iterator threads = activeThreads->begin();
1300 list<ThreadID>::iterator end = activeThreads->end();
1302 while (threads != end) {
1303 ThreadID tid = *threads++;
1305 if (!rob->isDoneSquashing(tid))
1312 template <class Impl>
1314 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1316 ThreadID tid = inst->threadNumber;
1319 // Pick off the software prefetches
1322 if (inst->isDataPrefetch()) {
1332 // Control Instructions
1334 if (inst->isControl())
1335 statComBranches[tid]++;
1338 // Memory references
1340 if (inst->isMemRef()) {
1343 if (inst->isLoad()) {
1344 statComLoads[tid]++;
1348 if (inst->isMemBarrier()) {
1349 statComMembars[tid]++;
1352 // Integer Instruction
1353 if (inst->isInteger())
1354 statComInteger[tid]++;
1356 // Floating Point Instruction
1357 if (inst->isFloating())
1358 statComFloating[tid]++;
1362 statComFunctionCalls[tid]++;
1366 ////////////////////////////////////////
1368 // SMT COMMIT POLICY MAINTAINED HERE //
1370 ////////////////////////////////////////
1371 template <class Impl>
1373 DefaultCommit<Impl>::getCommittingThread()
1375 if (numThreads > 1) {
1376 switch (commitPolicy) {
1379 //If Policy is Aggressive, commit will call
1380 //this function multiple times per
1382 return oldestReady();
1385 return roundRobin();
1388 return oldestReady();
1391 return InvalidThreadID;
1394 assert(!activeThreads->empty());
1395 ThreadID tid = activeThreads->front();
1397 if (commitStatus[tid] == Running ||
1398 commitStatus[tid] == Idle ||
1399 commitStatus[tid] == FetchTrapPending) {
1402 return InvalidThreadID;
1407 template<class Impl>
1409 DefaultCommit<Impl>::roundRobin()
1411 list<ThreadID>::iterator pri_iter = priority_list.begin();
1412 list<ThreadID>::iterator end = priority_list.end();
1414 while (pri_iter != end) {
1415 ThreadID tid = *pri_iter;
1417 if (commitStatus[tid] == Running ||
1418 commitStatus[tid] == Idle ||
1419 commitStatus[tid] == FetchTrapPending) {
1421 if (rob->isHeadReady(tid)) {
1422 priority_list.erase(pri_iter);
1423 priority_list.push_back(tid);
1432 return InvalidThreadID;
1435 template<class Impl>
1437 DefaultCommit<Impl>::oldestReady()
1439 unsigned oldest = 0;
1442 list<ThreadID>::iterator threads = activeThreads->begin();
1443 list<ThreadID>::iterator end = activeThreads->end();
1445 while (threads != end) {
1446 ThreadID tid = *threads++;
1448 if (!rob->isEmpty(tid) &&
1449 (commitStatus[tid] == Running ||
1450 commitStatus[tid] == Idle ||
1451 commitStatus[tid] == FetchTrapPending)) {
1453 if (rob->isHeadReady(tid)) {
1455 DynInstPtr head_inst = rob->readHeadInst(tid);
1460 } else if (head_inst->seqNum < oldest) {
1470 return InvalidThreadID;