src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include "config/full_system.hh"
  33 #include "config/use_checker.hh"
  34
  35 #include <algorithm>
  36 #include <string>
  37
  38 #include "base/loader/symtab.hh"
  39 #include "base/timebuf.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "cpu/o3/commit.hh"
  42 #include "cpu/o3/thread_state.hh"
  43
  44 #if USE_CHECKER
  45 #include "cpu/checker/cpu.hh"
  46 #endif
  47
  48 using namespace std;
  49
  50 template <class Impl>
  51 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  52                                           unsigned _tid)
  53     : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
  54 {
  55     this->setFlags(Event::AutoDelete);
  56 }
  57
  58 template <class Impl>
  59 void
  60 DefaultCommit<Impl>::TrapEvent::process()
  61 {
  62     // This will get reset by commit if it was switched out at the
  63     // time of this event processing.
  64     commit->trapSquash[tid] = true;
  65 }
  66
  67 template <class Impl>
  68 const char *
  69 DefaultCommit<Impl>::TrapEvent::description()
  70 {
  71     return "Trap event";
  72 }
  73
  74 template <class Impl>
  75 DefaultCommit<Impl>::DefaultCommit(Params *params)
  76     : squashCounter(0),
  77       iewToCommitDelay(params->iewToCommitDelay),
  78       commitToIEWDelay(params->commitToIEWDelay),
  79       renameToROBDelay(params->renameToROBDelay),
  80       fetchToCommitDelay(params->commitToFetchDelay),
  81       renameWidth(params->renameWidth),
  82       commitWidth(params->commitWidth),
  83       numThreads(params->numberOfThreads),
  84       drainPending(false),
  85       switchedOut(false),
  86       trapLatency(params->trapLatency)
  87 {
  88     _status = Active;
  89     _nextStatus = Inactive;
  90     string policy = params->smtCommitPolicy;
  91
  92     //Convert string to lowercase
  93     std::transform(policy.begin(), policy.end(), policy.begin(),
  94                    (int(*)(int)) tolower);
  95
  96     //Assign commit policy
  97     if (policy == "aggressive"){
  98         commitPolicy = Aggressive;
  99
 100         DPRINTF(Commit,"Commit Policy set to Aggressive.");
 101     } else if (policy == "roundrobin"){
 102         commitPolicy = RoundRobin;
 103
 104         //Set-Up Priority List
 105         for (int tid=0; tid < numThreads; tid++) {
 106             priority_list.push_back(tid);
 107         }
 108
 109         DPRINTF(Commit,"Commit Policy set to Round Robin.");
 110     } else if (policy == "oldestready"){
 111         commitPolicy = OldestReady;
 112
 113         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 114     } else {
 115         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 116                "RoundRobin,OldestReady}");
 117     }
 118
 119     for (int i=0; i < numThreads; i++) {
 120         commitStatus[i] = Idle;
 121         changedROBNumEntries[i] = false;
 122         trapSquash[i] = false;
 123         tcSquash[i] = false;
 124         PC[i] = nextPC[i] = nextNPC[i] = 0;
 125     }
 126 }
 127
 128 template <class Impl>
 129 std::string
 130 DefaultCommit<Impl>::name() const
 131 {
 132     return cpu->name() + ".commit";
 133 }
 134
 135 template <class Impl>
 136 void
 137 DefaultCommit<Impl>::regStats()
 138 {
 139     using namespace Stats;
 140     commitCommittedInsts
 141         .name(name() + ".commitCommittedInsts")
 142         .desc("The number of committed instructions")
 143         .prereq(commitCommittedInsts);
 144     commitSquashedInsts
 145         .name(name() + ".commitSquashedInsts")
 146         .desc("The number of squashed insts skipped by commit")
 147         .prereq(commitSquashedInsts);
 148     commitSquashEvents
 149         .name(name() + ".commitSquashEvents")
 150         .desc("The number of times commit is told to squash")
 151         .prereq(commitSquashEvents);
 152     commitNonSpecStalls
 153         .name(name() + ".commitNonSpecStalls")
 154         .desc("The number of times commit has been forced to stall to "
 155               "communicate backwards")
 156         .prereq(commitNonSpecStalls);
 157     branchMispredicts
 158         .name(name() + ".branchMispredicts")
 159         .desc("The number of times a branch was mispredicted")
 160         .prereq(branchMispredicts);
 161     numCommittedDist
 162         .init(0,commitWidth,1)
 163         .name(name() + ".COM:committed_per_cycle")
 164         .desc("Number of insts commited each cycle")
 165         .flags(Stats::pdf)
 166         ;
 167
 168     statComInst
 169         .init(cpu->number_of_threads)
 170         .name(name() + ".COM:count")
 171         .desc("Number of instructions committed")
 172         .flags(total)
 173         ;
 174
 175     statComSwp
 176         .init(cpu->number_of_threads)
 177         .name(name() + ".COM:swp_count")
 178         .desc("Number of s/w prefetches committed")
 179         .flags(total)
 180         ;
 181
 182     statComRefs
 183         .init(cpu->number_of_threads)
 184         .name(name() +  ".COM:refs")
 185         .desc("Number of memory references committed")
 186         .flags(total)
 187         ;
 188
 189     statComLoads
 190         .init(cpu->number_of_threads)
 191         .name(name() +  ".COM:loads")
 192         .desc("Number of loads committed")
 193         .flags(total)
 194         ;
 195
 196     statComMembars
 197         .init(cpu->number_of_threads)
 198         .name(name() +  ".COM:membars")
 199         .desc("Number of memory barriers committed")
 200         .flags(total)
 201         ;
 202
 203     statComBranches
 204         .init(cpu->number_of_threads)
 205         .name(name() + ".COM:branches")
 206         .desc("Number of branches committed")
 207         .flags(total)
 208         ;
 209
 210     commitEligible
 211         .init(cpu->number_of_threads)
 212         .name(name() + ".COM:bw_limited")
 213         .desc("number of insts not committed due to BW limits")
 214         .flags(total)
 215         ;
 216
 217     commitEligibleSamples
 218         .name(name() + ".COM:bw_lim_events")
 219         .desc("number cycles where commit BW limit reached")
 220         ;
 221 }
 222
 223 template <class Impl>
 224 void
 225 DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
 226 {
 227     DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
 228     cpu = cpu_ptr;
 229
 230     // Commit must broadcast the number of free entries it has at the start of
 231     // the simulation, so it starts as active.
 232     cpu->activateStage(O3CPU::CommitIdx);
 233
 234     trapLatency = cpu->cycles(trapLatency);
 235 }
 236
 237 template <class Impl>
 238 void
 239 DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
 240 {
 241     thread = threads;
 242 }
 243
 244 template <class Impl>
 245 void
 246 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 247 {
 248     DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
 249     timeBuffer = tb_ptr;
 250
 251     // Setup wire to send information back to IEW.
 252     toIEW = timeBuffer->getWire(0);
 253
 254     // Setup wire to read data from IEW (for the ROB).
 255     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 256 }
 257
 258 template <class Impl>
 259 void
 260 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 261 {
 262     DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
 263     fetchQueue = fq_ptr;
 264
 265     // Setup wire to get instructions from rename (for the ROB).
 266     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 267 }
 268
 269 template <class Impl>
 270 void
 271 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 272 {
 273     DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
 274     renameQueue = rq_ptr;
 275
 276     // Setup wire to get instructions from rename (for the ROB).
 277     fromRename = renameQueue->getWire(-renameToROBDelay);
 278 }
 279
 280 template <class Impl>
 281 void
 282 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 283 {
 284     DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
 285     iewQueue = iq_ptr;
 286
 287     // Setup wire to get instructions from IEW.
 288     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 289 }
 290
 291 template <class Impl>
 292 void
 293 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 294 {
 295     iewStage = iew_stage;
 296 }
 297
 298 template<class Impl>
 299 void
 300 DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
 301 {
 302     DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
 303     activeThreads = at_ptr;
 304 }
 305
 306 template <class Impl>
 307 void
 308 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 309 {
 310     DPRINTF(Commit, "Setting rename map pointers.\n");
 311
 312     for (int i=0; i < numThreads; i++) {
 313         renameMap[i] = &rm_ptr[i];
 314     }
 315 }
 316
 317 template <class Impl>
 318 void
 319 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 320 {
 321     DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
 322     rob = rob_ptr;
 323 }
 324
 325 template <class Impl>
 326 void
 327 DefaultCommit<Impl>::initStage()
 328 {
 329     rob->setActiveThreads(activeThreads);
 330     rob->resetEntries();
 331
 332     // Broadcast the number of free entries.
 333     for (int i=0; i < numThreads; i++) {
 334         toIEW->commitInfo[i].usedROB = true;
 335         toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
 336     }
 337
 338     cpu->activityThisCycle();
 339 }
 340
 341 template <class Impl>
 342 bool
 343 DefaultCommit<Impl>::drain()
 344 {
 345     drainPending = true;
 346
 347     // If it's already drained, return true.
 348     if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 349         cpu->signalDrained();
 350         return true;
 351     }
 352
 353     return false;
 354 }
 355
 356 template <class Impl>
 357 void
 358 DefaultCommit<Impl>::switchOut()
 359 {
 360     switchedOut = true;
 361     drainPending = false;
 362     rob->switchOut();
 363 }
 364
 365 template <class Impl>
 366 void
 367 DefaultCommit<Impl>::resume()
 368 {
 369     drainPending = false;
 370 }
 371
 372 template <class Impl>
 373 void
 374 DefaultCommit<Impl>::takeOverFrom()
 375 {
 376     switchedOut = false;
 377     _status = Active;
 378     _nextStatus = Inactive;
 379     for (int i=0; i < numThreads; i++) {
 380         commitStatus[i] = Idle;
 381         changedROBNumEntries[i] = false;
 382         trapSquash[i] = false;
 383         tcSquash[i] = false;
 384     }
 385     squashCounter = 0;
 386     rob->takeOverFrom();
 387 }
 388
 389 template <class Impl>
 390 void
 391 DefaultCommit<Impl>::updateStatus()
 392 {
 393     // reset ROB changed variable
 394     list<unsigned>::iterator threads = (*activeThreads).begin();
 395     while (threads != (*activeThreads).end()) {
 396         unsigned tid = *threads++;
 397         changedROBNumEntries[tid] = false;
 398
 399         // Also check if any of the threads has a trap pending
 400         if (commitStatus[tid] == TrapPending ||
 401             commitStatus[tid] == FetchTrapPending) {
 402             _nextStatus = Active;
 403         }
 404     }
 405
 406     if (_nextStatus == Inactive && _status == Active) {
 407         DPRINTF(Activity, "Deactivating stage.\n");
 408         cpu->deactivateStage(O3CPU::CommitIdx);
 409     } else if (_nextStatus == Active && _status == Inactive) {
 410         DPRINTF(Activity, "Activating stage.\n");
 411         cpu->activateStage(O3CPU::CommitIdx);
 412     }
 413
 414     _status = _nextStatus;
 415 }
 416
 417 template <class Impl>
 418 void
 419 DefaultCommit<Impl>::setNextStatus()
 420 {
 421     int squashes = 0;
 422
 423     list<unsigned>::iterator threads = (*activeThreads).begin();
 424
 425     while (threads != (*activeThreads).end()) {
 426         unsigned tid = *threads++;
 427
 428         if (commitStatus[tid] == ROBSquashing) {
 429             squashes++;
 430         }
 431     }
 432
 433     squashCounter = squashes;
 434
 435     // If commit is currently squashing, then it will have activity for the
 436     // next cycle. Set its next status as active.
 437     if (squashCounter) {
 438         _nextStatus = Active;
 439     }
 440 }
 441
 442 template <class Impl>
 443 bool
 444 DefaultCommit<Impl>::changedROBEntries()
 445 {
 446     list<unsigned>::iterator threads = (*activeThreads).begin();
 447
 448     while (threads != (*activeThreads).end()) {
 449         unsigned tid = *threads++;
 450
 451         if (changedROBNumEntries[tid]) {
 452             return true;
 453         }
 454     }
 455
 456     return false;
 457 }
 458
 459 template <class Impl>
 460 unsigned
 461 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
 462 {
 463     return rob->numFreeEntries(tid);
 464 }
 465
 466 template <class Impl>
 467 void
 468 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
 469 {
 470     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 471
 472     TrapEvent *trap = new TrapEvent(this, tid);
 473
 474     trap->schedule(curTick + trapLatency);
 475
 476     thread[tid]->trapPending = true;
 477 }
 478
 479 template <class Impl>
 480 void
 481 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
 482 {
 483     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 484
 485     tcSquash[tid] = true;
 486 }
 487
 488 template <class Impl>
 489 void
 490 DefaultCommit<Impl>::squashAll(unsigned tid)
 491 {
 492     // If we want to include the squashing instruction in the squash,
 493     // then use one older sequence number.
 494     // Hopefully this doesn't mess things up.  Basically I want to squash
 495     // all instructions of this thread.
 496     InstSeqNum squashed_inst = rob->isEmpty() ?
 497         0 : rob->readHeadInst(tid)->seqNum - 1;;
 498
 499     // All younger instructions will be squashed. Set the sequence
 500     // number as the youngest instruction in the ROB (0 in this case.
 501     // Hopefully nothing breaks.)
 502     youngestSeqNum[tid] = 0;
 503
 504     rob->squash(squashed_inst, tid);
 505     changedROBNumEntries[tid] = true;
 506
 507     // Send back the sequence number of the squashed instruction.
 508     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 509
 510     // Send back the squash signal to tell stages that they should
 511     // squash.
 512     toIEW->commitInfo[tid].squash = true;
 513
 514     // Send back the rob squashing signal so other stages know that
 515     // the ROB is in the process of squashing.
 516     toIEW->commitInfo[tid].robSquashing = true;
 517
 518     toIEW->commitInfo[tid].branchMispredict = false;
 519
 520     toIEW->commitInfo[tid].nextPC = PC[tid];
 521 }
 522
 523 template <class Impl>
 524 void
 525 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
 526 {
 527     squashAll(tid);
 528
 529     DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
 530
 531     thread[tid]->trapPending = false;
 532     thread[tid]->inSyscall = false;
 533
 534     trapSquash[tid] = false;
 535
 536     commitStatus[tid] = ROBSquashing;
 537     cpu->activityThisCycle();
 538 }
 539
 540 template <class Impl>
 541 void
 542 DefaultCommit<Impl>::squashFromTC(unsigned tid)
 543 {
 544     squashAll(tid);
 545
 546     DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
 547
 548     thread[tid]->inSyscall = false;
 549     assert(!thread[tid]->trapPending);
 550
 551     commitStatus[tid] = ROBSquashing;
 552     cpu->activityThisCycle();
 553
 554     tcSquash[tid] = false;
 555 }
 556
 557 template <class Impl>
 558 void
 559 DefaultCommit<Impl>::tick()
 560 {
 561     wroteToTimeBuffer = false;
 562     _nextStatus = Inactive;
 563
 564     if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 565         cpu->signalDrained();
 566         drainPending = false;
 567         return;
 568     }
 569
 570     if ((*activeThreads).size() <= 0)
 571         return;
 572
 573     list<unsigned>::iterator threads = (*activeThreads).begin();
 574
 575     // Check if any of the threads are done squashing.  Change the
 576     // status if they are done.
 577     while (threads != (*activeThreads).end()) {
 578         unsigned tid = *threads++;
 579
 580         if (commitStatus[tid] == ROBSquashing) {
 581
 582             if (rob->isDoneSquashing(tid)) {
 583                 commitStatus[tid] = Running;
 584             } else {
 585                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 586                         " insts this cycle.\n", tid);
 587                 rob->doSquash(tid);
 588                 toIEW->commitInfo[tid].robSquashing = true;
 589                 wroteToTimeBuffer = true;
 590             }
 591         }
 592     }
 593
 594     commit();
 595
 596     markCompletedInsts();
 597
 598     threads = (*activeThreads).begin();
 599
 600     while (threads != (*activeThreads).end()) {
 601         unsigned tid = *threads++;
 602
 603         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 604             // The ROB has more instructions it can commit. Its next status
 605             // will be active.
 606             _nextStatus = Active;
 607
 608             DynInstPtr inst = rob->readHeadInst(tid);
 609
 610             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
 611                     " ROB and ready to commit\n",
 612                     tid, inst->seqNum, inst->readPC());
 613
 614         } else if (!rob->isEmpty(tid)) {
 615             DynInstPtr inst = rob->readHeadInst(tid);
 616
 617             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 618                     "%#x is head of ROB and not ready\n",
 619                     tid, inst->seqNum, inst->readPC());
 620         }
 621
 622         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 623                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 624     }
 625
 626
 627     if (wroteToTimeBuffer) {
 628         DPRINTF(Activity, "Activity This Cycle.\n");
 629         cpu->activityThisCycle();
 630     }
 631
 632     updateStatus();
 633 }
 634
 635 template <class Impl>
 636 void
 637 DefaultCommit<Impl>::commit()
 638 {
 639
 640     //////////////////////////////////////
 641     // Check for interrupts
 642     //////////////////////////////////////
 643
 644 #if FULL_SYSTEM
 645     // Process interrupts if interrupts are enabled, not in PAL mode,
 646     // and no other traps or external squashes are currently pending.
 647     // @todo: Allow other threads to handle interrupts.
 648     if (cpu->checkInterrupts &&
 649         cpu->check_interrupts() &&
 650         !cpu->inPalMode(readPC()) &&
 651         !trapSquash[0] &&
 652         !tcSquash[0]) {
 653         // Tell fetch that there is an interrupt pending.  This will
 654         // make fetch wait until it sees a non PAL-mode PC, at which
 655         // point it stops fetching instructions.
 656         toIEW->commitInfo[0].interruptPending = true;
 657
 658         // Wait until the ROB is empty and all stores have drained in
 659         // order to enter the interrupt.
 660         if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 661             // Not sure which thread should be the one to interrupt.  For now
 662             // always do thread 0.
 663             assert(!thread[0]->inSyscall);
 664             thread[0]->inSyscall = true;
 665
 666             // CPU will handle implementation of the interrupt.
 667             cpu->processInterrupts();
 668
 669             // Now squash or record that I need to squash this cycle.
 670             commitStatus[0] = TrapPending;
 671
 672             // Exit state update mode to avoid accidental updating.
 673             thread[0]->inSyscall = false;
 674
 675             // Generate trap squash event.
 676             generateTrapEvent(0);
 677
 678             toIEW->commitInfo[0].clearInterrupt = true;
 679
 680             DPRINTF(Commit, "Interrupt detected.\n");
 681         } else {
 682             DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 683         }
 684     }
 685 #endif // FULL_SYSTEM
 686
 687     ////////////////////////////////////
 688     // Check for any possible squashes, handle them first
 689     ////////////////////////////////////
 690
 691     list<unsigned>::iterator threads = (*activeThreads).begin();
 692
 693     while (threads != (*activeThreads).end()) {
 694         unsigned tid = *threads++;
 695
 696         // Not sure which one takes priority.  I think if we have
 697         // both, that's a bad sign.
 698         if (trapSquash[tid] == true) {
 699             assert(!tcSquash[tid]);
 700             squashFromTrap(tid);
 701         } else if (tcSquash[tid] == true) {
 702             squashFromTC(tid);
 703         }
 704
 705         // Squashed sequence number must be older than youngest valid
 706         // instruction in the ROB. This prevents squashes from younger
 707         // instructions overriding squashes from older instructions.
 708         if (fromIEW->squash[tid] &&
 709             commitStatus[tid] != TrapPending &&
 710             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 711
 712             DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
 713                     tid,
 714                     fromIEW->mispredPC[tid],
 715                     fromIEW->squashedSeqNum[tid]);
 716
 717             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 718                     tid,
 719                     fromIEW->nextPC[tid]);
 720
 721             commitStatus[tid] = ROBSquashing;
 722
 723             // If we want to include the squashing instruction in the squash,
 724             // then use one older sequence number.
 725             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 726
 727 #if THE_ISA != ALPHA_ISA
 728             InstSeqNum bdelay_done_seq_num;
 729             bool squash_bdelay_slot;
 730
 731             if (fromIEW->branchMispredict[tid]) {
 732                 if (fromIEW->branchTaken[tid] &&
 733                     fromIEW->condDelaySlotBranch[tid]) {
 734                     DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
 735                             "mispredicted as taken. Squashing after previous "
 736                             "inst, [sn:%i]\n",
 737                             tid, squashed_inst);
 738                      bdelay_done_seq_num = squashed_inst;
 739                      squash_bdelay_slot = true;
 740                 } else {
 741                     DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
 742                             "after delay slot [sn:%i]\n", tid, squashed_inst+1);
 743                     bdelay_done_seq_num = squashed_inst + 1;
 744                     squash_bdelay_slot = false;
 745                 }
 746             } else {
 747                 bdelay_done_seq_num = squashed_inst;
 748             }
 749 #endif
 750
 751             if (fromIEW->includeSquashInst[tid] == true) {
 752                 squashed_inst--;
 753 #if THE_ISA != ALPHA_ISA
 754                 bdelay_done_seq_num--;
 755 #endif
 756             }
 757             // All younger instructions will be squashed. Set the sequence
 758             // number as the youngest instruction in the ROB.
 759             youngestSeqNum[tid] = squashed_inst;
 760
 761 #if THE_ISA == ALPHA_ISA
 762             rob->squash(squashed_inst, tid);
 763             toIEW->commitInfo[tid].squashDelaySlot = true;
 764 #else
 765             rob->squash(bdelay_done_seq_num, tid);
 766             toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
 767             toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
 768 #endif
 769             changedROBNumEntries[tid] = true;
 770
 771             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 772
 773             toIEW->commitInfo[tid].squash = true;
 774
 775             // Send back the rob squashing signal so other stages know that
 776             // the ROB is in the process of squashing.
 777             toIEW->commitInfo[tid].robSquashing = true;
 778
 779             toIEW->commitInfo[tid].branchMispredict =
 780                 fromIEW->branchMispredict[tid];
 781
 782             toIEW->commitInfo[tid].branchTaken =
 783                 fromIEW->branchTaken[tid];
 784
 785             toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
 786
 787             toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
 788
 789             if (toIEW->commitInfo[tid].branchMispredict) {
 790                 ++branchMispredicts;
 791             }
 792         }
 793
 794     }
 795
 796     setNextStatus();
 797
 798     if (squashCounter != numThreads) {
 799         // If we're not currently squashing, then get instructions.
 800         getInsts();
 801
 802         // Try to commit any instructions.
 803         commitInsts();
 804     } else {
 805 #if THE_ISA != ALPHA_ISA
 806         skidInsert();
 807 #endif
 808     }
 809
 810     //Check for any activity
 811     threads = (*activeThreads).begin();
 812
 813     while (threads != (*activeThreads).end()) {
 814         unsigned tid = *threads++;
 815
 816         if (changedROBNumEntries[tid]) {
 817             toIEW->commitInfo[tid].usedROB = true;
 818             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 819
 820             if (rob->isEmpty(tid)) {
 821                 toIEW->commitInfo[tid].emptyROB = true;
 822             }
 823
 824             wroteToTimeBuffer = true;
 825             changedROBNumEntries[tid] = false;
 826         }
 827     }
 828 }
 829
 830 template <class Impl>
 831 void
 832 DefaultCommit<Impl>::commitInsts()
 833 {
 834     ////////////////////////////////////
 835     // Handle commit
 836     // Note that commit will be handled prior to putting new
 837     // instructions in the ROB so that the ROB only tries to commit
 838     // instructions it has in this current cycle, and not instructions
 839     // it is writing in during this cycle.  Can't commit and squash
 840     // things at the same time...
 841     ////////////////////////////////////
 842
 843     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 844
 845     unsigned num_committed = 0;
 846
 847     DynInstPtr head_inst;
 848
 849     // Commit as many instructions as possible until the commit bandwidth
 850     // limit is reached, or it becomes impossible to commit any more.
 851     while (num_committed < commitWidth) {
 852         int commit_thread = getCommittingThread();
 853
 854         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 855             break;
 856
 857         head_inst = rob->readHeadInst(commit_thread);
 858
 859         int tid = head_inst->threadNumber;
 860
 861         assert(tid == commit_thread);
 862
 863         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 864                 head_inst->seqNum, tid);
 865
 866         // If the head instruction is squashed, it is ready to retire
 867         // (be removed from the ROB) at any time.
 868         if (head_inst->isSquashed()) {
 869
 870             DPRINTF(Commit, "Retiring squashed instruction from "
 871                     "ROB.\n");
 872
 873             rob->retireHead(commit_thread);
 874
 875             ++commitSquashedInsts;
 876
 877             // Record that the number of ROB entries has changed.
 878             changedROBNumEntries[tid] = true;
 879         } else {
 880             PC[tid] = head_inst->readPC();
 881             nextPC[tid] = head_inst->readNextPC();
 882             nextNPC[tid] = head_inst->readNextNPC();
 883
 884             // Increment the total number of non-speculative instructions
 885             // executed.
 886             // Hack for now: it really shouldn't happen until after the
 887             // commit is deemed to be successful, but this count is needed
 888             // for syscalls.
 889             thread[tid]->funcExeInst++;
 890
 891             // Try to commit the head instruction.
 892             bool commit_success = commitHead(head_inst, num_committed);
 893
 894             if (commit_success) {
 895                 ++num_committed;
 896
 897                 changedROBNumEntries[tid] = true;
 898
 899                 // Set the doneSeqNum to the youngest committed instruction.
 900                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 901
 902                 ++commitCommittedInsts;
 903
 904                 // To match the old model, don't count nops and instruction
 905                 // prefetches towards the total commit count.
 906                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 907                     cpu->instDone(tid);
 908                 }
 909
 910                 PC[tid] = nextPC[tid];
 911 #if THE_ISA == ALPHA_ISA
 912                 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
 913 #else
 914                 nextPC[tid] = nextNPC[tid];
 915                 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
 916 #endif
 917
 918 #if FULL_SYSTEM
 919                 int count = 0;
 920                 Addr oldpc;
 921                 do {
 922                     // Debug statement.  Checks to make sure we're not
 923                     // currently updating state while handling PC events.
 924                     if (count == 0)
 925                         assert(!thread[tid]->inSyscall &&
 926                                !thread[tid]->trapPending);
 927                     oldpc = PC[tid];
 928                     cpu->system->pcEventQueue.service(
 929                         thread[tid]->getTC());
 930                     count++;
 931                 } while (oldpc != PC[tid]);
 932                 if (count > 1) {
 933                     DPRINTF(Commit, "PC skip function event, stopping commit\n");
 934                     break;
 935                 }
 936 #endif
 937             } else {
 938                 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
 939                         "[tid:%i] [sn:%i].\n",
 940                         head_inst->readPC(), tid ,head_inst->seqNum);
 941                 break;
 942             }
 943         }
 944     }
 945
 946     DPRINTF(CommitRate, "%i\n", num_committed);
 947     numCommittedDist.sample(num_committed);
 948
 949     if (num_committed == commitWidth) {
 950         commitEligibleSamples++;
 951     }
 952 }
 953
 954 template <class Impl>
 955 bool
 956 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 957 {
 958     assert(head_inst);
 959
 960     int tid = head_inst->threadNumber;
 961
 962     // If the instruction is not executed yet, then it will need extra
 963     // handling.  Signal backwards that it should be executed.
 964     if (!head_inst->isExecuted()) {
 965         // Keep this number correct.  We have not yet actually executed
 966         // and committed this instruction.
 967         thread[tid]->funcExeInst--;
 968
 969         head_inst->setAtCommit();
 970
 971         if (head_inst->isNonSpeculative() ||
 972             head_inst->isStoreConditional() ||
 973             head_inst->isMemBarrier() ||
 974             head_inst->isWriteBarrier()) {
 975
 976             DPRINTF(Commit, "Encountered a barrier or non-speculative "
 977                     "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
 978                     head_inst->seqNum, head_inst->readPC());
 979
 980 #if !FULL_SYSTEM
 981             // Hack to make sure syscalls/memory barriers/quiesces
 982             // aren't executed until all stores write back their data.
 983             // This direct communication shouldn't be used for
 984             // anything other than this.
 985             if (inst_num > 0 || iewStage->hasStoresToWB())
 986 #else
 987             if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
 988                     head_inst->isQuiesce()) &&
 989                 iewStage->hasStoresToWB())
 990 #endif
 991             {
 992                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
 993                 return false;
 994             }
 995
 996             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
 997
 998             // Change the instruction so it won't try to commit again until
 999             // it is executed.
1000             head_inst->clearCanCommit();
1001
1002             ++commitNonSpecStalls;
1003
1004             return false;
1005         } else if (head_inst->isLoad()) {
1006             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1007                     head_inst->seqNum, head_inst->readPC());
1008
1009             // Send back the non-speculative instruction's sequence
1010             // number.  Tell the lsq to re-execute the load.
1011             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1012             toIEW->commitInfo[tid].uncached = true;
1013             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1014
1015             head_inst->clearCanCommit();
1016
1017             return false;
1018         } else {
1019             panic("Trying to commit un-executed instruction "
1020                   "of unknown type!\n");
1021         }
1022     }
1023
1024     if (head_inst->isThreadSync()) {
1025         // Not handled for now.
1026         panic("Thread sync instructions are not handled yet.\n");
1027     }
1028
1029     // Stores mark themselves as completed.
1030     if (!head_inst->isStore()) {
1031         head_inst->setCompleted();
1032     }
1033
1034 #if USE_CHECKER
1035     // Use checker prior to updating anything due to traps or PC
1036     // based events.
1037     if (cpu->checker) {
1038         cpu->checker->verify(head_inst);
1039     }
1040 #endif
1041
1042     // Check if the instruction caused a fault.  If so, trap.
1043     Fault inst_fault = head_inst->getFault();
1044
1045     // DTB will sometimes need the machine instruction for when
1046     // faults happen.  So we will set it here, prior to the DTB
1047     // possibly needing it for its fault.
1048     thread[tid]->setInst(
1049         static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1050
1051     if (inst_fault != NoFault) {
1052         head_inst->setCompleted();
1053         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1054                 head_inst->seqNum, head_inst->readPC());
1055
1056         if (iewStage->hasStoresToWB() || inst_num > 0) {
1057             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1058             return false;
1059         }
1060
1061 #if USE_CHECKER
1062         if (cpu->checker && head_inst->isStore()) {
1063             cpu->checker->verify(head_inst);
1064         }
1065 #endif
1066
1067         assert(!thread[tid]->inSyscall);
1068
1069         // Mark that we're in state update mode so that the trap's
1070         // execution doesn't generate extra squashes.
1071         thread[tid]->inSyscall = true;
1072
1073         // Execute the trap.  Although it's slightly unrealistic in
1074         // terms of timing (as it doesn't wait for the full timing of
1075         // the trap event to complete before updating state), it's
1076         // needed to update the state as soon as possible.  This
1077         // prevents external agents from changing any specific state
1078         // that the trap need.
1079         cpu->trap(inst_fault, tid);
1080
1081         // Exit state update mode to avoid accidental updating.
1082         thread[tid]->inSyscall = false;
1083
1084         commitStatus[tid] = TrapPending;
1085
1086         // Generate trap squash event.
1087         generateTrapEvent(tid);
1088
1089         return false;
1090     }
1091
1092     updateComInstStats(head_inst);
1093
1094     if (head_inst->traceData) {
1095         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1096         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1097         head_inst->traceData->finalize();
1098         head_inst->traceData = NULL;
1099     }
1100
1101     // Update the commit rename map
1102     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1103         renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1104                                  head_inst->renamedDestRegIdx(i));
1105     }
1106
1107     // Finally clear the head ROB entry.
1108     rob->retireHead(tid);
1109
1110     // Return true to indicate that we have committed an instruction.
1111     return true;
1112 }
1113
1114 template <class Impl>
1115 void
1116 DefaultCommit<Impl>::getInsts()
1117 {
1118     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1119
1120 #if THE_ISA == ALPHA_ISA
1121     // Read any renamed instructions and place them into the ROB.
1122     int insts_to_process = min((int)renameWidth, fromRename->size);
1123 #else
1124     // Read any renamed instructions and place them into the ROB.
1125     int insts_to_process = min((int)renameWidth,
1126                                (int)(fromRename->size + skidBuffer.size()));
1127     int rename_idx = 0;
1128
1129     DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1130             "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1131             skidBuffer.size());
1132 #endif
1133
1134
1135     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1136         DynInstPtr inst;
1137
1138 #if THE_ISA == ALPHA_ISA
1139         inst = fromRename->insts[inst_num];
1140 #else
1141         // Get insts from skidBuffer or from Rename
1142         if (skidBuffer.size() > 0) {
1143             DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1144             inst = skidBuffer.front();
1145             skidBuffer.pop();
1146         } else {
1147             DPRINTF(Commit, "Grabbing rename inst.\n");
1148             inst = fromRename->insts[rename_idx++];
1149         }
1150 #endif
1151         int tid = inst->threadNumber;
1152
1153         if (!inst->isSquashed() &&
1154             commitStatus[tid] != ROBSquashing) {
1155             changedROBNumEntries[tid] = true;
1156
1157             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1158                     inst->readPC(), inst->seqNum, tid);
1159
1160             rob->insertInst(inst);
1161
1162             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1163
1164             youngestSeqNum[tid] = inst->seqNum;
1165         } else {
1166             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1167                     "squashed, skipping.\n",
1168                     inst->readPC(), inst->seqNum, tid);
1169         }
1170     }
1171
1172 #if THE_ISA != ALPHA_ISA
1173     if (rename_idx < fromRename->size) {
1174         DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1175
1176         for (;
1177              rename_idx < fromRename->size;
1178              rename_idx++) {
1179             DynInstPtr inst = fromRename->insts[rename_idx];
1180             int tid = inst->threadNumber;
1181
1182             if (!inst->isSquashed()) {
1183                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1184                         "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1185                 skidBuffer.push(inst);
1186             } else {
1187                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1188                         "squashed, skipping.\n",
1189                         inst->readPC(), inst->seqNum, tid);
1190             }
1191         }
1192     }
1193 #endif
1194
1195 }
1196
1197 template <class Impl>
1198 void
1199 DefaultCommit<Impl>::skidInsert()
1200 {
1201     DPRINTF(Commit, "Attempting to any instructions from rename into "
1202             "skidBuffer.\n");
1203
1204     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1205         DynInstPtr inst = fromRename->insts[inst_num];
1206         int tid = inst->threadNumber;
1207
1208         if (!inst->isSquashed()) {
1209             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1210                     "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1211             skidBuffer.push(inst);
1212         } else {
1213             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1214                     "squashed, skipping.\n",
1215                     inst->readPC(), inst->seqNum, tid);
1216         }
1217     }
1218 }
1219
1220 template <class Impl>
1221 void
1222 DefaultCommit<Impl>::markCompletedInsts()
1223 {
1224     // Grab completed insts out of the IEW instruction queue, and mark
1225     // instructions completed within the ROB.
1226     for (int inst_num = 0;
1227          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1228          ++inst_num)
1229     {
1230         if (!fromIEW->insts[inst_num]->isSquashed()) {
1231             DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1232                     "within ROB.\n",
1233                     fromIEW->insts[inst_num]->threadNumber,
1234                     fromIEW->insts[inst_num]->readPC(),
1235                     fromIEW->insts[inst_num]->seqNum);
1236
1237             // Mark the instruction as ready to commit.
1238             fromIEW->insts[inst_num]->setCanCommit();
1239         }
1240     }
1241 }
1242
1243 template <class Impl>
1244 bool
1245 DefaultCommit<Impl>::robDoneSquashing()
1246 {
1247     list<unsigned>::iterator threads = (*activeThreads).begin();
1248
1249     while (threads != (*activeThreads).end()) {
1250         unsigned tid = *threads++;
1251
1252         if (!rob->isDoneSquashing(tid))
1253             return false;
1254     }
1255
1256     return true;
1257 }
1258
1259 template <class Impl>
1260 void
1261 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1262 {
1263     unsigned thread = inst->threadNumber;
1264
1265     //
1266     //  Pick off the software prefetches
1267     //
1268 #ifdef TARGET_ALPHA
1269     if (inst->isDataPrefetch()) {
1270         statComSwp[thread]++;
1271     } else {
1272         statComInst[thread]++;
1273     }
1274 #else
1275     statComInst[thread]++;
1276 #endif
1277
1278     //
1279     //  Control Instructions
1280     //
1281     if (inst->isControl())
1282         statComBranches[thread]++;
1283
1284     //
1285     //  Memory references
1286     //
1287     if (inst->isMemRef()) {
1288         statComRefs[thread]++;
1289
1290         if (inst->isLoad()) {
1291             statComLoads[thread]++;
1292         }
1293     }
1294
1295     if (inst->isMemBarrier()) {
1296         statComMembars[thread]++;
1297     }
1298 }
1299
1300 ////////////////////////////////////////
1301 //                                    //
1302 //  SMT COMMIT POLICY MAINTAINED HERE //
1303 //                                    //
1304 ////////////////////////////////////////
1305 template <class Impl>
1306 int
1307 DefaultCommit<Impl>::getCommittingThread()
1308 {
1309     if (numThreads > 1) {
1310         switch (commitPolicy) {
1311
1312           case Aggressive:
1313             //If Policy is Aggressive, commit will call
1314             //this function multiple times per
1315             //cycle
1316             return oldestReady();
1317
1318           case RoundRobin:
1319             return roundRobin();
1320
1321           case OldestReady:
1322             return oldestReady();
1323
1324           default:
1325             return -1;
1326         }
1327     } else {
1328         int tid = (*activeThreads).front();
1329
1330         if (commitStatus[tid] == Running ||
1331             commitStatus[tid] == Idle ||
1332             commitStatus[tid] == FetchTrapPending) {
1333             return tid;
1334         } else {
1335             return -1;
1336         }
1337     }
1338 }
1339
1340 template<class Impl>
1341 int
1342 DefaultCommit<Impl>::roundRobin()
1343 {
1344     list<unsigned>::iterator pri_iter = priority_list.begin();
1345     list<unsigned>::iterator end      = priority_list.end();
1346
1347     while (pri_iter != end) {
1348         unsigned tid = *pri_iter;
1349
1350         if (commitStatus[tid] == Running ||
1351             commitStatus[tid] == Idle ||
1352             commitStatus[tid] == FetchTrapPending) {
1353
1354             if (rob->isHeadReady(tid)) {
1355                 priority_list.erase(pri_iter);
1356                 priority_list.push_back(tid);
1357
1358                 return tid;
1359             }
1360         }
1361
1362         pri_iter++;
1363     }
1364
1365     return -1;
1366 }
1367
1368 template<class Impl>
1369 int
1370 DefaultCommit<Impl>::oldestReady()
1371 {
1372     unsigned oldest = 0;
1373     bool first = true;
1374
1375     list<unsigned>::iterator threads = (*activeThreads).begin();
1376
1377     while (threads != (*activeThreads).end()) {
1378         unsigned tid = *threads++;
1379
1380         if (!rob->isEmpty(tid) &&
1381             (commitStatus[tid] == Running ||
1382              commitStatus[tid] == Idle ||
1383              commitStatus[tid] == FetchTrapPending)) {
1384
1385             if (rob->isHeadReady(tid)) {
1386
1387                 DynInstPtr head_inst = rob->readHeadInst(tid);
1388
1389                 if (first) {
1390                     oldest = tid;
1391                     first = false;
1392                 } else if (head_inst->seqNum < oldest) {
1393                     oldest = tid;
1394                 }
1395             }
1396         }
1397     }
1398
1399     if (!first) {
1400         return oldest;
1401     } else {
1402         return -1;
1403     }
1404 }