2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
38 #include "arch/utility.hh"
39 #include "base/loader/symtab.hh"
40 #include "base/timebuf.hh"
41 #include "cpu/exetrace.hh"
42 #include "cpu/o3/commit.hh"
43 #include "cpu/o3/thread_state.hh"
46 #include "cpu/checker/cpu.hh"
50 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
54 this->setFlags(Event::AutoDelete);
59 DefaultCommit<Impl>::TrapEvent::process()
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
68 DefaultCommit<Impl>::TrapEvent::description()
74 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
77 iewToCommitDelay(params->iewToCommitDelay),
78 commitToIEWDelay(params->commitToIEWDelay),
79 renameToROBDelay(params->renameToROBDelay),
80 fetchToCommitDelay(params->commitToFetchDelay),
81 renameWidth(params->renameWidth),
82 commitWidth(params->commitWidth),
83 numThreads(params->numberOfThreads),
86 trapLatency(params->trapLatency)
89 _nextStatus = Inactive;
90 std::string policy = params->smtCommitPolicy;
92 //Convert string to lowercase
93 std::transform(policy.begin(), policy.end(), policy.begin(),
94 (int(*)(int)) tolower);
96 //Assign commit policy
97 if (policy == "aggressive"){
98 commitPolicy = Aggressive;
100 DPRINTF(Commit,"Commit Policy set to Aggressive.");
101 } else if (policy == "roundrobin"){
102 commitPolicy = RoundRobin;
104 //Set-Up Priority List
105 for (int tid=0; tid < numThreads; tid++) {
106 priority_list.push_back(tid);
109 DPRINTF(Commit,"Commit Policy set to Round Robin.");
110 } else if (policy == "oldestready"){
111 commitPolicy = OldestReady;
113 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
115 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
116 "RoundRobin,OldestReady}");
119 for (int i=0; i < numThreads; i++) {
120 commitStatus[i] = Idle;
121 changedROBNumEntries[i] = false;
122 checkEmptyROB[i] = false;
123 trapInFlight[i] = false;
124 committedStores[i] = false;
125 trapSquash[i] = false;
127 microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0;
134 template <class Impl>
136 DefaultCommit<Impl>::name() const
138 return cpu->name() + ".commit";
141 template <class Impl>
143 DefaultCommit<Impl>::regStats()
145 using namespace Stats;
147 .name(name() + ".commitCommittedInsts")
148 .desc("The number of committed instructions")
149 .prereq(commitCommittedInsts);
151 .name(name() + ".commitSquashedInsts")
152 .desc("The number of squashed insts skipped by commit")
153 .prereq(commitSquashedInsts);
155 .name(name() + ".commitSquashEvents")
156 .desc("The number of times commit is told to squash")
157 .prereq(commitSquashEvents);
159 .name(name() + ".commitNonSpecStalls")
160 .desc("The number of times commit has been forced to stall to "
161 "communicate backwards")
162 .prereq(commitNonSpecStalls);
164 .name(name() + ".branchMispredicts")
165 .desc("The number of times a branch was mispredicted")
166 .prereq(branchMispredicts);
168 .init(0,commitWidth,1)
169 .name(name() + ".COM:committed_per_cycle")
170 .desc("Number of insts commited each cycle")
175 .init(cpu->number_of_threads)
176 .name(name() + ".COM:count")
177 .desc("Number of instructions committed")
182 .init(cpu->number_of_threads)
183 .name(name() + ".COM:swp_count")
184 .desc("Number of s/w prefetches committed")
189 .init(cpu->number_of_threads)
190 .name(name() + ".COM:refs")
191 .desc("Number of memory references committed")
196 .init(cpu->number_of_threads)
197 .name(name() + ".COM:loads")
198 .desc("Number of loads committed")
203 .init(cpu->number_of_threads)
204 .name(name() + ".COM:membars")
205 .desc("Number of memory barriers committed")
210 .init(cpu->number_of_threads)
211 .name(name() + ".COM:branches")
212 .desc("Number of branches committed")
217 .init(cpu->number_of_threads)
218 .name(name() + ".COM:bw_limited")
219 .desc("number of insts not committed due to BW limits")
223 commitEligibleSamples
224 .name(name() + ".COM:bw_lim_events")
225 .desc("number cycles where commit BW limit reached")
229 template <class Impl>
231 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
236 template <class Impl>
238 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
242 // Setup wire to send information back to IEW.
243 toIEW = timeBuffer->getWire(0);
245 // Setup wire to read data from IEW (for the ROB).
246 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
249 template <class Impl>
251 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
255 // Setup wire to get instructions from rename (for the ROB).
256 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
259 template <class Impl>
261 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
263 renameQueue = rq_ptr;
265 // Setup wire to get instructions from rename (for the ROB).
266 fromRename = renameQueue->getWire(-renameToROBDelay);
269 template <class Impl>
271 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
275 // Setup wire to get instructions from IEW.
276 fromIEW = iewQueue->getWire(-iewToCommitDelay);
279 template <class Impl>
281 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
283 iewStage = iew_stage;
288 DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
290 activeThreads = at_ptr;
293 template <class Impl>
295 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
297 for (int i=0; i < numThreads; i++) {
298 renameMap[i] = &rm_ptr[i];
302 template <class Impl>
304 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
309 template <class Impl>
311 DefaultCommit<Impl>::initStage()
313 rob->setActiveThreads(activeThreads);
316 // Broadcast the number of free entries.
317 for (int i=0; i < numThreads; i++) {
318 toIEW->commitInfo[i].usedROB = true;
319 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
320 toIEW->commitInfo[i].emptyROB = true;
323 // Commit must broadcast the number of free entries it has at the
324 // start of the simulation, so it starts as active.
325 cpu->activateStage(O3CPU::CommitIdx);
327 cpu->activityThisCycle();
328 trapLatency = cpu->cycles(trapLatency);
331 template <class Impl>
333 DefaultCommit<Impl>::drain()
340 template <class Impl>
342 DefaultCommit<Impl>::switchOut()
345 drainPending = false;
349 template <class Impl>
351 DefaultCommit<Impl>::resume()
353 drainPending = false;
356 template <class Impl>
358 DefaultCommit<Impl>::takeOverFrom()
362 _nextStatus = Inactive;
363 for (int i=0; i < numThreads; i++) {
364 commitStatus[i] = Idle;
365 changedROBNumEntries[i] = false;
366 trapSquash[i] = false;
373 template <class Impl>
375 DefaultCommit<Impl>::updateStatus()
377 // reset ROB changed variable
378 std::list<unsigned>::iterator threads = activeThreads->begin();
379 std::list<unsigned>::iterator end = activeThreads->end();
381 while (threads != end) {
382 unsigned tid = *threads++;
384 changedROBNumEntries[tid] = false;
386 // Also check if any of the threads has a trap pending
387 if (commitStatus[tid] == TrapPending ||
388 commitStatus[tid] == FetchTrapPending) {
389 _nextStatus = Active;
393 if (_nextStatus == Inactive && _status == Active) {
394 DPRINTF(Activity, "Deactivating stage.\n");
395 cpu->deactivateStage(O3CPU::CommitIdx);
396 } else if (_nextStatus == Active && _status == Inactive) {
397 DPRINTF(Activity, "Activating stage.\n");
398 cpu->activateStage(O3CPU::CommitIdx);
401 _status = _nextStatus;
404 template <class Impl>
406 DefaultCommit<Impl>::setNextStatus()
410 std::list<unsigned>::iterator threads = activeThreads->begin();
411 std::list<unsigned>::iterator end = activeThreads->end();
413 while (threads != end) {
414 unsigned tid = *threads++;
416 if (commitStatus[tid] == ROBSquashing) {
421 squashCounter = squashes;
423 // If commit is currently squashing, then it will have activity for the
424 // next cycle. Set its next status as active.
426 _nextStatus = Active;
430 template <class Impl>
432 DefaultCommit<Impl>::changedROBEntries()
434 std::list<unsigned>::iterator threads = activeThreads->begin();
435 std::list<unsigned>::iterator end = activeThreads->end();
437 while (threads != end) {
438 unsigned tid = *threads++;
440 if (changedROBNumEntries[tid]) {
448 template <class Impl>
450 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
452 return rob->numFreeEntries(tid);
455 template <class Impl>
457 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
459 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
461 TrapEvent *trap = new TrapEvent(this, tid);
463 trap->schedule(curTick + trapLatency);
464 trapInFlight[tid] = true;
467 template <class Impl>
469 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
471 assert(!trapInFlight[tid]);
472 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
474 tcSquash[tid] = true;
477 template <class Impl>
479 DefaultCommit<Impl>::squashAll(unsigned tid)
481 // If we want to include the squashing instruction in the squash,
482 // then use one older sequence number.
483 // Hopefully this doesn't mess things up. Basically I want to squash
484 // all instructions of this thread.
485 InstSeqNum squashed_inst = rob->isEmpty() ?
486 0 : rob->readHeadInst(tid)->seqNum - 1;
488 // All younger instructions will be squashed. Set the sequence
489 // number as the youngest instruction in the ROB (0 in this case.
490 // Hopefully nothing breaks.)
491 youngestSeqNum[tid] = 0;
493 rob->squash(squashed_inst, tid);
494 changedROBNumEntries[tid] = true;
496 // Send back the sequence number of the squashed instruction.
497 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
499 // Send back the squash signal to tell stages that they should
501 toIEW->commitInfo[tid].squash = true;
503 // Send back the rob squashing signal so other stages know that
504 // the ROB is in the process of squashing.
505 toIEW->commitInfo[tid].robSquashing = true;
507 toIEW->commitInfo[tid].branchMispredict = false;
509 toIEW->commitInfo[tid].nextPC = PC[tid];
510 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
511 toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid];
514 template <class Impl>
516 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
520 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
522 thread[tid]->trapPending = false;
523 thread[tid]->inSyscall = false;
524 trapInFlight[tid] = false;
526 trapSquash[tid] = false;
528 commitStatus[tid] = ROBSquashing;
529 cpu->activityThisCycle();
532 template <class Impl>
534 DefaultCommit<Impl>::squashFromTC(unsigned tid)
538 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
540 thread[tid]->inSyscall = false;
541 assert(!thread[tid]->trapPending);
543 commitStatus[tid] = ROBSquashing;
544 cpu->activityThisCycle();
546 tcSquash[tid] = false;
549 template <class Impl>
551 DefaultCommit<Impl>::tick()
553 wroteToTimeBuffer = false;
554 _nextStatus = Inactive;
556 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
557 cpu->signalDrained();
558 drainPending = false;
562 if (activeThreads->empty())
565 std::list<unsigned>::iterator threads = activeThreads->begin();
566 std::list<unsigned>::iterator end = activeThreads->end();
568 // Check if any of the threads are done squashing. Change the
569 // status if they are done.
570 while (threads != end) {
571 unsigned tid = *threads++;
573 // Clear the bit saying if the thread has committed stores
575 committedStores[tid] = false;
577 if (commitStatus[tid] == ROBSquashing) {
579 if (rob->isDoneSquashing(tid)) {
580 commitStatus[tid] = Running;
582 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
583 " insts this cycle.\n", tid);
585 toIEW->commitInfo[tid].robSquashing = true;
586 wroteToTimeBuffer = true;
593 markCompletedInsts();
595 threads = activeThreads->begin();
597 while (threads != end) {
598 unsigned tid = *threads++;
600 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
601 // The ROB has more instructions it can commit. Its next status
603 _nextStatus = Active;
605 DynInstPtr inst = rob->readHeadInst(tid);
607 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608 " ROB and ready to commit\n",
609 tid, inst->seqNum, inst->readPC());
611 } else if (!rob->isEmpty(tid)) {
612 DynInstPtr inst = rob->readHeadInst(tid);
614 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
615 "%#x is head of ROB and not ready\n",
616 tid, inst->seqNum, inst->readPC());
619 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
620 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
624 if (wroteToTimeBuffer) {
625 DPRINTF(Activity, "Activity This Cycle.\n");
626 cpu->activityThisCycle();
633 template <class Impl>
635 DefaultCommit<Impl>::handleInterrupt()
637 if (interrupt != NoFault) {
638 // Wait until the ROB is empty and all stores have drained in
639 // order to enter the interrupt.
640 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
641 // Squash or record that I need to squash this cycle if
642 // an interrupt needed to be handled.
643 DPRINTF(Commit, "Interrupt detected.\n");
645 // Clear the interrupt now that it's going to be handled
646 toIEW->commitInfo[0].clearInterrupt = true;
648 assert(!thread[0]->inSyscall);
649 thread[0]->inSyscall = true;
651 // CPU will handle interrupt.
652 cpu->processInterrupts(interrupt);
654 thread[0]->inSyscall = false;
656 commitStatus[0] = TrapPending;
658 // Generate trap squash event.
659 generateTrapEvent(0);
663 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
665 } else if (commitStatus[0] != TrapPending &&
666 cpu->check_interrupts(cpu->tcBase(0)) &&
669 // Process interrupts if interrupts are enabled, not in PAL
670 // mode, and no other traps or external squashes are currently
672 // @todo: Allow other threads to handle interrupts.
674 // Get any interrupt that happened
675 interrupt = cpu->getInterrupts();
677 if (interrupt != NoFault) {
678 // Tell fetch that there is an interrupt pending. This
679 // will make fetch wait until it sees a non PAL-mode PC,
680 // at which point it stops fetching instructions.
681 toIEW->commitInfo[0].interruptPending = true;
685 #endif // FULL_SYSTEM
687 template <class Impl>
689 DefaultCommit<Impl>::commit()
693 // Check for any interrupt, and start processing it. Or if we
694 // have an outstanding interrupt and are at a point when it is
695 // valid to take an interrupt, process it.
696 if (cpu->check_interrupts(cpu->tcBase(0))) {
699 #endif // FULL_SYSTEM
701 ////////////////////////////////////
702 // Check for any possible squashes, handle them first
703 ////////////////////////////////////
704 std::list<unsigned>::iterator threads = activeThreads->begin();
705 std::list<unsigned>::iterator end = activeThreads->end();
707 while (threads != end) {
708 unsigned tid = *threads++;
710 // Not sure which one takes priority. I think if we have
711 // both, that's a bad sign.
712 if (trapSquash[tid] == true) {
713 assert(!tcSquash[tid]);
715 } else if (tcSquash[tid] == true) {
716 assert(commitStatus[tid] != TrapPending);
720 // Squashed sequence number must be older than youngest valid
721 // instruction in the ROB. This prevents squashes from younger
722 // instructions overriding squashes from older instructions.
723 if (fromIEW->squash[tid] &&
724 commitStatus[tid] != TrapPending &&
725 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
727 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
729 fromIEW->mispredPC[tid],
730 fromIEW->squashedSeqNum[tid]);
732 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
734 fromIEW->nextPC[tid]);
736 commitStatus[tid] = ROBSquashing;
738 // If we want to include the squashing instruction in the squash,
739 // then use one older sequence number.
740 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
742 if (fromIEW->includeSquashInst[tid] == true) {
746 // All younger instructions will be squashed. Set the sequence
747 // number as the youngest instruction in the ROB.
748 youngestSeqNum[tid] = squashed_inst;
750 rob->squash(squashed_inst, tid);
751 changedROBNumEntries[tid] = true;
753 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
755 toIEW->commitInfo[tid].squash = true;
757 // Send back the rob squashing signal so other stages know that
758 // the ROB is in the process of squashing.
759 toIEW->commitInfo[tid].robSquashing = true;
761 toIEW->commitInfo[tid].branchMispredict =
762 fromIEW->branchMispredict[tid];
764 toIEW->commitInfo[tid].branchTaken =
765 fromIEW->branchTaken[tid];
767 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
768 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
769 toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid];
771 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
773 if (toIEW->commitInfo[tid].branchMispredict) {
782 if (squashCounter != numThreads) {
783 // If we're not currently squashing, then get instructions.
786 // Try to commit any instructions.
790 //Check for any activity
791 threads = activeThreads->begin();
793 while (threads != end) {
794 unsigned tid = *threads++;
796 if (changedROBNumEntries[tid]) {
797 toIEW->commitInfo[tid].usedROB = true;
798 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
800 wroteToTimeBuffer = true;
801 changedROBNumEntries[tid] = false;
802 if (rob->isEmpty(tid))
803 checkEmptyROB[tid] = true;
806 // ROB is only considered "empty" for previous stages if: a)
807 // ROB is empty, b) there are no outstanding stores, c) IEW
808 // stage has received any information regarding stores that
810 // c) is checked by making sure to not consider the ROB empty
811 // on the same cycle as when stores have been committed.
812 // @todo: Make this handle multi-cycle communication between
814 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
815 !iewStage->hasStoresToWB() && !committedStores[tid]) {
816 checkEmptyROB[tid] = false;
817 toIEW->commitInfo[tid].usedROB = true;
818 toIEW->commitInfo[tid].emptyROB = true;
819 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
820 wroteToTimeBuffer = true;
826 template <class Impl>
828 DefaultCommit<Impl>::commitInsts()
830 ////////////////////////////////////
832 // Note that commit will be handled prior to putting new
833 // instructions in the ROB so that the ROB only tries to commit
834 // instructions it has in this current cycle, and not instructions
835 // it is writing in during this cycle. Can't commit and squash
836 // things at the same time...
837 ////////////////////////////////////
839 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
841 unsigned num_committed = 0;
843 DynInstPtr head_inst;
845 // Commit as many instructions as possible until the commit bandwidth
846 // limit is reached, or it becomes impossible to commit any more.
847 while (num_committed < commitWidth) {
848 int commit_thread = getCommittingThread();
850 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
853 head_inst = rob->readHeadInst(commit_thread);
855 int tid = head_inst->threadNumber;
857 assert(tid == commit_thread);
859 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
860 head_inst->seqNum, tid);
862 // If the head instruction is squashed, it is ready to retire
863 // (be removed from the ROB) at any time.
864 if (head_inst->isSquashed()) {
866 DPRINTF(Commit, "Retiring squashed instruction from "
869 rob->retireHead(commit_thread);
871 ++commitSquashedInsts;
873 // Record that the number of ROB entries has changed.
874 changedROBNumEntries[tid] = true;
876 PC[tid] = head_inst->readPC();
877 nextPC[tid] = head_inst->readNextPC();
878 nextNPC[tid] = head_inst->readNextNPC();
879 nextMicroPC[tid] = head_inst->readNextMicroPC();
881 // Increment the total number of non-speculative instructions
883 // Hack for now: it really shouldn't happen until after the
884 // commit is deemed to be successful, but this count is needed
886 thread[tid]->funcExeInst++;
888 // Try to commit the head instruction.
889 bool commit_success = commitHead(head_inst, num_committed);
891 if (commit_success) {
894 changedROBNumEntries[tid] = true;
896 // Set the doneSeqNum to the youngest committed instruction.
897 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
899 ++commitCommittedInsts;
901 // To match the old model, don't count nops and instruction
902 // prefetches towards the total commit count.
903 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
907 PC[tid] = nextPC[tid];
908 nextPC[tid] = nextNPC[tid];
909 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
910 microPC[tid] = nextMicroPC[tid];
911 nextMicroPC[tid] = microPC[tid] + 1;
917 // Debug statement. Checks to make sure we're not
918 // currently updating state while handling PC events.
920 assert(!thread[tid]->inSyscall &&
921 !thread[tid]->trapPending);
923 cpu->system->pcEventQueue.service(
924 thread[tid]->getTC());
926 } while (oldpc != PC[tid]);
928 DPRINTF(Commit, "PC skip function event, stopping commit\n");
933 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
934 "[tid:%i] [sn:%i].\n",
935 head_inst->readPC(), tid ,head_inst->seqNum);
941 DPRINTF(CommitRate, "%i\n", num_committed);
942 numCommittedDist.sample(num_committed);
944 if (num_committed == commitWidth) {
945 commitEligibleSamples++;
949 template <class Impl>
951 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
955 int tid = head_inst->threadNumber;
957 // If the instruction is not executed yet, then it will need extra
958 // handling. Signal backwards that it should be executed.
959 if (!head_inst->isExecuted()) {
960 // Keep this number correct. We have not yet actually executed
961 // and committed this instruction.
962 thread[tid]->funcExeInst--;
964 if (head_inst->isNonSpeculative() ||
965 head_inst->isStoreConditional() ||
966 head_inst->isMemBarrier() ||
967 head_inst->isWriteBarrier()) {
969 DPRINTF(Commit, "Encountered a barrier or non-speculative "
970 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
971 head_inst->seqNum, head_inst->readPC());
973 if (inst_num > 0 || iewStage->hasStoresToWB()) {
974 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
978 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
980 // Change the instruction so it won't try to commit again until
982 head_inst->clearCanCommit();
984 ++commitNonSpecStalls;
987 } else if (head_inst->isLoad()) {
988 if (inst_num > 0 || iewStage->hasStoresToWB()) {
989 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
993 assert(head_inst->uncacheable());
994 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
995 head_inst->seqNum, head_inst->readPC());
997 // Send back the non-speculative instruction's sequence
998 // number. Tell the lsq to re-execute the load.
999 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1000 toIEW->commitInfo[tid].uncached = true;
1001 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1003 head_inst->clearCanCommit();
1007 panic("Trying to commit un-executed instruction "
1008 "of unknown type!\n");
1012 if (head_inst->isThreadSync()) {
1013 // Not handled for now.
1014 panic("Thread sync instructions are not handled yet.\n");
1017 // Check if the instruction caused a fault. If so, trap.
1018 Fault inst_fault = head_inst->getFault();
1020 // Stores mark themselves as completed.
1021 if (!head_inst->isStore() && inst_fault == NoFault) {
1022 head_inst->setCompleted();
1026 // Use checker prior to updating anything due to traps or PC
1029 cpu->checker->verify(head_inst);
1033 // DTB will sometimes need the machine instruction for when
1034 // faults happen. So we will set it here, prior to the DTB
1035 // possibly needing it for its fault.
1036 thread[tid]->setInst(
1037 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1039 if (inst_fault != NoFault) {
1040 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1041 head_inst->seqNum, head_inst->readPC());
1043 if (iewStage->hasStoresToWB() || inst_num > 0) {
1044 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1048 head_inst->setCompleted();
1051 if (cpu->checker && head_inst->isStore()) {
1052 cpu->checker->verify(head_inst);
1056 assert(!thread[tid]->inSyscall);
1058 // Mark that we're in state update mode so that the trap's
1059 // execution doesn't generate extra squashes.
1060 thread[tid]->inSyscall = true;
1062 // Execute the trap. Although it's slightly unrealistic in
1063 // terms of timing (as it doesn't wait for the full timing of
1064 // the trap event to complete before updating state), it's
1065 // needed to update the state as soon as possible. This
1066 // prevents external agents from changing any specific state
1067 // that the trap need.
1068 cpu->trap(inst_fault, tid);
1070 // Exit state update mode to avoid accidental updating.
1071 thread[tid]->inSyscall = false;
1073 commitStatus[tid] = TrapPending;
1075 if (head_inst->traceData) {
1076 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1077 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1078 head_inst->traceData->dump();
1079 delete head_inst->traceData;
1080 head_inst->traceData = NULL;
1083 // Generate trap squash event.
1084 generateTrapEvent(tid);
1085 // warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1089 updateComInstStats(head_inst);
1092 if (thread[tid]->profile) {
1093 // bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1094 // thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1095 thread[tid]->profilePC = head_inst->readPC();
1096 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1097 head_inst->staticInst);
1100 thread[tid]->profileNode = node;
1104 if (head_inst->traceData) {
1105 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1106 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1107 head_inst->traceData->dump();
1108 delete head_inst->traceData;
1109 head_inst->traceData = NULL;
1112 // Update the commit rename map
1113 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1114 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1115 head_inst->renamedDestRegIdx(i));
1118 if (head_inst->isCopy())
1119 panic("Should not commit any copy instructions!");
1121 // Finally clear the head ROB entry.
1122 rob->retireHead(tid);
1124 // If this was a store, record it for this cycle.
1125 if (head_inst->isStore())
1126 committedStores[tid] = true;
1128 // Return true to indicate that we have committed an instruction.
1132 template <class Impl>
1134 DefaultCommit<Impl>::getInsts()
1136 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1138 // Read any renamed instructions and place them into the ROB.
1139 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1141 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1144 inst = fromRename->insts[inst_num];
1145 int tid = inst->threadNumber;
1147 if (!inst->isSquashed() &&
1148 commitStatus[tid] != ROBSquashing &&
1149 commitStatus[tid] != TrapPending) {
1150 changedROBNumEntries[tid] = true;
1152 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1153 inst->readPC(), inst->seqNum, tid);
1155 rob->insertInst(inst);
1157 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1159 youngestSeqNum[tid] = inst->seqNum;
1161 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1162 "squashed, skipping.\n",
1163 inst->readPC(), inst->seqNum, tid);
1168 template <class Impl>
1170 DefaultCommit<Impl>::skidInsert()
1172 DPRINTF(Commit, "Attempting to any instructions from rename into "
1175 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1176 DynInstPtr inst = fromRename->insts[inst_num];
1178 if (!inst->isSquashed()) {
1179 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1180 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1181 inst->threadNumber);
1182 skidBuffer.push(inst);
1184 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1185 "squashed, skipping.\n",
1186 inst->readPC(), inst->seqNum, inst->threadNumber);
1191 template <class Impl>
1193 DefaultCommit<Impl>::markCompletedInsts()
1195 // Grab completed insts out of the IEW instruction queue, and mark
1196 // instructions completed within the ROB.
1197 for (int inst_num = 0;
1198 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1201 if (!fromIEW->insts[inst_num]->isSquashed()) {
1202 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1204 fromIEW->insts[inst_num]->threadNumber,
1205 fromIEW->insts[inst_num]->readPC(),
1206 fromIEW->insts[inst_num]->seqNum);
1208 // Mark the instruction as ready to commit.
1209 fromIEW->insts[inst_num]->setCanCommit();
1214 template <class Impl>
1216 DefaultCommit<Impl>::robDoneSquashing()
1218 std::list<unsigned>::iterator threads = activeThreads->begin();
1219 std::list<unsigned>::iterator end = activeThreads->end();
1221 while (threads != end) {
1222 unsigned tid = *threads++;
1224 if (!rob->isDoneSquashing(tid))
1231 template <class Impl>
1233 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1235 unsigned thread = inst->threadNumber;
1238 // Pick off the software prefetches
1241 if (inst->isDataPrefetch()) {
1242 statComSwp[thread]++;
1244 statComInst[thread]++;
1247 statComInst[thread]++;
1251 // Control Instructions
1253 if (inst->isControl())
1254 statComBranches[thread]++;
1257 // Memory references
1259 if (inst->isMemRef()) {
1260 statComRefs[thread]++;
1262 if (inst->isLoad()) {
1263 statComLoads[thread]++;
1267 if (inst->isMemBarrier()) {
1268 statComMembars[thread]++;
1272 ////////////////////////////////////////
1274 // SMT COMMIT POLICY MAINTAINED HERE //
1276 ////////////////////////////////////////
1277 template <class Impl>
1279 DefaultCommit<Impl>::getCommittingThread()
1281 if (numThreads > 1) {
1282 switch (commitPolicy) {
1285 //If Policy is Aggressive, commit will call
1286 //this function multiple times per
1288 return oldestReady();
1291 return roundRobin();
1294 return oldestReady();
1300 assert(!activeThreads->empty());
1301 int tid = activeThreads->front();
1303 if (commitStatus[tid] == Running ||
1304 commitStatus[tid] == Idle ||
1305 commitStatus[tid] == FetchTrapPending) {
1313 template<class Impl>
1315 DefaultCommit<Impl>::roundRobin()
1317 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1318 std::list<unsigned>::iterator end = priority_list.end();
1320 while (pri_iter != end) {
1321 unsigned tid = *pri_iter;
1323 if (commitStatus[tid] == Running ||
1324 commitStatus[tid] == Idle ||
1325 commitStatus[tid] == FetchTrapPending) {
1327 if (rob->isHeadReady(tid)) {
1328 priority_list.erase(pri_iter);
1329 priority_list.push_back(tid);
1341 template<class Impl>
1343 DefaultCommit<Impl>::oldestReady()
1345 unsigned oldest = 0;
1348 std::list<unsigned>::iterator threads = activeThreads->begin();
1349 std::list<unsigned>::iterator end = activeThreads->end();
1351 while (threads != end) {
1352 unsigned tid = *threads++;
1354 if (!rob->isEmpty(tid) &&
1355 (commitStatus[tid] == Running ||
1356 commitStatus[tid] == Idle ||
1357 commitStatus[tid] == FetchTrapPending)) {
1359 if (rob->isHeadReady(tid)) {
1361 DynInstPtr head_inst = rob->readHeadInst(tid);
1366 } else if (head_inst->seqNum < oldest) {