src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <algorithm>
  32 #include <string>
  33
  34 #include "base/loader/symtab.hh"
  35 #include "base/timebuf.hh"
  36 #include "cpu/checker/cpu.hh"
  37 #include "cpu/exetrace.hh"
  38 #include "cpu/o3/commit.hh"
  39 #include "cpu/o3/thread_state.hh"
  40
  41 using namespace std;
  42
  43 template <class Impl>
  44 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  45                                           unsigned _tid)
  46     : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
  47 {
  48     this->setFlags(Event::AutoDelete);
  49 }
  50
  51 template <class Impl>
  52 void
  53 DefaultCommit<Impl>::TrapEvent::process()
  54 {
  55     // This will get reset by commit if it was switched out at the
  56     // time of this event processing.
  57     commit->trapSquash[tid] = true;
  58 }
  59
  60 template <class Impl>
  61 const char *
  62 DefaultCommit<Impl>::TrapEvent::description()
  63 {
  64     return "Trap event";
  65 }
  66
  67 template <class Impl>
  68 DefaultCommit<Impl>::DefaultCommit(Params *params)
  69     : squashCounter(0),
  70       iewToCommitDelay(params->iewToCommitDelay),
  71       commitToIEWDelay(params->commitToIEWDelay),
  72       renameToROBDelay(params->renameToROBDelay),
  73       fetchToCommitDelay(params->commitToFetchDelay),
  74       renameWidth(params->renameWidth),
  75       iewWidth(params->executeWidth),
  76       commitWidth(params->commitWidth),
  77       numThreads(params->numberOfThreads),
  78       switchedOut(false),
  79       trapLatency(params->trapLatency),
  80       fetchTrapLatency(params->fetchTrapLatency)
  81 {
  82     _status = Active;
  83     _nextStatus = Inactive;
  84     string policy = params->smtCommitPolicy;
  85
  86     //Convert string to lowercase
  87     std::transform(policy.begin(), policy.end(), policy.begin(),
  88                    (int(*)(int)) tolower);
  89
  90     //Assign commit policy
  91     if (policy == "aggressive"){
  92         commitPolicy = Aggressive;
  93
  94         DPRINTF(Commit,"Commit Policy set to Aggressive.");
  95     } else if (policy == "roundrobin"){
  96         commitPolicy = RoundRobin;
  97
  98         //Set-Up Priority List
  99         for (int tid=0; tid < numThreads; tid++) {
 100             priority_list.push_back(tid);
 101         }
 102
 103         DPRINTF(Commit,"Commit Policy set to Round Robin.");
 104     } else if (policy == "oldestready"){
 105         commitPolicy = OldestReady;
 106
 107         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 108     } else {
 109         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 110                "RoundRobin,OldestReady}");
 111     }
 112
 113     for (int i=0; i < numThreads; i++) {
 114         commitStatus[i] = Idle;
 115         changedROBNumEntries[i] = false;
 116         trapSquash[i] = false;
 117         xcSquash[i] = false;
 118     }
 119
 120     fetchFaultTick = 0;
 121     fetchTrapWait = 0;
 122 }
 123
 124 template <class Impl>
 125 std::string
 126 DefaultCommit<Impl>::name() const
 127 {
 128     return cpu->name() + ".commit";
 129 }
 130
 131 template <class Impl>
 132 void
 133 DefaultCommit<Impl>::regStats()
 134 {
 135     using namespace Stats;
 136     commitCommittedInsts
 137         .name(name() + ".commitCommittedInsts")
 138         .desc("The number of committed instructions")
 139         .prereq(commitCommittedInsts);
 140     commitSquashedInsts
 141         .name(name() + ".commitSquashedInsts")
 142         .desc("The number of squashed insts skipped by commit")
 143         .prereq(commitSquashedInsts);
 144     commitSquashEvents
 145         .name(name() + ".commitSquashEvents")
 146         .desc("The number of times commit is told to squash")
 147         .prereq(commitSquashEvents);
 148     commitNonSpecStalls
 149         .name(name() + ".commitNonSpecStalls")
 150         .desc("The number of times commit has been forced to stall to "
 151               "communicate backwards")
 152         .prereq(commitNonSpecStalls);
 153     branchMispredicts
 154         .name(name() + ".branchMispredicts")
 155         .desc("The number of times a branch was mispredicted")
 156         .prereq(branchMispredicts);
 157     numCommittedDist
 158         .init(0,commitWidth,1)
 159         .name(name() + ".COM:committed_per_cycle")
 160         .desc("Number of insts commited each cycle")
 161         .flags(Stats::pdf)
 162         ;
 163
 164     statComInst
 165         .init(cpu->number_of_threads)
 166         .name(name() + ".COM:count")
 167         .desc("Number of instructions committed")
 168         .flags(total)
 169         ;
 170
 171     statComSwp
 172         .init(cpu->number_of_threads)
 173         .name(name() + ".COM:swp_count")
 174         .desc("Number of s/w prefetches committed")
 175         .flags(total)
 176         ;
 177
 178     statComRefs
 179         .init(cpu->number_of_threads)
 180         .name(name() +  ".COM:refs")
 181         .desc("Number of memory references committed")
 182         .flags(total)
 183         ;
 184
 185     statComLoads
 186         .init(cpu->number_of_threads)
 187         .name(name() +  ".COM:loads")
 188         .desc("Number of loads committed")
 189         .flags(total)
 190         ;
 191
 192     statComMembars
 193         .init(cpu->number_of_threads)
 194         .name(name() +  ".COM:membars")
 195         .desc("Number of memory barriers committed")
 196         .flags(total)
 197         ;
 198
 199     statComBranches
 200         .init(cpu->number_of_threads)
 201         .name(name() + ".COM:branches")
 202         .desc("Number of branches committed")
 203         .flags(total)
 204         ;
 205
 206     //
 207     //  Commit-Eligible instructions...
 208     //
 209     //  -> The number of instructions eligible to commit in those
 210     //  cycles where we reached our commit BW limit (less the number
 211     //  actually committed)
 212     //
 213     //  -> The average value is computed over ALL CYCLES... not just
 214     //  the BW limited cycles
 215     //
 216     //  -> The standard deviation is computed only over cycles where
 217     //  we reached the BW limit
 218     //
 219     commitEligible
 220         .init(cpu->number_of_threads)
 221         .name(name() + ".COM:bw_limited")
 222         .desc("number of insts not committed due to BW limits")
 223         .flags(total)
 224         ;
 225
 226     commitEligibleSamples
 227         .name(name() + ".COM:bw_lim_events")
 228         .desc("number cycles where commit BW limit reached")
 229         ;
 230 }
 231
 232 template <class Impl>
 233 void
 234 DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
 235 {
 236     DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
 237     cpu = cpu_ptr;
 238
 239     // Commit must broadcast the number of free entries it has at the start of
 240     // the simulation, so it starts as active.
 241     cpu->activateStage(FullCPU::CommitIdx);
 242
 243     trapLatency = cpu->cycles(trapLatency);
 244     fetchTrapLatency = cpu->cycles(fetchTrapLatency);
 245 }
 246
 247 template <class Impl>
 248 void
 249 DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
 250 {
 251     thread = threads;
 252 }
 253
 254 template <class Impl>
 255 void
 256 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 257 {
 258     DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
 259     timeBuffer = tb_ptr;
 260
 261     // Setup wire to send information back to IEW.
 262     toIEW = timeBuffer->getWire(0);
 263
 264     // Setup wire to read data from IEW (for the ROB).
 265     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 266 }
 267
 268 template <class Impl>
 269 void
 270 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 271 {
 272     DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
 273     fetchQueue = fq_ptr;
 274
 275     // Setup wire to get instructions from rename (for the ROB).
 276     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 277 }
 278
 279 template <class Impl>
 280 void
 281 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 282 {
 283     DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
 284     renameQueue = rq_ptr;
 285
 286     // Setup wire to get instructions from rename (for the ROB).
 287     fromRename = renameQueue->getWire(-renameToROBDelay);
 288 }
 289
 290 template <class Impl>
 291 void
 292 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 293 {
 294     DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
 295     iewQueue = iq_ptr;
 296
 297     // Setup wire to get instructions from IEW.
 298     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 299 }
 300
 301 template <class Impl>
 302 void
 303 DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
 304 {
 305     fetchStage = fetch_stage;
 306 }
 307
 308 template <class Impl>
 309 void
 310 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 311 {
 312     iewStage = iew_stage;
 313 }
 314
 315 template<class Impl>
 316 void
 317 DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
 318 {
 319     DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
 320     activeThreads = at_ptr;
 321 }
 322
 323 template <class Impl>
 324 void
 325 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 326 {
 327     DPRINTF(Commit, "Setting rename map pointers.\n");
 328
 329     for (int i=0; i < numThreads; i++) {
 330         renameMap[i] = &rm_ptr[i];
 331     }
 332 }
 333
 334 template <class Impl>
 335 void
 336 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 337 {
 338     DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
 339     rob = rob_ptr;
 340 }
 341
 342 template <class Impl>
 343 void
 344 DefaultCommit<Impl>::initStage()
 345 {
 346     rob->setActiveThreads(activeThreads);
 347     rob->resetEntries();
 348
 349     // Broadcast the number of free entries.
 350     for (int i=0; i < numThreads; i++) {
 351         toIEW->commitInfo[i].usedROB = true;
 352         toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
 353     }
 354
 355     cpu->activityThisCycle();
 356 }
 357
 358 template <class Impl>
 359 void
 360 DefaultCommit<Impl>::switchOut()
 361 {
 362     switchPending = true;
 363 }
 364
 365 template <class Impl>
 366 void
 367 DefaultCommit<Impl>::doSwitchOut()
 368 {
 369     switchedOut = true;
 370     switchPending = false;
 371     rob->switchOut();
 372 }
 373
 374 template <class Impl>
 375 void
 376 DefaultCommit<Impl>::takeOverFrom()
 377 {
 378     switchedOut = false;
 379     _status = Active;
 380     _nextStatus = Inactive;
 381     for (int i=0; i < numThreads; i++) {
 382         commitStatus[i] = Idle;
 383         changedROBNumEntries[i] = false;
 384         trapSquash[i] = false;
 385         xcSquash[i] = false;
 386     }
 387     squashCounter = 0;
 388     rob->takeOverFrom();
 389 }
 390
 391 template <class Impl>
 392 void
 393 DefaultCommit<Impl>::updateStatus()
 394 {
 395     // reset ROB changed variable
 396     list<unsigned>::iterator threads = (*activeThreads).begin();
 397     while (threads != (*activeThreads).end()) {
 398         unsigned tid = *threads++;
 399         changedROBNumEntries[tid] = false;
 400
 401         // Also check if any of the threads has a trap pending
 402         if (commitStatus[tid] == TrapPending ||
 403             commitStatus[tid] == FetchTrapPending) {
 404             _nextStatus = Active;
 405         }
 406     }
 407
 408     if (_nextStatus == Inactive && _status == Active) {
 409         DPRINTF(Activity, "Deactivating stage.\n");
 410         cpu->deactivateStage(FullCPU::CommitIdx);
 411     } else if (_nextStatus == Active && _status == Inactive) {
 412         DPRINTF(Activity, "Activating stage.\n");
 413         cpu->activateStage(FullCPU::CommitIdx);
 414     }
 415
 416     _status = _nextStatus;
 417 }
 418
 419 template <class Impl>
 420 void
 421 DefaultCommit<Impl>::setNextStatus()
 422 {
 423     int squashes = 0;
 424
 425     list<unsigned>::iterator threads = (*activeThreads).begin();
 426
 427     while (threads != (*activeThreads).end()) {
 428         unsigned tid = *threads++;
 429
 430         if (commitStatus[tid] == ROBSquashing) {
 431             squashes++;
 432         }
 433     }
 434
 435     assert(squashes == squashCounter);
 436
 437     // If commit is currently squashing, then it will have activity for the
 438     // next cycle. Set its next status as active.
 439     if (squashCounter) {
 440         _nextStatus = Active;
 441     }
 442 }
 443
 444 template <class Impl>
 445 bool
 446 DefaultCommit<Impl>::changedROBEntries()
 447 {
 448     list<unsigned>::iterator threads = (*activeThreads).begin();
 449
 450     while (threads != (*activeThreads).end()) {
 451         unsigned tid = *threads++;
 452
 453         if (changedROBNumEntries[tid]) {
 454             return true;
 455         }
 456     }
 457
 458     return false;
 459 }
 460
 461 template <class Impl>
 462 unsigned
 463 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
 464 {
 465     return rob->numFreeEntries(tid);
 466 }
 467
 468 template <class Impl>
 469 void
 470 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
 471 {
 472     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 473
 474     TrapEvent *trap = new TrapEvent(this, tid);
 475
 476     trap->schedule(curTick + trapLatency);
 477
 478     thread[tid]->trapPending = true;
 479 }
 480
 481 template <class Impl>
 482 void
 483 DefaultCommit<Impl>::generateXCEvent(unsigned tid)
 484 {
 485     DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
 486
 487     xcSquash[tid] = true;
 488 }
 489
 490 template <class Impl>
 491 void
 492 DefaultCommit<Impl>::squashAll(unsigned tid)
 493 {
 494     // If we want to include the squashing instruction in the squash,
 495     // then use one older sequence number.
 496     // Hopefully this doesn't mess things up.  Basically I want to squash
 497     // all instructions of this thread.
 498     InstSeqNum squashed_inst = rob->isEmpty() ?
 499         0 : rob->readHeadInst(tid)->seqNum - 1;;
 500
 501     // All younger instructions will be squashed. Set the sequence
 502     // number as the youngest instruction in the ROB (0 in this case.
 503     // Hopefully nothing breaks.)
 504     youngestSeqNum[tid] = 0;
 505
 506     rob->squash(squashed_inst, tid);
 507     changedROBNumEntries[tid] = true;
 508
 509     // Send back the sequence number of the squashed instruction.
 510     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 511
 512     // Send back the squash signal to tell stages that they should
 513     // squash.
 514     toIEW->commitInfo[tid].squash = true;
 515
 516     // Send back the rob squashing signal so other stages know that
 517     // the ROB is in the process of squashing.
 518     toIEW->commitInfo[tid].robSquashing = true;
 519
 520     toIEW->commitInfo[tid].branchMispredict = false;
 521
 522     toIEW->commitInfo[tid].nextPC = PC[tid];
 523 }
 524
 525 template <class Impl>
 526 void
 527 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
 528 {
 529     squashAll(tid);
 530
 531     DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
 532
 533     thread[tid]->trapPending = false;
 534     thread[tid]->inSyscall = false;
 535
 536     trapSquash[tid] = false;
 537
 538     commitStatus[tid] = ROBSquashing;
 539     cpu->activityThisCycle();
 540
 541     ++squashCounter;
 542 }
 543
 544 template <class Impl>
 545 void
 546 DefaultCommit<Impl>::squashFromXC(unsigned tid)
 547 {
 548     squashAll(tid);
 549
 550     DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
 551
 552     thread[tid]->inSyscall = false;
 553     assert(!thread[tid]->trapPending);
 554
 555     commitStatus[tid] = ROBSquashing;
 556     cpu->activityThisCycle();
 557
 558     xcSquash[tid] = false;
 559
 560     ++squashCounter;
 561 }
 562
 563 template <class Impl>
 564 void
 565 DefaultCommit<Impl>::tick()
 566 {
 567     wroteToTimeBuffer = false;
 568     _nextStatus = Inactive;
 569
 570     if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 571         cpu->signalSwitched();
 572         return;
 573     }
 574
 575     list<unsigned>::iterator threads = (*activeThreads).begin();
 576
 577     // Check if any of the threads are done squashing.  Change the
 578     // status if they are done.
 579     while (threads != (*activeThreads).end()) {
 580         unsigned tid = *threads++;
 581
 582         if (commitStatus[tid] == ROBSquashing) {
 583
 584             if (rob->isDoneSquashing(tid)) {
 585                 commitStatus[tid] = Running;
 586                 --squashCounter;
 587             } else {
 588                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 589                         "insts this cycle.\n", tid);
 590             }
 591         }
 592     }
 593
 594     commit();
 595
 596     markCompletedInsts();
 597
 598     threads = (*activeThreads).begin();
 599
 600     while (threads != (*activeThreads).end()) {
 601         unsigned tid = *threads++;
 602
 603         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 604             // The ROB has more instructions it can commit. Its next status
 605             // will be active.
 606             _nextStatus = Active;
 607
 608             DynInstPtr inst = rob->readHeadInst(tid);
 609
 610             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
 611                     " ROB and ready to commit\n",
 612                     tid, inst->seqNum, inst->readPC());
 613
 614         } else if (!rob->isEmpty(tid)) {
 615             DynInstPtr inst = rob->readHeadInst(tid);
 616
 617             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 618                     "%#x is head of ROB and not ready\n",
 619                     tid, inst->seqNum, inst->readPC());
 620         }
 621
 622         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 623                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 624     }
 625
 626
 627     if (wroteToTimeBuffer) {
 628         DPRINTF(Activity, "Activity This Cycle.\n");
 629         cpu->activityThisCycle();
 630     }
 631
 632     updateStatus();
 633 }
 634
 635 template <class Impl>
 636 void
 637 DefaultCommit<Impl>::commit()
 638 {
 639
 640     //////////////////////////////////////
 641     // Check for interrupts
 642     //////////////////////////////////////
 643
 644 #if FULL_SYSTEM
 645     // Process interrupts if interrupts are enabled, not in PAL mode,
 646     // and no other traps or external squashes are currently pending.
 647     // @todo: Allow other threads to handle interrupts.
 648     if (cpu->checkInterrupts &&
 649         cpu->check_interrupts() &&
 650         !cpu->inPalMode(readPC()) &&
 651         !trapSquash[0] &&
 652         !xcSquash[0]) {
 653         // Tell fetch that there is an interrupt pending.  This will
 654         // make fetch wait until it sees a non PAL-mode PC, at which
 655         // point it stops fetching instructions.
 656         toIEW->commitInfo[0].interruptPending = true;
 657
 658         // Wait until the ROB is empty and all stores have drained in
 659         // order to enter the interrupt.
 660         if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 661             // Not sure which thread should be the one to interrupt.  For now
 662             // always do thread 0.
 663             assert(!thread[0]->inSyscall);
 664             thread[0]->inSyscall = true;
 665
 666             // CPU will handle implementation of the interrupt.
 667             cpu->processInterrupts();
 668
 669             // Now squash or record that I need to squash this cycle.
 670             commitStatus[0] = TrapPending;
 671
 672             // Exit state update mode to avoid accidental updating.
 673             thread[0]->inSyscall = false;
 674
 675             // Generate trap squash event.
 676             generateTrapEvent(0);
 677
 678             toIEW->commitInfo[0].clearInterrupt = true;
 679
 680             DPRINTF(Commit, "Interrupt detected.\n");
 681         } else {
 682             DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 683         }
 684     }
 685 #endif // FULL_SYSTEM
 686
 687     ////////////////////////////////////
 688     // Check for any possible squashes, handle them first
 689     ////////////////////////////////////
 690
 691     list<unsigned>::iterator threads = (*activeThreads).begin();
 692
 693     while (threads != (*activeThreads).end()) {
 694         unsigned tid = *threads++;
 695 /*
 696         if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
 697             // Record the fault.  Wait until it's empty in the ROB.
 698             // Then handle the trap.  Ignore it if there's already a
 699             // trap pending as fetch will be redirected.
 700             fetchFault = fromFetch->fetchFault;
 701             fetchFaultTick = curTick + fetchTrapLatency;
 702             commitStatus[0] = FetchTrapPending;
 703             DPRINTF(Commit, "Fault from fetch recorded.  Will trap if the "
 704                     "ROB empties without squashing the fault.\n");
 705             fetchTrapWait = 0;
 706         }
 707
 708         // Fetch may tell commit to clear the trap if it's been squashed.
 709         if (fromFetch->clearFetchFault) {
 710             DPRINTF(Commit, "Received clear fetch fault signal\n");
 711             fetchTrapWait = 0;
 712             if (commitStatus[0] == FetchTrapPending) {
 713                 DPRINTF(Commit, "Clearing fault from fetch\n");
 714                 commitStatus[0] = Running;
 715             }
 716         }
 717 */
 718         // Not sure which one takes priority.  I think if we have
 719         // both, that's a bad sign.
 720         if (trapSquash[tid] == true) {
 721             assert(!xcSquash[tid]);
 722             squashFromTrap(tid);
 723         } else if (xcSquash[tid] == true) {
 724             squashFromXC(tid);
 725         }
 726
 727         // Squashed sequence number must be older than youngest valid
 728         // instruction in the ROB. This prevents squashes from younger
 729         // instructions overriding squashes from older instructions.
 730         if (fromIEW->squash[tid] &&
 731             commitStatus[tid] != TrapPending &&
 732             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 733
 734             DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
 735                     tid,
 736                     fromIEW->mispredPC[tid],
 737                     fromIEW->squashedSeqNum[tid]);
 738
 739             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 740                     tid,
 741                     fromIEW->nextPC[tid]);
 742
 743             commitStatus[tid] = ROBSquashing;
 744
 745             ++squashCounter;
 746
 747             // If we want to include the squashing instruction in the squash,
 748             // then use one older sequence number.
 749             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 750
 751             if (fromIEW->includeSquashInst[tid] == true)
 752                 squashed_inst--;
 753
 754             // All younger instructions will be squashed. Set the sequence
 755             // number as the youngest instruction in the ROB.
 756             youngestSeqNum[tid] = squashed_inst;
 757
 758             rob->squash(squashed_inst, tid);
 759             changedROBNumEntries[tid] = true;
 760
 761             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 762
 763             toIEW->commitInfo[tid].squash = true;
 764
 765             // Send back the rob squashing signal so other stages know that
 766             // the ROB is in the process of squashing.
 767             toIEW->commitInfo[tid].robSquashing = true;
 768
 769             toIEW->commitInfo[tid].branchMispredict =
 770                 fromIEW->branchMispredict[tid];
 771
 772             toIEW->commitInfo[tid].branchTaken =
 773                 fromIEW->branchTaken[tid];
 774
 775             toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
 776
 777             toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
 778
 779             if (toIEW->commitInfo[tid].branchMispredict) {
 780                 ++branchMispredicts;
 781             }
 782         }
 783
 784     }
 785
 786     setNextStatus();
 787
 788     if (squashCounter != numThreads) {
 789         // If we're not currently squashing, then get instructions.
 790         getInsts();
 791
 792         // Try to commit any instructions.
 793         commitInsts();
 794     }
 795
 796     //Check for any activity
 797     threads = (*activeThreads).begin();
 798
 799     while (threads != (*activeThreads).end()) {
 800         unsigned tid = *threads++;
 801
 802         if (changedROBNumEntries[tid]) {
 803             toIEW->commitInfo[tid].usedROB = true;
 804             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 805
 806             if (rob->isEmpty(tid)) {
 807                 toIEW->commitInfo[tid].emptyROB = true;
 808             }
 809
 810             wroteToTimeBuffer = true;
 811             changedROBNumEntries[tid] = false;
 812         }
 813     }
 814 }
 815
 816 template <class Impl>
 817 void
 818 DefaultCommit<Impl>::commitInsts()
 819 {
 820     ////////////////////////////////////
 821     // Handle commit
 822     // Note that commit will be handled prior to putting new
 823     // instructions in the ROB so that the ROB only tries to commit
 824     // instructions it has in this current cycle, and not instructions
 825     // it is writing in during this cycle.  Can't commit and squash
 826     // things at the same time...
 827     ////////////////////////////////////
 828
 829     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 830
 831     unsigned num_committed = 0;
 832
 833     DynInstPtr head_inst;
 834
 835     // Commit as many instructions as possible until the commit bandwidth
 836     // limit is reached, or it becomes impossible to commit any more.
 837     while (num_committed < commitWidth) {
 838         int commit_thread = getCommittingThread();
 839
 840         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 841             break;
 842
 843         head_inst = rob->readHeadInst(commit_thread);
 844
 845         int tid = head_inst->threadNumber;
 846
 847         assert(tid == commit_thread);
 848
 849         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 850                 head_inst->seqNum, tid);
 851
 852         // If the head instruction is squashed, it is ready to retire
 853         // (be removed from the ROB) at any time.
 854         if (head_inst->isSquashed()) {
 855
 856             DPRINTF(Commit, "Retiring squashed instruction from "
 857                     "ROB.\n");
 858
 859             rob->retireHead(commit_thread);
 860
 861             ++commitSquashedInsts;
 862
 863             // Record that the number of ROB entries has changed.
 864             changedROBNumEntries[tid] = true;
 865         } else {
 866             PC[tid] = head_inst->readPC();
 867             nextPC[tid] = head_inst->readNextPC();
 868
 869             // Increment the total number of non-speculative instructions
 870             // executed.
 871             // Hack for now: it really shouldn't happen until after the
 872             // commit is deemed to be successful, but this count is needed
 873             // for syscalls.
 874             thread[tid]->funcExeInst++;
 875
 876             // Try to commit the head instruction.
 877             bool commit_success = commitHead(head_inst, num_committed);
 878
 879             if (commit_success) {
 880                 ++num_committed;
 881
 882                 changedROBNumEntries[tid] = true;
 883
 884                 // Set the doneSeqNum to the youngest committed instruction.
 885                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 886
 887                 ++commitCommittedInsts;
 888
 889                 // To match the old model, don't count nops and instruction
 890                 // prefetches towards the total commit count.
 891                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 892                     cpu->instDone(tid);
 893                 }
 894
 895                 PC[tid] = nextPC[tid];
 896                 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
 897 #if FULL_SYSTEM
 898                 int count = 0;
 899                 Addr oldpc;
 900                 do {
 901                     // Debug statement.  Checks to make sure we're not
 902                     // currently updating state while handling PC events.
 903                     if (count == 0)
 904                         assert(!thread[tid]->inSyscall &&
 905                                !thread[tid]->trapPending);
 906                     oldpc = PC[tid];
 907                     cpu->system->pcEventQueue.service(
 908                         thread[tid]->getXCProxy());
 909                     count++;
 910                 } while (oldpc != PC[tid]);
 911                 if (count > 1) {
 912                     DPRINTF(Commit, "PC skip function event, stopping commit\n");
 913                     break;
 914                 }
 915 #endif
 916             } else {
 917                 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
 918                         "[tid:%i] [sn:%i].\n",
 919                         head_inst->readPC(), tid ,head_inst->seqNum);
 920                 break;
 921             }
 922         }
 923     }
 924
 925     DPRINTF(CommitRate, "%i\n", num_committed);
 926     numCommittedDist.sample(num_committed);
 927
 928     if (num_committed == commitWidth) {
 929         commitEligibleSamples++;
 930     }
 931 }
 932
 933 template <class Impl>
 934 bool
 935 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 936 {
 937     assert(head_inst);
 938
 939     int tid = head_inst->threadNumber;
 940
 941     // If the instruction is not executed yet, then it will need extra
 942     // handling.  Signal backwards that it should be executed.
 943     if (!head_inst->isExecuted()) {
 944         // Keep this number correct.  We have not yet actually executed
 945         // and committed this instruction.
 946         thread[tid]->funcExeInst--;
 947
 948         head_inst->reachedCommit = true;
 949
 950         if (head_inst->isNonSpeculative() ||
 951             head_inst->isStoreConditional() ||
 952             head_inst->isMemBarrier() ||
 953             head_inst->isWriteBarrier()) {
 954
 955             DPRINTF(Commit, "Encountered a barrier or non-speculative "
 956                     "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
 957                     head_inst->seqNum, head_inst->readPC());
 958
 959 #if !FULL_SYSTEM
 960             // Hack to make sure syscalls/memory barriers/quiesces
 961             // aren't executed until all stores write back their data.
 962             // This direct communication shouldn't be used for
 963             // anything other than this.
 964             if (inst_num > 0 || iewStage->hasStoresToWB())
 965 #else
 966             if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
 967                     head_inst->isQuiesce()) &&
 968                 iewStage->hasStoresToWB())
 969 #endif
 970             {
 971                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
 972                 return false;
 973             }
 974
 975             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
 976
 977             // Change the instruction so it won't try to commit again until
 978             // it is executed.
 979             head_inst->clearCanCommit();
 980
 981             ++commitNonSpecStalls;
 982
 983             return false;
 984         } else if (head_inst->isLoad()) {
 985             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
 986                     head_inst->seqNum, head_inst->readPC());
 987
 988             // Send back the non-speculative instruction's sequence
 989             // number.  Tell the lsq to re-execute the load.
 990             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
 991             toIEW->commitInfo[tid].uncached = true;
 992             toIEW->commitInfo[tid].uncachedLoad = head_inst;
 993
 994             head_inst->clearCanCommit();
 995
 996             return false;
 997         } else {
 998             panic("Trying to commit un-executed instruction "
 999                   "of unknown type!\n");
1000         }
1001     }
1002
1003     if (head_inst->isThreadSync()) {
1004         // Not handled for now.
1005         panic("Thread sync instructions are not handled yet.\n");
1006     }
1007
1008     // Stores mark themselves as completed.
1009     if (!head_inst->isStore()) {
1010         head_inst->setCompleted();
1011     }
1012
1013     // Use checker prior to updating anything due to traps or PC
1014     // based events.
1015     if (cpu->checker) {
1016         cpu->checker->tick(head_inst);
1017     }
1018
1019     // Check if the instruction caused a fault.  If so, trap.
1020     Fault inst_fault = head_inst->getFault();
1021
1022     if (inst_fault != NoFault) {
1023         head_inst->setCompleted();
1024 #if FULL_SYSTEM
1025         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1026                 head_inst->seqNum, head_inst->readPC());
1027
1028         if (iewStage->hasStoresToWB() || inst_num > 0) {
1029             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1030             return false;
1031         }
1032
1033         if (cpu->checker && head_inst->isStore()) {
1034             cpu->checker->tick(head_inst);
1035         }
1036
1037         assert(!thread[tid]->inSyscall);
1038
1039         // Mark that we're in state update mode so that the trap's
1040         // execution doesn't generate extra squashes.
1041         thread[tid]->inSyscall = true;
1042
1043         // DTB will sometimes need the machine instruction for when
1044         // faults happen.  So we will set it here, prior to the DTB
1045         // possibly needing it for its fault.
1046         thread[tid]->setInst(
1047             static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1048
1049         // Execute the trap.  Although it's slightly unrealistic in
1050         // terms of timing (as it doesn't wait for the full timing of
1051         // the trap event to complete before updating state), it's
1052         // needed to update the state as soon as possible.  This
1053         // prevents external agents from changing any specific state
1054         // that the trap need.
1055         cpu->trap(inst_fault, tid);
1056
1057         // Exit state update mode to avoid accidental updating.
1058         thread[tid]->inSyscall = false;
1059
1060         commitStatus[tid] = TrapPending;
1061
1062         // Generate trap squash event.
1063         generateTrapEvent(tid);
1064
1065         return false;
1066 #else // !FULL_SYSTEM
1067         panic("fault (%d) detected @ PC %08p", inst_fault,
1068               head_inst->PC);
1069 #endif // FULL_SYSTEM
1070     }
1071
1072     updateComInstStats(head_inst);
1073
1074     if (head_inst->traceData) {
1075         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1076         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1077         head_inst->traceData->finalize();
1078         head_inst->traceData = NULL;
1079     }
1080
1081     // Update the commit rename map
1082     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1083         renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1084                                  head_inst->renamedDestRegIdx(i));
1085     }
1086
1087     // Finally clear the head ROB entry.
1088     rob->retireHead(tid);
1089
1090     // Return true to indicate that we have committed an instruction.
1091     return true;
1092 }
1093
1094 template <class Impl>
1095 void
1096 DefaultCommit<Impl>::getInsts()
1097 {
1098     // Read any renamed instructions and place them into the ROB.
1099     int insts_to_process = min((int)renameWidth, fromRename->size);
1100
1101     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1102     {
1103         DynInstPtr inst = fromRename->insts[inst_num];
1104         int tid = inst->threadNumber;
1105
1106         if (!inst->isSquashed() &&
1107             commitStatus[tid] != ROBSquashing) {
1108             changedROBNumEntries[tid] = true;
1109
1110             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1111                     inst->readPC(), inst->seqNum, tid);
1112
1113             rob->insertInst(inst);
1114
1115             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1116
1117             youngestSeqNum[tid] = inst->seqNum;
1118         } else {
1119             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1120                     "squashed, skipping.\n",
1121                     inst->readPC(), inst->seqNum, tid);
1122         }
1123     }
1124 }
1125
1126 template <class Impl>
1127 void
1128 DefaultCommit<Impl>::markCompletedInsts()
1129 {
1130     // Grab completed insts out of the IEW instruction queue, and mark
1131     // instructions completed within the ROB.
1132     for (int inst_num = 0;
1133          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1134          ++inst_num)
1135     {
1136         if (!fromIEW->insts[inst_num]->isSquashed()) {
1137             DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1138                     "within ROB.\n",
1139                     fromIEW->insts[inst_num]->threadNumber,
1140                     fromIEW->insts[inst_num]->readPC(),
1141                     fromIEW->insts[inst_num]->seqNum);
1142
1143             // Mark the instruction as ready to commit.
1144             fromIEW->insts[inst_num]->setCanCommit();
1145         }
1146     }
1147 }
1148
1149 template <class Impl>
1150 bool
1151 DefaultCommit<Impl>::robDoneSquashing()
1152 {
1153     list<unsigned>::iterator threads = (*activeThreads).begin();
1154
1155     while (threads != (*activeThreads).end()) {
1156         unsigned tid = *threads++;
1157
1158         if (!rob->isDoneSquashing(tid))
1159             return false;
1160     }
1161
1162     return true;
1163 }
1164
1165 template <class Impl>
1166 void
1167 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1168 {
1169     unsigned thread = inst->threadNumber;
1170
1171     //
1172     //  Pick off the software prefetches
1173     //
1174 #ifdef TARGET_ALPHA
1175     if (inst->isDataPrefetch()) {
1176         statComSwp[thread]++;
1177     } else {
1178         statComInst[thread]++;
1179     }
1180 #else
1181     statComInst[thread]++;
1182 #endif
1183
1184     //
1185     //  Control Instructions
1186     //
1187     if (inst->isControl())
1188         statComBranches[thread]++;
1189
1190     //
1191     //  Memory references
1192     //
1193     if (inst->isMemRef()) {
1194         statComRefs[thread]++;
1195
1196         if (inst->isLoad()) {
1197             statComLoads[thread]++;
1198         }
1199     }
1200
1201     if (inst->isMemBarrier()) {
1202         statComMembars[thread]++;
1203     }
1204 }
1205
1206 ////////////////////////////////////////
1207 //                                    //
1208 //  SMT COMMIT POLICY MAINTAINED HERE //
1209 //                                    //
1210 ////////////////////////////////////////
1211 template <class Impl>
1212 int
1213 DefaultCommit<Impl>::getCommittingThread()
1214 {
1215     if (numThreads > 1) {
1216         switch (commitPolicy) {
1217
1218           case Aggressive:
1219             //If Policy is Aggressive, commit will call
1220             //this function multiple times per
1221             //cycle
1222             return oldestReady();
1223
1224           case RoundRobin:
1225             return roundRobin();
1226
1227           case OldestReady:
1228             return oldestReady();
1229
1230           default:
1231             return -1;
1232         }
1233     } else {
1234         int tid = (*activeThreads).front();
1235
1236         if (commitStatus[tid] == Running ||
1237             commitStatus[tid] == Idle ||
1238             commitStatus[tid] == FetchTrapPending) {
1239             return tid;
1240         } else {
1241             return -1;
1242         }
1243     }
1244 }
1245
1246 template<class Impl>
1247 int
1248 DefaultCommit<Impl>::roundRobin()
1249 {
1250     list<unsigned>::iterator pri_iter = priority_list.begin();
1251     list<unsigned>::iterator end      = priority_list.end();
1252
1253     while (pri_iter != end) {
1254         unsigned tid = *pri_iter;
1255
1256         if (commitStatus[tid] == Running ||
1257             commitStatus[tid] == Idle) {
1258
1259             if (rob->isHeadReady(tid)) {
1260                 priority_list.erase(pri_iter);
1261                 priority_list.push_back(tid);
1262
1263                 return tid;
1264             }
1265         }
1266
1267         pri_iter++;
1268     }
1269
1270     return -1;
1271 }
1272
1273 template<class Impl>
1274 int
1275 DefaultCommit<Impl>::oldestReady()
1276 {
1277     unsigned oldest = 0;
1278     bool first = true;
1279
1280     list<unsigned>::iterator threads = (*activeThreads).begin();
1281
1282     while (threads != (*activeThreads).end()) {
1283         unsigned tid = *threads++;
1284
1285         if (!rob->isEmpty(tid) &&
1286             (commitStatus[tid] == Running ||
1287              commitStatus[tid] == Idle ||
1288              commitStatus[tid] == FetchTrapPending)) {
1289
1290             if (rob->isHeadReady(tid)) {
1291
1292                 DynInstPtr head_inst = rob->readHeadInst(tid);
1293
1294                 if (first) {
1295                     oldest = tid;
1296                     first = false;
1297                 } else if (head_inst->seqNum < oldest) {
1298                     oldest = tid;
1299                 }
1300             }
1301         }
1302     }
1303
1304     if (!first) {
1305         return oldest;
1306     } else {
1307         return -1;
1308     }
1309 }