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44 #ifndef __CPU_O3_COMMIT_IMPL_HH__
45 #define __CPU_O3_COMMIT_IMPL_HH__
51 #include "arch/utility.hh"
52 #include "base/cp_annotate.hh"
53 #include "base/loader/symtab.hh"
54 #include "base/logging.hh"
55 #include "config/the_isa.hh"
56 #include "cpu/checker/cpu.hh"
57 #include "cpu/o3/commit.hh"
58 #include "cpu/o3/thread_state.hh"
59 #include "cpu/base.hh"
60 #include "cpu/exetrace.hh"
61 #include "cpu/timebuf.hh"
62 #include "debug/Activity.hh"
63 #include "debug/Commit.hh"
64 #include "debug/CommitRate.hh"
65 #include "debug/Drain.hh"
66 #include "debug/ExecFaulting.hh"
67 #include "debug/O3PipeView.hh"
68 #include "params/DerivO3CPU.hh"
69 #include "sim/faults.hh"
70 #include "sim/full_system.hh"
76 DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
78 // This will get reset by commit if it was switched out at the
79 // time of this event processing.
80 trapSquash[tid] = true;
84 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
85 : commitPolicy(params->smtCommitPolicy),
87 iewToCommitDelay(params->iewToCommitDelay),
88 commitToIEWDelay(params->commitToIEWDelay),
89 renameToROBDelay(params->renameToROBDelay),
90 fetchToCommitDelay(params->commitToFetchDelay),
91 renameWidth(params->renameWidth),
92 commitWidth(params->commitWidth),
93 numThreads(params->numThreads),
96 trapLatency(params->trapLatency),
97 canHandleInterrupts(true),
98 avoidQuiesceLiveLock(false)
100 if (commitWidth > Impl::MaxWidth)
101 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
102 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
103 commitWidth, static_cast<int>(Impl::MaxWidth));
106 _nextStatus = Inactive;
108 if (commitPolicy == CommitPolicy::RoundRobin) {
109 //Set-Up Priority List
110 for (ThreadID tid = 0; tid < numThreads; tid++) {
111 priority_list.push_back(tid);
115 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
116 commitStatus[tid] = Idle;
117 changedROBNumEntries[tid] = false;
118 trapSquash[tid] = false;
119 tcSquash[tid] = false;
120 squashAfterInst[tid] = nullptr;
122 youngestSeqNum[tid] = 0;
123 lastCommitedSeqNum[tid] = 0;
124 trapInFlight[tid] = false;
125 committedStores[tid] = false;
126 checkEmptyROB[tid] = false;
127 renameMap[tid] = nullptr;
132 template <class Impl>
134 DefaultCommit<Impl>::name() const
136 return cpu->name() + ".commit";
139 template <class Impl>
141 DefaultCommit<Impl>::regProbePoints()
143 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
144 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
145 ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
148 template <class Impl>
150 DefaultCommit<Impl>::regStats()
152 using namespace Stats;
154 .name(name() + ".commitSquashedInsts")
155 .desc("The number of squashed insts skipped by commit")
156 .prereq(commitSquashedInsts);
159 .name(name() + ".commitNonSpecStalls")
160 .desc("The number of times commit has been forced to stall to "
161 "communicate backwards")
162 .prereq(commitNonSpecStalls);
165 .name(name() + ".branchMispredicts")
166 .desc("The number of times a branch was mispredicted")
167 .prereq(branchMispredicts);
170 .init(0,commitWidth,1)
171 .name(name() + ".committed_per_cycle")
172 .desc("Number of insts commited each cycle")
177 .init(cpu->numThreads)
178 .name(name() + ".committedInsts")
179 .desc("Number of instructions committed")
184 .init(cpu->numThreads)
185 .name(name() + ".committedOps")
186 .desc("Number of ops (including micro ops) committed")
191 .init(cpu->numThreads)
192 .name(name() + ".swp_count")
193 .desc("Number of s/w prefetches committed")
198 .init(cpu->numThreads)
199 .name(name() + ".refs")
200 .desc("Number of memory references committed")
205 .init(cpu->numThreads)
206 .name(name() + ".loads")
207 .desc("Number of loads committed")
212 .init(cpu->numThreads)
213 .name(name() + ".amos")
214 .desc("Number of atomic instructions committed")
219 .init(cpu->numThreads)
220 .name(name() + ".membars")
221 .desc("Number of memory barriers committed")
226 .init(cpu->numThreads)
227 .name(name() + ".branches")
228 .desc("Number of branches committed")
233 .init(cpu->numThreads)
234 .name(name() + ".fp_insts")
235 .desc("Number of committed floating point instructions.")
240 .init(cpu->numThreads)
241 .name(name() + ".vec_insts")
242 .desc("Number of committed Vector instructions.")
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
260 statCommittedInstType
261 .init(numThreads,Enums::Num_OpClass)
262 .name(name() + ".op_class")
263 .desc("Class of committed instruction")
264 .flags(total | pdf | dist)
266 statCommittedInstType.ysubnames(Enums::OpClassStrings);
268 commitEligibleSamples
269 .name(name() + ".bw_lim_events")
270 .desc("number cycles where commit BW limit reached")
274 template <class Impl>
276 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
281 template <class Impl>
283 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
287 // Setup wire to send information back to IEW.
288 toIEW = timeBuffer->getWire(0);
290 // Setup wire to read data from IEW (for the ROB).
291 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
294 template <class Impl>
296 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
300 // Setup wire to get instructions from rename (for the ROB).
301 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
304 template <class Impl>
306 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
308 renameQueue = rq_ptr;
310 // Setup wire to get instructions from rename (for the ROB).
311 fromRename = renameQueue->getWire(-renameToROBDelay);
314 template <class Impl>
316 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
320 // Setup wire to get instructions from IEW.
321 fromIEW = iewQueue->getWire(-iewToCommitDelay);
324 template <class Impl>
326 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
328 iewStage = iew_stage;
333 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
335 activeThreads = at_ptr;
338 template <class Impl>
340 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
342 for (ThreadID tid = 0; tid < numThreads; tid++)
343 renameMap[tid] = &rm_ptr[tid];
346 template <class Impl>
348 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
353 template <class Impl>
355 DefaultCommit<Impl>::startupStage()
357 rob->setActiveThreads(activeThreads);
360 // Broadcast the number of free entries.
361 for (ThreadID tid = 0; tid < numThreads; tid++) {
362 toIEW->commitInfo[tid].usedROB = true;
363 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
364 toIEW->commitInfo[tid].emptyROB = true;
367 // Commit must broadcast the number of free entries it has at the
368 // start of the simulation, so it starts as active.
369 cpu->activateStage(O3CPU::CommitIdx);
371 cpu->activityThisCycle();
374 template <class Impl>
376 DefaultCommit<Impl>::clearStates(ThreadID tid)
378 commitStatus[tid] = Idle;
379 changedROBNumEntries[tid] = false;
380 checkEmptyROB[tid] = false;
381 trapInFlight[tid] = false;
382 committedStores[tid] = false;
383 trapSquash[tid] = false;
384 tcSquash[tid] = false;
386 lastCommitedSeqNum[tid] = 0;
387 squashAfterInst[tid] = NULL;
390 template <class Impl>
392 DefaultCommit<Impl>::drain()
397 template <class Impl>
399 DefaultCommit<Impl>::drainResume()
401 drainPending = false;
402 drainImminent = false;
405 template <class Impl>
407 DefaultCommit<Impl>::drainSanityCheck() const
410 rob->drainSanityCheck();
413 template <class Impl>
415 DefaultCommit<Impl>::isDrained() const
417 /* Make sure no one is executing microcode. There are two reasons
419 * - Hardware virtualized CPUs can't switch into the middle of a
420 * microcode sequence.
421 * - The current fetch implementation will most likely get very
422 * confused if it tries to start fetching an instruction that
423 * is executing in the middle of a ucode sequence that changes
424 * address mappings. This can happen on for example x86.
426 for (ThreadID tid = 0; tid < numThreads; tid++) {
427 if (pc[tid].microPC() != 0)
431 /* Make sure that all instructions have finished committing before
432 * declaring the system as drained. We want the pipeline to be
433 * completely empty when we declare the CPU to be drained. This
434 * makes debugging easier since CPU handover and restoring from a
435 * checkpoint with a different CPU should have the same timing.
437 return rob->isEmpty() &&
438 interrupt == NoFault;
441 template <class Impl>
443 DefaultCommit<Impl>::takeOverFrom()
446 _nextStatus = Inactive;
447 for (ThreadID tid = 0; tid < numThreads; tid++) {
448 commitStatus[tid] = Idle;
449 changedROBNumEntries[tid] = false;
450 trapSquash[tid] = false;
451 tcSquash[tid] = false;
452 squashAfterInst[tid] = NULL;
457 template <class Impl>
459 DefaultCommit<Impl>::deactivateThread(ThreadID tid)
461 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
462 priority_list.end(), tid);
464 if (thread_it != priority_list.end()) {
465 priority_list.erase(thread_it);
470 template <class Impl>
472 DefaultCommit<Impl>::updateStatus()
474 // reset ROB changed variable
475 list<ThreadID>::iterator threads = activeThreads->begin();
476 list<ThreadID>::iterator end = activeThreads->end();
478 while (threads != end) {
479 ThreadID tid = *threads++;
481 changedROBNumEntries[tid] = false;
483 // Also check if any of the threads has a trap pending
484 if (commitStatus[tid] == TrapPending ||
485 commitStatus[tid] == FetchTrapPending) {
486 _nextStatus = Active;
490 if (_nextStatus == Inactive && _status == Active) {
491 DPRINTF(Activity, "Deactivating stage.\n");
492 cpu->deactivateStage(O3CPU::CommitIdx);
493 } else if (_nextStatus == Active && _status == Inactive) {
494 DPRINTF(Activity, "Activating stage.\n");
495 cpu->activateStage(O3CPU::CommitIdx);
498 _status = _nextStatus;
501 template <class Impl>
503 DefaultCommit<Impl>::changedROBEntries()
505 list<ThreadID>::iterator threads = activeThreads->begin();
506 list<ThreadID>::iterator end = activeThreads->end();
508 while (threads != end) {
509 ThreadID tid = *threads++;
511 if (changedROBNumEntries[tid]) {
519 template <class Impl>
521 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
523 return rob->numFreeEntries(tid);
526 template <class Impl>
528 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
530 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
532 EventFunctionWrapper *trap = new EventFunctionWrapper(
533 [this, tid]{ processTrapEvent(tid); },
534 "Trap", true, Event::CPU_Tick_Pri);
536 Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
537 cpu->syscallRetryLatency : trapLatency;
539 cpu->schedule(trap, cpu->clockEdge(latency));
540 trapInFlight[tid] = true;
541 thread[tid]->trapPending = true;
544 template <class Impl>
546 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
548 assert(!trapInFlight[tid]);
549 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
551 tcSquash[tid] = true;
554 template <class Impl>
556 DefaultCommit<Impl>::squashAll(ThreadID tid)
558 // If we want to include the squashing instruction in the squash,
559 // then use one older sequence number.
560 // Hopefully this doesn't mess things up. Basically I want to squash
561 // all instructions of this thread.
562 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
563 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
565 // All younger instructions will be squashed. Set the sequence
566 // number as the youngest instruction in the ROB (0 in this case.
567 // Hopefully nothing breaks.)
568 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
570 rob->squash(squashed_inst, tid);
571 changedROBNumEntries[tid] = true;
573 // Send back the sequence number of the squashed instruction.
574 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
576 // Send back the squash signal to tell stages that they should
578 toIEW->commitInfo[tid].squash = true;
580 // Send back the rob squashing signal so other stages know that
581 // the ROB is in the process of squashing.
582 toIEW->commitInfo[tid].robSquashing = true;
584 toIEW->commitInfo[tid].mispredictInst = NULL;
585 toIEW->commitInfo[tid].squashInst = NULL;
587 toIEW->commitInfo[tid].pc = pc[tid];
590 template <class Impl>
592 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
596 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
598 thread[tid]->trapPending = false;
599 thread[tid]->noSquashFromTC = false;
600 trapInFlight[tid] = false;
602 trapSquash[tid] = false;
604 commitStatus[tid] = ROBSquashing;
605 cpu->activityThisCycle();
608 template <class Impl>
610 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
614 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
616 thread[tid]->noSquashFromTC = false;
617 assert(!thread[tid]->trapPending);
619 commitStatus[tid] = ROBSquashing;
620 cpu->activityThisCycle();
622 tcSquash[tid] = false;
625 template <class Impl>
627 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
629 DPRINTF(Commit, "Squashing after squash after request, "
630 "restarting at PC %s\n", pc[tid]);
633 // Make sure to inform the fetch stage of which instruction caused
634 // the squash. It'll try to re-fetch an instruction executing in
635 // microcode unless this is set.
636 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
637 squashAfterInst[tid] = NULL;
639 commitStatus[tid] = ROBSquashing;
640 cpu->activityThisCycle();
643 template <class Impl>
645 DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst)
647 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n",
648 tid, head_inst->seqNum);
650 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
651 commitStatus[tid] = SquashAfterPending;
652 squashAfterInst[tid] = head_inst;
655 template <class Impl>
657 DefaultCommit<Impl>::tick()
659 wroteToTimeBuffer = false;
660 _nextStatus = Inactive;
662 if (activeThreads->empty())
665 list<ThreadID>::iterator threads = activeThreads->begin();
666 list<ThreadID>::iterator end = activeThreads->end();
668 // Check if any of the threads are done squashing. Change the
669 // status if they are done.
670 while (threads != end) {
671 ThreadID tid = *threads++;
673 // Clear the bit saying if the thread has committed stores
675 committedStores[tid] = false;
677 if (commitStatus[tid] == ROBSquashing) {
679 if (rob->isDoneSquashing(tid)) {
680 commitStatus[tid] = Running;
682 DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any"
683 " insts this cycle.\n", tid);
685 toIEW->commitInfo[tid].robSquashing = true;
686 wroteToTimeBuffer = true;
693 markCompletedInsts();
695 threads = activeThreads->begin();
697 while (threads != end) {
698 ThreadID tid = *threads++;
700 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
701 // The ROB has more instructions it can commit. Its next status
703 _nextStatus = Active;
705 const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
707 DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
708 " ROB and ready to commit\n",
709 tid, inst->seqNum, inst->pcState());
711 } else if (!rob->isEmpty(tid)) {
712 const DynInstPtr &inst = rob->readHeadInst(tid);
714 ppCommitStall->notify(inst);
716 DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%llu] PC "
717 "%s is head of ROB and not ready\n",
718 tid, inst->seqNum, inst->pcState());
721 DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
722 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
726 if (wroteToTimeBuffer) {
727 DPRINTF(Activity, "Activity This Cycle.\n");
728 cpu->activityThisCycle();
734 template <class Impl>
736 DefaultCommit<Impl>::handleInterrupt()
738 // Verify that we still have an interrupt to handle
739 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
740 DPRINTF(Commit, "Pending interrupt is cleared by master before "
741 "it got handled. Restart fetching from the orig path.\n");
742 toIEW->commitInfo[0].clearInterrupt = true;
744 avoidQuiesceLiveLock = true;
748 // Wait until all in flight instructions are finished before enterring
750 if (canHandleInterrupts && cpu->instList.empty()) {
751 // Squash or record that I need to squash this cycle if
752 // an interrupt needed to be handled.
753 DPRINTF(Commit, "Interrupt detected.\n");
755 // Clear the interrupt now that it's going to be handled
756 toIEW->commitInfo[0].clearInterrupt = true;
758 assert(!thread[0]->noSquashFromTC);
759 thread[0]->noSquashFromTC = true;
762 cpu->checker->handlePendingInt();
765 // CPU will handle interrupt. Note that we ignore the local copy of
766 // interrupt. This is because the local copy may no longer be the
767 // interrupt that the interrupt controller thinks is being handled.
768 cpu->processInterrupts(cpu->getInterrupts());
770 thread[0]->noSquashFromTC = false;
772 commitStatus[0] = TrapPending;
776 // Generate trap squash event.
777 generateTrapEvent(0, interrupt);
779 avoidQuiesceLiveLock = false;
781 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
782 "flight, ROB is %sempty\n",
783 canHandleInterrupts ? "not " : "",
784 cpu->instList.empty() ? "" : "not " );
788 template <class Impl>
790 DefaultCommit<Impl>::propagateInterrupt()
792 // Don't propagate intterupts if we are currently handling a trap or
793 // in draining and the last observable instruction has been committed.
794 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
795 tcSquash[0] || drainImminent)
798 // Process interrupts if interrupts are enabled, not in PAL
799 // mode, and no other traps or external squashes are currently
801 // @todo: Allow other threads to handle interrupts.
803 // Get any interrupt that happened
804 interrupt = cpu->getInterrupts();
806 // Tell fetch that there is an interrupt pending. This
807 // will make fetch wait until it sees a non PAL-mode PC,
808 // at which point it stops fetching instructions.
809 if (interrupt != NoFault)
810 toIEW->commitInfo[0].interruptPending = true;
813 template <class Impl>
815 DefaultCommit<Impl>::commit()
818 // Check if we have a interrupt and get read to handle it
819 if (cpu->checkInterrupts(cpu->tcBase(0)))
820 propagateInterrupt();
823 ////////////////////////////////////
824 // Check for any possible squashes, handle them first
825 ////////////////////////////////////
826 list<ThreadID>::iterator threads = activeThreads->begin();
827 list<ThreadID>::iterator end = activeThreads->end();
829 int num_squashing_threads = 0;
831 while (threads != end) {
832 ThreadID tid = *threads++;
834 // Not sure which one takes priority. I think if we have
835 // both, that's a bad sign.
836 if (trapSquash[tid]) {
837 assert(!tcSquash[tid]);
840 // If the thread is trying to exit (i.e., an exit syscall was
841 // executed), this trapSquash was originated by the exit
842 // syscall earlier. In this case, schedule an exit event in
843 // the next cycle to fully terminate this thread
844 if (cpu->isThreadExiting(tid))
845 cpu->scheduleThreadExitEvent(tid);
846 } else if (tcSquash[tid]) {
847 assert(commitStatus[tid] != TrapPending);
849 } else if (commitStatus[tid] == SquashAfterPending) {
850 // A squash from the previous cycle of the commit stage (i.e.,
851 // commitInsts() called squashAfter) is pending. Squash the
853 squashFromSquashAfter(tid);
856 // Squashed sequence number must be older than youngest valid
857 // instruction in the ROB. This prevents squashes from younger
858 // instructions overriding squashes from older instructions.
859 if (fromIEW->squash[tid] &&
860 commitStatus[tid] != TrapPending &&
861 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
863 if (fromIEW->mispredictInst[tid]) {
865 "[tid:%i] Squashing due to branch mispred "
866 "PC:%#x [sn:%llu]\n",
868 fromIEW->mispredictInst[tid]->instAddr(),
869 fromIEW->squashedSeqNum[tid]);
872 "[tid:%i] Squashing due to order violation [sn:%llu]\n",
873 tid, fromIEW->squashedSeqNum[tid]);
876 DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n",
878 fromIEW->pc[tid].nextInstAddr());
880 commitStatus[tid] = ROBSquashing;
882 // If we want to include the squashing instruction in the squash,
883 // then use one older sequence number.
884 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
886 if (fromIEW->includeSquashInst[tid]) {
890 // All younger instructions will be squashed. Set the sequence
891 // number as the youngest instruction in the ROB.
892 youngestSeqNum[tid] = squashed_inst;
894 rob->squash(squashed_inst, tid);
895 changedROBNumEntries[tid] = true;
897 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
899 toIEW->commitInfo[tid].squash = true;
901 // Send back the rob squashing signal so other stages know that
902 // the ROB is in the process of squashing.
903 toIEW->commitInfo[tid].robSquashing = true;
905 toIEW->commitInfo[tid].mispredictInst =
906 fromIEW->mispredictInst[tid];
907 toIEW->commitInfo[tid].branchTaken =
908 fromIEW->branchTaken[tid];
909 toIEW->commitInfo[tid].squashInst =
910 rob->findInst(tid, squashed_inst);
911 if (toIEW->commitInfo[tid].mispredictInst) {
912 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
913 toIEW->commitInfo[tid].branchTaken = true;
918 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
921 if (commitStatus[tid] == ROBSquashing) {
922 num_squashing_threads++;
926 // If commit is currently squashing, then it will have activity for the
927 // next cycle. Set its next status as active.
928 if (num_squashing_threads) {
929 _nextStatus = Active;
932 if (num_squashing_threads != numThreads) {
933 // If we're not currently squashing, then get instructions.
936 // Try to commit any instructions.
940 //Check for any activity
941 threads = activeThreads->begin();
943 while (threads != end) {
944 ThreadID tid = *threads++;
946 if (changedROBNumEntries[tid]) {
947 toIEW->commitInfo[tid].usedROB = true;
948 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
950 wroteToTimeBuffer = true;
951 changedROBNumEntries[tid] = false;
952 if (rob->isEmpty(tid))
953 checkEmptyROB[tid] = true;
956 // ROB is only considered "empty" for previous stages if: a)
957 // ROB is empty, b) there are no outstanding stores, c) IEW
958 // stage has received any information regarding stores that
960 // c) is checked by making sure to not consider the ROB empty
961 // on the same cycle as when stores have been committed.
962 // @todo: Make this handle multi-cycle communication between
964 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
965 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
966 checkEmptyROB[tid] = false;
967 toIEW->commitInfo[tid].usedROB = true;
968 toIEW->commitInfo[tid].emptyROB = true;
969 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
970 wroteToTimeBuffer = true;
976 template <class Impl>
978 DefaultCommit<Impl>::commitInsts()
980 ////////////////////////////////////
982 // Note that commit will be handled prior to putting new
983 // instructions in the ROB so that the ROB only tries to commit
984 // instructions it has in this current cycle, and not instructions
985 // it is writing in during this cycle. Can't commit and squash
986 // things at the same time...
987 ////////////////////////////////////
989 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
991 unsigned num_committed = 0;
993 DynInstPtr head_inst;
995 // Commit as many instructions as possible until the commit bandwidth
996 // limit is reached, or it becomes impossible to commit any more.
997 while (num_committed < commitWidth) {
998 // Check for any interrupt that we've already squashed for
999 // and start processing it.
1000 if (interrupt != NoFault)
1003 ThreadID commit_thread = getCommittingThread();
1005 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1008 head_inst = rob->readHeadInst(commit_thread);
1010 ThreadID tid = head_inst->threadNumber;
1012 assert(tid == commit_thread);
1015 "Trying to commit head instruction, [tid:%i] [sn:%llu]\n",
1016 tid, head_inst->seqNum);
1018 // If the head instruction is squashed, it is ready to retire
1019 // (be removed from the ROB) at any time.
1020 if (head_inst->isSquashed()) {
1022 DPRINTF(Commit, "Retiring squashed instruction from "
1025 rob->retireHead(commit_thread);
1027 ++commitSquashedInsts;
1028 // Notify potential listeners that this instruction is squashed
1029 ppSquash->notify(head_inst);
1031 // Record that the number of ROB entries has changed.
1032 changedROBNumEntries[tid] = true;
1034 pc[tid] = head_inst->pcState();
1036 // Increment the total number of non-speculative instructions
1038 // Hack for now: it really shouldn't happen until after the
1039 // commit is deemed to be successful, but this count is needed
1041 thread[tid]->funcExeInst++;
1043 // Try to commit the head instruction.
1044 bool commit_success = commitHead(head_inst, num_committed);
1046 if (commit_success) {
1048 statCommittedInstType[tid][head_inst->opClass()]++;
1049 ppCommit->notify(head_inst);
1051 changedROBNumEntries[tid] = true;
1053 // Set the doneSeqNum to the youngest committed instruction.
1054 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1057 canHandleInterrupts = !head_inst->isDelayedCommit();
1059 // at this point store conditionals should either have
1060 // been completed or predicated false
1061 assert(!head_inst->isStoreConditional() ||
1062 head_inst->isCompleted() ||
1063 !head_inst->readPredicate());
1065 // Updates misc. registers.
1066 head_inst->updateMiscRegs();
1068 // Check instruction execution if it successfully commits and
1069 // is not carrying a fault.
1071 cpu->checker->verify(head_inst);
1074 cpu->traceFunctions(pc[tid].instAddr());
1076 TheISA::advancePC(pc[tid], head_inst->staticInst);
1078 // Keep track of the last sequence number commited
1079 lastCommitedSeqNum[tid] = head_inst->seqNum;
1081 // If this is an instruction that doesn't play nicely with
1082 // others squash everything and restart fetch
1083 if (head_inst->isSquashAfter())
1084 squashAfter(tid, head_inst);
1087 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1088 !thread[tid]->trapPending) {
1089 // Last architectually committed instruction.
1090 // Squash the pipeline, stall fetch, and use
1091 // drainImminent to disable interrupts
1092 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1093 squashAfter(tid, head_inst);
1094 cpu->commitDrained(tid);
1095 drainImminent = true;
1099 bool onInstBoundary = !head_inst->isMicroop() ||
1100 head_inst->isLastMicroop() ||
1101 !head_inst->isDelayedCommit();
1103 if (onInstBoundary) {
1106 // Make sure we're not currently updating state while
1107 // handling PC events.
1108 assert(!thread[tid]->noSquashFromTC &&
1109 !thread[tid]->trapPending);
1111 oldpc = pc[tid].instAddr();
1112 thread[tid]->pcEventQueue.service(
1113 oldpc, thread[tid]->getTC());
1115 } while (oldpc != pc[tid].instAddr());
1118 "PC skip function event, stopping commit\n");
1123 // Check if an instruction just enabled interrupts and we've
1124 // previously had an interrupt pending that was not handled
1125 // because interrupts were subsequently disabled before the
1126 // pipeline reached a place to handle the interrupt. In that
1127 // case squash now to make sure the interrupt is handled.
1129 // If we don't do this, we might end up in a live lock situation
1130 if (!interrupt && avoidQuiesceLiveLock &&
1131 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1132 squashAfter(tid, head_inst);
1134 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1135 "[tid:%i] [sn:%llu].\n",
1136 head_inst->pcState(), tid ,head_inst->seqNum);
1142 DPRINTF(CommitRate, "%i\n", num_committed);
1143 numCommittedDist.sample(num_committed);
1145 if (num_committed == commitWidth) {
1146 commitEligibleSamples++;
1150 template <class Impl>
1152 DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
1156 ThreadID tid = head_inst->threadNumber;
1158 // If the instruction is not executed yet, then it will need extra
1159 // handling. Signal backwards that it should be executed.
1160 if (!head_inst->isExecuted()) {
1161 // Keep this number correct. We have not yet actually executed
1162 // and committed this instruction.
1163 thread[tid]->funcExeInst--;
1165 // Make sure we are only trying to commit un-executed instructions we
1166 // think are possible.
1167 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1168 || head_inst->isMemBarrier() || head_inst->isWriteBarrier()
1169 || head_inst->isAtomic()
1170 || (head_inst->isLoad() && head_inst->strictlyOrdered()));
1173 "Encountered a barrier or non-speculative "
1174 "instruction [tid:%i] [sn:%llu] "
1175 "at the head of the ROB, PC %s.\n",
1176 tid, head_inst->seqNum, head_inst->pcState());
1178 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1180 "[tid:%i] [sn:%llu] "
1181 "Waiting for all stores to writeback.\n",
1182 tid, head_inst->seqNum);
1186 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1188 // Change the instruction so it won't try to commit again until
1190 head_inst->clearCanCommit();
1192 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1193 DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1194 "Strictly ordered load, PC %s.\n",
1195 tid, head_inst->seqNum, head_inst->pcState());
1196 toIEW->commitInfo[tid].strictlyOrdered = true;
1197 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1199 ++commitNonSpecStalls;
1205 if (head_inst->isThreadSync()) {
1206 // Not handled for now.
1207 panic("Thread sync instructions are not handled yet.\n");
1210 // Check if the instruction caused a fault. If so, trap.
1211 Fault inst_fault = head_inst->getFault();
1213 // Stores mark themselves as completed.
1214 if (!head_inst->isStore() && inst_fault == NoFault) {
1215 head_inst->setCompleted();
1218 if (inst_fault != NoFault) {
1219 DPRINTF(Commit, "Inst [tid:%i] [sn:%llu] PC %s has a fault\n",
1220 tid, head_inst->seqNum, head_inst->pcState());
1222 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1224 "[tid:%i] [sn:%llu] "
1225 "Stores outstanding, fault must wait.\n",
1226 tid, head_inst->seqNum);
1230 head_inst->setCompleted();
1232 // If instruction has faulted, let the checker execute it and
1233 // check if it sees the same fault and control flow.
1235 // Need to check the instruction before its fault is processed
1236 cpu->checker->verify(head_inst);
1239 assert(!thread[tid]->noSquashFromTC);
1241 // Mark that we're in state update mode so that the trap's
1242 // execution doesn't generate extra squashes.
1243 thread[tid]->noSquashFromTC = true;
1245 // Execute the trap. Although it's slightly unrealistic in
1246 // terms of timing (as it doesn't wait for the full timing of
1247 // the trap event to complete before updating state), it's
1248 // needed to update the state as soon as possible. This
1249 // prevents external agents from changing any specific state
1250 // that the trap need.
1251 cpu->trap(inst_fault, tid,
1252 head_inst->notAnInst() ?
1253 StaticInst::nullStaticInstPtr :
1254 head_inst->staticInst);
1256 // Exit state update mode to avoid accidental updating.
1257 thread[tid]->noSquashFromTC = false;
1259 commitStatus[tid] = TrapPending;
1262 "[tid:%i] [sn:%llu] Committing instruction with fault\n",
1263 tid, head_inst->seqNum);
1264 if (head_inst->traceData) {
1265 if (DTRACE(ExecFaulting)) {
1266 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1267 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1268 head_inst->traceData->dump();
1270 delete head_inst->traceData;
1271 head_inst->traceData = NULL;
1274 // Generate trap squash event.
1275 generateTrapEvent(tid, inst_fault);
1279 updateComInstStats(head_inst);
1282 if (thread[tid]->profile) {
1283 thread[tid]->profilePC = head_inst->instAddr();
1284 ProfileNode *node = thread[tid]->profile->consume(
1285 thread[tid]->getTC(), head_inst->staticInst);
1288 thread[tid]->profileNode = node;
1290 if (CPA::available()) {
1291 if (head_inst->isControl()) {
1292 ThreadContext *tc = thread[tid]->getTC();
1293 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1298 "[tid:%i] [sn:%llu] Committing instruction with PC %s\n",
1299 tid, head_inst->seqNum, head_inst->pcState());
1300 if (head_inst->traceData) {
1301 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1302 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1303 head_inst->traceData->dump();
1304 delete head_inst->traceData;
1305 head_inst->traceData = NULL;
1307 if (head_inst->isReturn()) {
1309 "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n",
1310 tid, head_inst->seqNum, head_inst->pcState());
1313 // Update the commit rename map
1314 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1315 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1316 head_inst->renamedDestRegIdx(i));
1319 // Finally clear the head ROB entry.
1320 rob->retireHead(tid);
1323 if (DTRACE(O3PipeView)) {
1324 head_inst->commitTick = curTick() - head_inst->fetchTick;
1328 // If this was a store, record it for this cycle.
1329 if (head_inst->isStore() || head_inst->isAtomic())
1330 committedStores[tid] = true;
1332 // Return true to indicate that we have committed an instruction.
1336 template <class Impl>
1338 DefaultCommit<Impl>::getInsts()
1340 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1342 // Read any renamed instructions and place them into the ROB.
1343 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1345 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1346 const DynInstPtr &inst = fromRename->insts[inst_num];
1347 ThreadID tid = inst->threadNumber;
1349 if (!inst->isSquashed() &&
1350 commitStatus[tid] != ROBSquashing &&
1351 commitStatus[tid] != TrapPending) {
1352 changedROBNumEntries[tid] = true;
1354 DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n",
1355 inst->seqNum, tid, inst->pcState());
1357 rob->insertInst(inst);
1359 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1361 youngestSeqNum[tid] = inst->seqNum;
1363 DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1364 "Instruction PC %s was squashed, skipping.\n",
1365 inst->seqNum, tid, inst->pcState());
1370 template <class Impl>
1372 DefaultCommit<Impl>::markCompletedInsts()
1374 // Grab completed insts out of the IEW instruction queue, and mark
1375 // instructions completed within the ROB.
1376 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1377 assert(fromIEW->insts[inst_num]);
1378 if (!fromIEW->insts[inst_num]->isSquashed()) {
1379 DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%llu] ready "
1381 fromIEW->insts[inst_num]->threadNumber,
1382 fromIEW->insts[inst_num]->pcState(),
1383 fromIEW->insts[inst_num]->seqNum);
1385 // Mark the instruction as ready to commit.
1386 fromIEW->insts[inst_num]->setCanCommit();
1391 template <class Impl>
1393 DefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst)
1395 ThreadID tid = inst->threadNumber;
1397 if (!inst->isMicroop() || inst->isLastMicroop())
1398 instsCommitted[tid]++;
1399 opsCommitted[tid]++;
1401 // To match the old model, don't count nops and instruction
1402 // prefetches towards the total commit count.
1403 if (!inst->isNop() && !inst->isInstPrefetch()) {
1404 cpu->instDone(tid, inst);
1408 // Control Instructions
1410 if (inst->isControl())
1411 statComBranches[tid]++;
1414 // Memory references
1416 if (inst->isMemRef()) {
1419 if (inst->isLoad()) {
1420 statComLoads[tid]++;
1423 if (inst->isAtomic()) {
1428 if (inst->isMemBarrier()) {
1429 statComMembars[tid]++;
1432 // Integer Instruction
1433 if (inst->isInteger())
1434 statComInteger[tid]++;
1436 // Floating Point Instruction
1437 if (inst->isFloating())
1438 statComFloating[tid]++;
1439 // Vector Instruction
1440 if (inst->isVector())
1441 statComVector[tid]++;
1445 statComFunctionCalls[tid]++;
1449 ////////////////////////////////////////
1451 // SMT COMMIT POLICY MAINTAINED HERE //
1453 ////////////////////////////////////////
1454 template <class Impl>
1456 DefaultCommit<Impl>::getCommittingThread()
1458 if (numThreads > 1) {
1459 switch (commitPolicy) {
1461 case CommitPolicy::Aggressive:
1462 //If Policy is Aggressive, commit will call
1463 //this function multiple times per
1465 return oldestReady();
1467 case CommitPolicy::RoundRobin:
1468 return roundRobin();
1470 case CommitPolicy::OldestReady:
1471 return oldestReady();
1474 return InvalidThreadID;
1477 assert(!activeThreads->empty());
1478 ThreadID tid = activeThreads->front();
1480 if (commitStatus[tid] == Running ||
1481 commitStatus[tid] == Idle ||
1482 commitStatus[tid] == FetchTrapPending) {
1485 return InvalidThreadID;
1490 template<class Impl>
1492 DefaultCommit<Impl>::roundRobin()
1494 list<ThreadID>::iterator pri_iter = priority_list.begin();
1495 list<ThreadID>::iterator end = priority_list.end();
1497 while (pri_iter != end) {
1498 ThreadID tid = *pri_iter;
1500 if (commitStatus[tid] == Running ||
1501 commitStatus[tid] == Idle ||
1502 commitStatus[tid] == FetchTrapPending) {
1504 if (rob->isHeadReady(tid)) {
1505 priority_list.erase(pri_iter);
1506 priority_list.push_back(tid);
1515 return InvalidThreadID;
1518 template<class Impl>
1520 DefaultCommit<Impl>::oldestReady()
1522 unsigned oldest = 0;
1525 list<ThreadID>::iterator threads = activeThreads->begin();
1526 list<ThreadID>::iterator end = activeThreads->end();
1528 while (threads != end) {
1529 ThreadID tid = *threads++;
1531 if (!rob->isEmpty(tid) &&
1532 (commitStatus[tid] == Running ||
1533 commitStatus[tid] == Idle ||
1534 commitStatus[tid] == FetchTrapPending)) {
1536 if (rob->isHeadReady(tid)) {
1538 const DynInstPtr &head_inst = rob->readHeadInst(tid);
1543 } else if (head_inst->seqNum < oldest) {
1553 return InvalidThreadID;
1557 #endif//__CPU_O3_COMMIT_IMPL_HH__