src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include "config/full_system.hh"
  33 #include "config/use_checker.hh"
  34
  35 #include <algorithm>
  36 #include <string>
  37
  38 #include "arch/utility.hh"
  39 #include "base/loader/symtab.hh"
  40 #include "base/timebuf.hh"
  41 #include "cpu/exetrace.hh"
  42 #include "cpu/o3/commit.hh"
  43 #include "cpu/o3/thread_state.hh"
  44
  45 #if USE_CHECKER
  46 #include "cpu/checker/cpu.hh"
  47 #endif
  48
  49 template <class Impl>
  50 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  51                                           unsigned _tid)
  52     : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
  53 {
  54     this->setFlags(Event::AutoDelete);
  55 }
  56
  57 template <class Impl>
  58 void
  59 DefaultCommit<Impl>::TrapEvent::process()
  60 {
  61     // This will get reset by commit if it was switched out at the
  62     // time of this event processing.
  63     commit->trapSquash[tid] = true;
  64 }
  65
  66 template <class Impl>
  67 const char *
  68 DefaultCommit<Impl>::TrapEvent::description()
  69 {
  70     return "Trap event";
  71 }
  72
  73 template <class Impl>
  74 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
  75     : cpu(_cpu),
  76       squashCounter(0),
  77       iewToCommitDelay(params->iewToCommitDelay),
  78       commitToIEWDelay(params->commitToIEWDelay),
  79       renameToROBDelay(params->renameToROBDelay),
  80       fetchToCommitDelay(params->commitToFetchDelay),
  81       renameWidth(params->renameWidth),
  82       commitWidth(params->commitWidth),
  83       numThreads(params->numberOfThreads),
  84       drainPending(false),
  85       switchedOut(false),
  86       trapLatency(params->trapLatency)
  87 {
  88     _status = Active;
  89     _nextStatus = Inactive;
  90     std::string policy = params->smtCommitPolicy;
  91
  92     //Convert string to lowercase
  93     std::transform(policy.begin(), policy.end(), policy.begin(),
  94                    (int(*)(int)) tolower);
  95
  96     //Assign commit policy
  97     if (policy == "aggressive"){
  98         commitPolicy = Aggressive;
  99
 100         DPRINTF(Commit,"Commit Policy set to Aggressive.");
 101     } else if (policy == "roundrobin"){
 102         commitPolicy = RoundRobin;
 103
 104         //Set-Up Priority List
 105         for (int tid=0; tid < numThreads; tid++) {
 106             priority_list.push_back(tid);
 107         }
 108
 109         DPRINTF(Commit,"Commit Policy set to Round Robin.");
 110     } else if (policy == "oldestready"){
 111         commitPolicy = OldestReady;
 112
 113         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 114     } else {
 115         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 116                "RoundRobin,OldestReady}");
 117     }
 118
 119     for (int i=0; i < numThreads; i++) {
 120         commitStatus[i] = Idle;
 121         changedROBNumEntries[i] = false;
 122         checkEmptyROB[i] = false;
 123         trapInFlight[i] = false;
 124         committedStores[i] = false;
 125         trapSquash[i] = false;
 126         tcSquash[i] = false;
 127         PC[i] = nextPC[i] = nextNPC[i] = 0;
 128     }
 129 #if FULL_SYSTEM
 130     interrupt = NoFault;
 131 #endif
 132 }
 133
 134 template <class Impl>
 135 std::string
 136 DefaultCommit<Impl>::name() const
 137 {
 138     return cpu->name() + ".commit";
 139 }
 140
 141 template <class Impl>
 142 void
 143 DefaultCommit<Impl>::regStats()
 144 {
 145     using namespace Stats;
 146     commitCommittedInsts
 147         .name(name() + ".commitCommittedInsts")
 148         .desc("The number of committed instructions")
 149         .prereq(commitCommittedInsts);
 150     commitSquashedInsts
 151         .name(name() + ".commitSquashedInsts")
 152         .desc("The number of squashed insts skipped by commit")
 153         .prereq(commitSquashedInsts);
 154     commitSquashEvents
 155         .name(name() + ".commitSquashEvents")
 156         .desc("The number of times commit is told to squash")
 157         .prereq(commitSquashEvents);
 158     commitNonSpecStalls
 159         .name(name() + ".commitNonSpecStalls")
 160         .desc("The number of times commit has been forced to stall to "
 161               "communicate backwards")
 162         .prereq(commitNonSpecStalls);
 163     branchMispredicts
 164         .name(name() + ".branchMispredicts")
 165         .desc("The number of times a branch was mispredicted")
 166         .prereq(branchMispredicts);
 167     numCommittedDist
 168         .init(0,commitWidth,1)
 169         .name(name() + ".COM:committed_per_cycle")
 170         .desc("Number of insts commited each cycle")
 171         .flags(Stats::pdf)
 172         ;
 173
 174     statComInst
 175         .init(cpu->number_of_threads)
 176         .name(name() + ".COM:count")
 177         .desc("Number of instructions committed")
 178         .flags(total)
 179         ;
 180
 181     statComSwp
 182         .init(cpu->number_of_threads)
 183         .name(name() + ".COM:swp_count")
 184         .desc("Number of s/w prefetches committed")
 185         .flags(total)
 186         ;
 187
 188     statComRefs
 189         .init(cpu->number_of_threads)
 190         .name(name() +  ".COM:refs")
 191         .desc("Number of memory references committed")
 192         .flags(total)
 193         ;
 194
 195     statComLoads
 196         .init(cpu->number_of_threads)
 197         .name(name() +  ".COM:loads")
 198         .desc("Number of loads committed")
 199         .flags(total)
 200         ;
 201
 202     statComMembars
 203         .init(cpu->number_of_threads)
 204         .name(name() +  ".COM:membars")
 205         .desc("Number of memory barriers committed")
 206         .flags(total)
 207         ;
 208
 209     statComBranches
 210         .init(cpu->number_of_threads)
 211         .name(name() + ".COM:branches")
 212         .desc("Number of branches committed")
 213         .flags(total)
 214         ;
 215
 216     commitEligible
 217         .init(cpu->number_of_threads)
 218         .name(name() + ".COM:bw_limited")
 219         .desc("number of insts not committed due to BW limits")
 220         .flags(total)
 221         ;
 222
 223     commitEligibleSamples
 224         .name(name() + ".COM:bw_lim_events")
 225         .desc("number cycles where commit BW limit reached")
 226         ;
 227 }
 228
 229 template <class Impl>
 230 void
 231 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 232 {
 233     thread = threads;
 234 }
 235
 236 template <class Impl>
 237 void
 238 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 239 {
 240     timeBuffer = tb_ptr;
 241
 242     // Setup wire to send information back to IEW.
 243     toIEW = timeBuffer->getWire(0);
 244
 245     // Setup wire to read data from IEW (for the ROB).
 246     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 247 }
 248
 249 template <class Impl>
 250 void
 251 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 252 {
 253     fetchQueue = fq_ptr;
 254
 255     // Setup wire to get instructions from rename (for the ROB).
 256     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 257 }
 258
 259 template <class Impl>
 260 void
 261 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 262 {
 263     renameQueue = rq_ptr;
 264
 265     // Setup wire to get instructions from rename (for the ROB).
 266     fromRename = renameQueue->getWire(-renameToROBDelay);
 267 }
 268
 269 template <class Impl>
 270 void
 271 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 272 {
 273     iewQueue = iq_ptr;
 274
 275     // Setup wire to get instructions from IEW.
 276     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 277 }
 278
 279 template <class Impl>
 280 void
 281 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 282 {
 283     iewStage = iew_stage;
 284 }
 285
 286 template<class Impl>
 287 void
 288 DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 289 {
 290     activeThreads = at_ptr;
 291 }
 292
 293 template <class Impl>
 294 void
 295 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 296 {
 297     for (int i=0; i < numThreads; i++) {
 298         renameMap[i] = &rm_ptr[i];
 299     }
 300 }
 301
 302 template <class Impl>
 303 void
 304 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 305 {
 306     rob = rob_ptr;
 307 }
 308
 309 template <class Impl>
 310 void
 311 DefaultCommit<Impl>::initStage()
 312 {
 313     rob->setActiveThreads(activeThreads);
 314     rob->resetEntries();
 315
 316     // Broadcast the number of free entries.
 317     for (int i=0; i < numThreads; i++) {
 318         toIEW->commitInfo[i].usedROB = true;
 319         toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
 320         toIEW->commitInfo[i].emptyROB = true;
 321     }
 322
 323     // Commit must broadcast the number of free entries it has at the
 324     // start of the simulation, so it starts as active.
 325     cpu->activateStage(O3CPU::CommitIdx);
 326
 327     cpu->activityThisCycle();
 328     trapLatency = cpu->cycles(trapLatency);
 329 }
 330
 331 template <class Impl>
 332 bool
 333 DefaultCommit<Impl>::drain()
 334 {
 335     drainPending = true;
 336
 337     return false;
 338 }
 339
 340 template <class Impl>
 341 void
 342 DefaultCommit<Impl>::switchOut()
 343 {
 344     switchedOut = true;
 345     drainPending = false;
 346     rob->switchOut();
 347 }
 348
 349 template <class Impl>
 350 void
 351 DefaultCommit<Impl>::resume()
 352 {
 353     drainPending = false;
 354 }
 355
 356 template <class Impl>
 357 void
 358 DefaultCommit<Impl>::takeOverFrom()
 359 {
 360     switchedOut = false;
 361     _status = Active;
 362     _nextStatus = Inactive;
 363     for (int i=0; i < numThreads; i++) {
 364         commitStatus[i] = Idle;
 365         changedROBNumEntries[i] = false;
 366         trapSquash[i] = false;
 367         tcSquash[i] = false;
 368     }
 369     squashCounter = 0;
 370     rob->takeOverFrom();
 371 }
 372
 373 template <class Impl>
 374 void
 375 DefaultCommit<Impl>::updateStatus()
 376 {
 377     // reset ROB changed variable
 378     std::list<unsigned>::iterator threads = activeThreads->begin();
 379     std::list<unsigned>::iterator end = activeThreads->end();
 380
 381     while (threads != end) {
 382         unsigned tid = *threads++;
 383
 384         changedROBNumEntries[tid] = false;
 385
 386         // Also check if any of the threads has a trap pending
 387         if (commitStatus[tid] == TrapPending ||
 388             commitStatus[tid] == FetchTrapPending) {
 389             _nextStatus = Active;
 390         }
 391     }
 392
 393     if (_nextStatus == Inactive && _status == Active) {
 394         DPRINTF(Activity, "Deactivating stage.\n");
 395         cpu->deactivateStage(O3CPU::CommitIdx);
 396     } else if (_nextStatus == Active && _status == Inactive) {
 397         DPRINTF(Activity, "Activating stage.\n");
 398         cpu->activateStage(O3CPU::CommitIdx);
 399     }
 400
 401     _status = _nextStatus;
 402 }
 403
 404 template <class Impl>
 405 void
 406 DefaultCommit<Impl>::setNextStatus()
 407 {
 408     int squashes = 0;
 409
 410     std::list<unsigned>::iterator threads = activeThreads->begin();
 411     std::list<unsigned>::iterator end = activeThreads->end();
 412
 413     while (threads != end) {
 414         unsigned tid = *threads++;
 415
 416         if (commitStatus[tid] == ROBSquashing) {
 417             squashes++;
 418         }
 419     }
 420
 421     squashCounter = squashes;
 422
 423     // If commit is currently squashing, then it will have activity for the
 424     // next cycle. Set its next status as active.
 425     if (squashCounter) {
 426         _nextStatus = Active;
 427     }
 428 }
 429
 430 template <class Impl>
 431 bool
 432 DefaultCommit<Impl>::changedROBEntries()
 433 {
 434     std::list<unsigned>::iterator threads = activeThreads->begin();
 435     std::list<unsigned>::iterator end = activeThreads->end();
 436
 437     while (threads != end) {
 438         unsigned tid = *threads++;
 439
 440         if (changedROBNumEntries[tid]) {
 441             return true;
 442         }
 443     }
 444
 445     return false;
 446 }
 447
 448 template <class Impl>
 449 unsigned
 450 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
 451 {
 452     return rob->numFreeEntries(tid);
 453 }
 454
 455 template <class Impl>
 456 void
 457 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
 458 {
 459     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 460
 461     TrapEvent *trap = new TrapEvent(this, tid);
 462
 463     trap->schedule(curTick + trapLatency);
 464     trapInFlight[tid] = true;
 465 }
 466
 467 template <class Impl>
 468 void
 469 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
 470 {
 471     assert(!trapInFlight[tid]);
 472     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 473
 474     tcSquash[tid] = true;
 475 }
 476
 477 template <class Impl>
 478 void
 479 DefaultCommit<Impl>::squashAll(unsigned tid)
 480 {
 481     // If we want to include the squashing instruction in the squash,
 482     // then use one older sequence number.
 483     // Hopefully this doesn't mess things up.  Basically I want to squash
 484     // all instructions of this thread.
 485     InstSeqNum squashed_inst = rob->isEmpty() ?
 486         0 : rob->readHeadInst(tid)->seqNum - 1;
 487
 488     // All younger instructions will be squashed. Set the sequence
 489     // number as the youngest instruction in the ROB (0 in this case.
 490     // Hopefully nothing breaks.)
 491     youngestSeqNum[tid] = 0;
 492
 493     rob->squash(squashed_inst, tid);
 494     changedROBNumEntries[tid] = true;
 495
 496     // Send back the sequence number of the squashed instruction.
 497     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 498
 499     // Send back the squash signal to tell stages that they should
 500     // squash.
 501     toIEW->commitInfo[tid].squash = true;
 502
 503     // Send back the rob squashing signal so other stages know that
 504     // the ROB is in the process of squashing.
 505     toIEW->commitInfo[tid].robSquashing = true;
 506
 507     toIEW->commitInfo[tid].branchMispredict = false;
 508
 509     toIEW->commitInfo[tid].nextPC = PC[tid];
 510     toIEW->commitInfo[tid].nextNPC = nextPC[tid];
 511 }
 512
 513 template <class Impl>
 514 void
 515 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
 516 {
 517     squashAll(tid);
 518
 519     DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
 520
 521     thread[tid]->trapPending = false;
 522     thread[tid]->inSyscall = false;
 523     trapInFlight[tid] = false;
 524
 525     trapSquash[tid] = false;
 526
 527     commitStatus[tid] = ROBSquashing;
 528     cpu->activityThisCycle();
 529 }
 530
 531 template <class Impl>
 532 void
 533 DefaultCommit<Impl>::squashFromTC(unsigned tid)
 534 {
 535     squashAll(tid);
 536
 537     DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
 538
 539     thread[tid]->inSyscall = false;
 540     assert(!thread[tid]->trapPending);
 541
 542     commitStatus[tid] = ROBSquashing;
 543     cpu->activityThisCycle();
 544
 545     tcSquash[tid] = false;
 546 }
 547
 548 template <class Impl>
 549 void
 550 DefaultCommit<Impl>::tick()
 551 {
 552     wroteToTimeBuffer = false;
 553     _nextStatus = Inactive;
 554
 555     if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 556         cpu->signalDrained();
 557         drainPending = false;
 558         return;
 559     }
 560
 561     if (activeThreads->empty())
 562         return;
 563
 564     std::list<unsigned>::iterator threads = activeThreads->begin();
 565     std::list<unsigned>::iterator end = activeThreads->end();
 566
 567     // Check if any of the threads are done squashing.  Change the
 568     // status if they are done.
 569     while (threads != end) {
 570         unsigned tid = *threads++;
 571
 572         // Clear the bit saying if the thread has committed stores
 573         // this cycle.
 574         committedStores[tid] = false;
 575
 576         if (commitStatus[tid] == ROBSquashing) {
 577
 578             if (rob->isDoneSquashing(tid)) {
 579                 commitStatus[tid] = Running;
 580             } else {
 581                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 582                         " insts this cycle.\n", tid);
 583                 rob->doSquash(tid);
 584                 toIEW->commitInfo[tid].robSquashing = true;
 585                 wroteToTimeBuffer = true;
 586             }
 587         }
 588     }
 589
 590     commit();
 591
 592     markCompletedInsts();
 593
 594     threads = activeThreads->begin();
 595
 596     while (threads != end) {
 597         unsigned tid = *threads++;
 598
 599         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 600             // The ROB has more instructions it can commit. Its next status
 601             // will be active.
 602             _nextStatus = Active;
 603
 604             DynInstPtr inst = rob->readHeadInst(tid);
 605
 606             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
 607                     " ROB and ready to commit\n",
 608                     tid, inst->seqNum, inst->readPC());
 609
 610         } else if (!rob->isEmpty(tid)) {
 611             DynInstPtr inst = rob->readHeadInst(tid);
 612
 613             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 614                     "%#x is head of ROB and not ready\n",
 615                     tid, inst->seqNum, inst->readPC());
 616         }
 617
 618         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 619                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 620     }
 621
 622
 623     if (wroteToTimeBuffer) {
 624         DPRINTF(Activity, "Activity This Cycle.\n");
 625         cpu->activityThisCycle();
 626     }
 627
 628     updateStatus();
 629 }
 630
 631 #if FULL_SYSTEM
 632 template <class Impl>
 633 void
 634 DefaultCommit<Impl>::handleInterrupt()
 635 {
 636     if (interrupt != NoFault) {
 637         // Wait until the ROB is empty and all stores have drained in
 638         // order to enter the interrupt.
 639         if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 640             // Squash or record that I need to squash this cycle if
 641             // an interrupt needed to be handled.
 642             DPRINTF(Commit, "Interrupt detected.\n");
 643
 644             Fault new_interrupt = cpu->getInterrupts();
 645             assert(new_interrupt != NoFault);
 646
 647             // Clear the interrupt now that it's going to be handled
 648             toIEW->commitInfo[0].clearInterrupt = true;
 649
 650             assert(!thread[0]->inSyscall);
 651             thread[0]->inSyscall = true;
 652
 653             // CPU will handle interrupt.
 654             cpu->processInterrupts(interrupt);
 655
 656             thread[0]->inSyscall = false;
 657
 658             commitStatus[0] = TrapPending;
 659
 660             // Generate trap squash event.
 661             generateTrapEvent(0);
 662
 663             interrupt = NoFault;
 664         } else {
 665             DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 666         }
 667     } else if (commitStatus[0] != TrapPending &&
 668                cpu->check_interrupts(cpu->tcBase(0)) &&
 669                !trapSquash[0] &&
 670                !tcSquash[0]) {
 671         // Process interrupts if interrupts are enabled, not in PAL
 672         // mode, and no other traps or external squashes are currently
 673         // pending.
 674         // @todo: Allow other threads to handle interrupts.
 675
 676         // Get any interrupt that happened
 677         interrupt = cpu->getInterrupts();
 678
 679         if (interrupt != NoFault) {
 680             // Tell fetch that there is an interrupt pending.  This
 681             // will make fetch wait until it sees a non PAL-mode PC,
 682             // at which point it stops fetching instructions.
 683             toIEW->commitInfo[0].interruptPending = true;
 684         }
 685     }
 686 }
 687 #endif // FULL_SYSTEM
 688
 689 template <class Impl>
 690 void
 691 DefaultCommit<Impl>::commit()
 692 {
 693
 694 #if FULL_SYSTEM
 695     // Check for any interrupt, and start processing it.  Or if we
 696     // have an outstanding interrupt and are at a point when it is
 697     // valid to take an interrupt, process it.
 698     if (cpu->check_interrupts(cpu->tcBase(0))) {
 699         handleInterrupt();
 700     }
 701 #endif // FULL_SYSTEM
 702
 703     ////////////////////////////////////
 704     // Check for any possible squashes, handle them first
 705     ////////////////////////////////////
 706     std::list<unsigned>::iterator threads = activeThreads->begin();
 707     std::list<unsigned>::iterator end = activeThreads->end();
 708
 709     while (threads != end) {
 710         unsigned tid = *threads++;
 711
 712         // Not sure which one takes priority.  I think if we have
 713         // both, that's a bad sign.
 714         if (trapSquash[tid] == true) {
 715             assert(!tcSquash[tid]);
 716             squashFromTrap(tid);
 717         } else if (tcSquash[tid] == true) {
 718             assert(commitStatus[tid] != TrapPending);
 719             squashFromTC(tid);
 720         }
 721
 722         // Squashed sequence number must be older than youngest valid
 723         // instruction in the ROB. This prevents squashes from younger
 724         // instructions overriding squashes from older instructions.
 725         if (fromIEW->squash[tid] &&
 726             commitStatus[tid] != TrapPending &&
 727             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 728
 729             DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
 730                     tid,
 731                     fromIEW->mispredPC[tid],
 732                     fromIEW->squashedSeqNum[tid]);
 733
 734             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 735                     tid,
 736                     fromIEW->nextPC[tid]);
 737
 738             commitStatus[tid] = ROBSquashing;
 739
 740             // If we want to include the squashing instruction in the squash,
 741             // then use one older sequence number.
 742             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 743
 744 #if ISA_HAS_DELAY_SLOT
 745             InstSeqNum bdelay_done_seq_num = squashed_inst;
 746             bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
 747             bool branchMispredict = fromIEW->branchMispredict[tid];
 748
 749             // Squashing/not squashing the branch delay slot only makes
 750             // sense when you're squashing from a branch, ie from a branch
 751             // mispredict.
 752             if (branchMispredict && !squash_bdelay_slot) {
 753                 bdelay_done_seq_num++;
 754             }
 755 #endif
 756
 757             if (fromIEW->includeSquashInst[tid] == true) {
 758                 squashed_inst--;
 759 #if ISA_HAS_DELAY_SLOT
 760                 bdelay_done_seq_num--;
 761 #endif
 762             }
 763
 764             // All younger instructions will be squashed. Set the sequence
 765             // number as the youngest instruction in the ROB.
 766             youngestSeqNum[tid] = squashed_inst;
 767
 768 #if ISA_HAS_DELAY_SLOT
 769             rob->squash(bdelay_done_seq_num, tid);
 770             toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
 771             toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
 772 #else
 773             rob->squash(squashed_inst, tid);
 774             toIEW->commitInfo[tid].squashDelaySlot = true;
 775 #endif
 776             changedROBNumEntries[tid] = true;
 777
 778             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 779
 780             toIEW->commitInfo[tid].squash = true;
 781
 782             // Send back the rob squashing signal so other stages know that
 783             // the ROB is in the process of squashing.
 784             toIEW->commitInfo[tid].robSquashing = true;
 785
 786             toIEW->commitInfo[tid].branchMispredict =
 787                 fromIEW->branchMispredict[tid];
 788
 789             toIEW->commitInfo[tid].branchTaken =
 790                 fromIEW->branchTaken[tid];
 791
 792             toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
 793             toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
 794
 795             toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
 796
 797             if (toIEW->commitInfo[tid].branchMispredict) {
 798                 ++branchMispredicts;
 799             }
 800         }
 801
 802     }
 803
 804     setNextStatus();
 805
 806     if (squashCounter != numThreads) {
 807         // If we're not currently squashing, then get instructions.
 808         getInsts();
 809
 810         // Try to commit any instructions.
 811         commitInsts();
 812     } else {
 813 #if ISA_HAS_DELAY_SLOT
 814         skidInsert();
 815 #endif
 816     }
 817
 818     //Check for any activity
 819     threads = activeThreads->begin();
 820
 821     while (threads != end) {
 822         unsigned tid = *threads++;
 823
 824         if (changedROBNumEntries[tid]) {
 825             toIEW->commitInfo[tid].usedROB = true;
 826             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 827
 828             wroteToTimeBuffer = true;
 829             changedROBNumEntries[tid] = false;
 830             if (rob->isEmpty(tid))
 831                 checkEmptyROB[tid] = true;
 832         }
 833
 834         // ROB is only considered "empty" for previous stages if: a)
 835         // ROB is empty, b) there are no outstanding stores, c) IEW
 836         // stage has received any information regarding stores that
 837         // committed.
 838         // c) is checked by making sure to not consider the ROB empty
 839         // on the same cycle as when stores have been committed.
 840         // @todo: Make this handle multi-cycle communication between
 841         // commit and IEW.
 842         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
 843             !iewStage->hasStoresToWB() && !committedStores[tid]) {
 844             checkEmptyROB[tid] = false;
 845             toIEW->commitInfo[tid].usedROB = true;
 846             toIEW->commitInfo[tid].emptyROB = true;
 847             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 848             wroteToTimeBuffer = true;
 849         }
 850
 851     }
 852 }
 853
 854 template <class Impl>
 855 void
 856 DefaultCommit<Impl>::commitInsts()
 857 {
 858     ////////////////////////////////////
 859     // Handle commit
 860     // Note that commit will be handled prior to putting new
 861     // instructions in the ROB so that the ROB only tries to commit
 862     // instructions it has in this current cycle, and not instructions
 863     // it is writing in during this cycle.  Can't commit and squash
 864     // things at the same time...
 865     ////////////////////////////////////
 866
 867     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 868
 869     unsigned num_committed = 0;
 870
 871     DynInstPtr head_inst;
 872
 873     // Commit as many instructions as possible until the commit bandwidth
 874     // limit is reached, or it becomes impossible to commit any more.
 875     while (num_committed < commitWidth) {
 876         int commit_thread = getCommittingThread();
 877
 878         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 879             break;
 880
 881         head_inst = rob->readHeadInst(commit_thread);
 882
 883         int tid = head_inst->threadNumber;
 884
 885         assert(tid == commit_thread);
 886
 887         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 888                 head_inst->seqNum, tid);
 889
 890         // If the head instruction is squashed, it is ready to retire
 891         // (be removed from the ROB) at any time.
 892         if (head_inst->isSquashed()) {
 893
 894             DPRINTF(Commit, "Retiring squashed instruction from "
 895                     "ROB.\n");
 896
 897             rob->retireHead(commit_thread);
 898
 899             ++commitSquashedInsts;
 900
 901             // Record that the number of ROB entries has changed.
 902             changedROBNumEntries[tid] = true;
 903         } else {
 904             PC[tid] = head_inst->readPC();
 905             nextPC[tid] = head_inst->readNextPC();
 906             nextNPC[tid] = head_inst->readNextNPC();
 907
 908             // Increment the total number of non-speculative instructions
 909             // executed.
 910             // Hack for now: it really shouldn't happen until after the
 911             // commit is deemed to be successful, but this count is needed
 912             // for syscalls.
 913             thread[tid]->funcExeInst++;
 914
 915             // Try to commit the head instruction.
 916             bool commit_success = commitHead(head_inst, num_committed);
 917
 918             if (commit_success) {
 919                 ++num_committed;
 920
 921                 changedROBNumEntries[tid] = true;
 922
 923                 // Set the doneSeqNum to the youngest committed instruction.
 924                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 925
 926                 ++commitCommittedInsts;
 927
 928                 // To match the old model, don't count nops and instruction
 929                 // prefetches towards the total commit count.
 930                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 931                     cpu->instDone(tid);
 932                 }
 933
 934                 PC[tid] = nextPC[tid];
 935 #if ISA_HAS_DELAY_SLOT
 936                 nextPC[tid] = nextNPC[tid];
 937                 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
 938 #else
 939                 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
 940 #endif
 941
 942 #if FULL_SYSTEM
 943                 int count = 0;
 944                 Addr oldpc;
 945                 do {
 946                     // Debug statement.  Checks to make sure we're not
 947                     // currently updating state while handling PC events.
 948                     if (count == 0)
 949                         assert(!thread[tid]->inSyscall &&
 950                                !thread[tid]->trapPending);
 951                     oldpc = PC[tid];
 952                     cpu->system->pcEventQueue.service(
 953                         thread[tid]->getTC());
 954                     count++;
 955                 } while (oldpc != PC[tid]);
 956                 if (count > 1) {
 957                     DPRINTF(Commit, "PC skip function event, stopping commit\n");
 958                     break;
 959                 }
 960 #endif
 961             } else {
 962                 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
 963                         "[tid:%i] [sn:%i].\n",
 964                         head_inst->readPC(), tid ,head_inst->seqNum);
 965                 break;
 966             }
 967         }
 968     }
 969
 970     DPRINTF(CommitRate, "%i\n", num_committed);
 971     numCommittedDist.sample(num_committed);
 972
 973     if (num_committed == commitWidth) {
 974         commitEligibleSamples++;
 975     }
 976 }
 977
 978 template <class Impl>
 979 bool
 980 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 981 {
 982     assert(head_inst);
 983
 984     int tid = head_inst->threadNumber;
 985
 986     // If the instruction is not executed yet, then it will need extra
 987     // handling.  Signal backwards that it should be executed.
 988     if (!head_inst->isExecuted()) {
 989         // Keep this number correct.  We have not yet actually executed
 990         // and committed this instruction.
 991         thread[tid]->funcExeInst--;
 992
 993         if (head_inst->isNonSpeculative() ||
 994             head_inst->isStoreConditional() ||
 995             head_inst->isMemBarrier() ||
 996             head_inst->isWriteBarrier()) {
 997
 998             DPRINTF(Commit, "Encountered a barrier or non-speculative "
 999                     "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
1000                     head_inst->seqNum, head_inst->readPC());
1001
1002             if (inst_num > 0 || iewStage->hasStoresToWB()) {
1003                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1004                 return false;
1005             }
1006
1007             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1008
1009             // Change the instruction so it won't try to commit again until
1010             // it is executed.
1011             head_inst->clearCanCommit();
1012
1013             ++commitNonSpecStalls;
1014
1015             return false;
1016         } else if (head_inst->isLoad()) {
1017             if (inst_num > 0 || iewStage->hasStoresToWB()) {
1018                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1019                 return false;
1020             }
1021
1022             assert(head_inst->uncacheable());
1023             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1024                     head_inst->seqNum, head_inst->readPC());
1025
1026             // Send back the non-speculative instruction's sequence
1027             // number.  Tell the lsq to re-execute the load.
1028             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1029             toIEW->commitInfo[tid].uncached = true;
1030             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1031
1032             head_inst->clearCanCommit();
1033
1034             return false;
1035         } else {
1036             panic("Trying to commit un-executed instruction "
1037                   "of unknown type!\n");
1038         }
1039     }
1040
1041     if (head_inst->isThreadSync()) {
1042         // Not handled for now.
1043         panic("Thread sync instructions are not handled yet.\n");
1044     }
1045
1046     // Check if the instruction caused a fault.  If so, trap.
1047     Fault inst_fault = head_inst->getFault();
1048
1049     // Stores mark themselves as completed.
1050     if (!head_inst->isStore() && inst_fault == NoFault) {
1051         head_inst->setCompleted();
1052     }
1053
1054 #if USE_CHECKER
1055     // Use checker prior to updating anything due to traps or PC
1056     // based events.
1057     if (cpu->checker) {
1058         cpu->checker->verify(head_inst);
1059     }
1060 #endif
1061
1062     // DTB will sometimes need the machine instruction for when
1063     // faults happen.  So we will set it here, prior to the DTB
1064     // possibly needing it for its fault.
1065     thread[tid]->setInst(
1066         static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1067
1068     if (inst_fault != NoFault) {
1069         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1070                 head_inst->seqNum, head_inst->readPC());
1071
1072         if (iewStage->hasStoresToWB() || inst_num > 0) {
1073             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1074             return false;
1075         }
1076
1077         head_inst->setCompleted();
1078
1079 #if USE_CHECKER
1080         if (cpu->checker && head_inst->isStore()) {
1081             cpu->checker->verify(head_inst);
1082         }
1083 #endif
1084
1085         assert(!thread[tid]->inSyscall);
1086
1087         // Mark that we're in state update mode so that the trap's
1088         // execution doesn't generate extra squashes.
1089         thread[tid]->inSyscall = true;
1090
1091         // Execute the trap.  Although it's slightly unrealistic in
1092         // terms of timing (as it doesn't wait for the full timing of
1093         // the trap event to complete before updating state), it's
1094         // needed to update the state as soon as possible.  This
1095         // prevents external agents from changing any specific state
1096         // that the trap need.
1097         cpu->trap(inst_fault, tid);
1098
1099         // Exit state update mode to avoid accidental updating.
1100         thread[tid]->inSyscall = false;
1101
1102         commitStatus[tid] = TrapPending;
1103
1104         if (head_inst->traceData) {
1105             head_inst->traceData->setFetchSeq(head_inst->seqNum);
1106             head_inst->traceData->setCPSeq(thread[tid]->numInst);
1107             head_inst->traceData->dump();
1108             delete head_inst->traceData;
1109             head_inst->traceData = NULL;
1110         }
1111
1112         // Generate trap squash event.
1113         generateTrapEvent(tid);
1114 //        warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1115         return false;
1116     }
1117
1118     updateComInstStats(head_inst);
1119
1120 #if FULL_SYSTEM
1121     if (thread[tid]->profile) {
1122 //        bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1123 //        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1124         thread[tid]->profilePC = head_inst->readPC();
1125         ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1126                                                           head_inst->staticInst);
1127
1128         if (node)
1129             thread[tid]->profileNode = node;
1130     }
1131 #endif
1132
1133     if (head_inst->traceData) {
1134         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1135         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1136         head_inst->traceData->dump();
1137         delete head_inst->traceData;
1138         head_inst->traceData = NULL;
1139     }
1140
1141     // Update the commit rename map
1142     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1143         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1144                                  head_inst->renamedDestRegIdx(i));
1145     }
1146
1147     if (head_inst->isCopy())
1148         panic("Should not commit any copy instructions!");
1149
1150     // Finally clear the head ROB entry.
1151     rob->retireHead(tid);
1152
1153     // If this was a store, record it for this cycle.
1154     if (head_inst->isStore())
1155         committedStores[tid] = true;
1156
1157     // Return true to indicate that we have committed an instruction.
1158     return true;
1159 }
1160
1161 template <class Impl>
1162 void
1163 DefaultCommit<Impl>::getInsts()
1164 {
1165     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1166
1167 #if ISA_HAS_DELAY_SLOT
1168     // Read any renamed instructions and place them into the ROB.
1169     int insts_to_process = std::min((int)renameWidth,
1170                                (int)(fromRename->size + skidBuffer.size()));
1171     int rename_idx = 0;
1172
1173     DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1174             "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1175             skidBuffer.size());
1176 #else
1177     // Read any renamed instructions and place them into the ROB.
1178     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1179 #endif
1180
1181
1182     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1183         DynInstPtr inst;
1184
1185 #if ISA_HAS_DELAY_SLOT
1186         // Get insts from skidBuffer or from Rename
1187         if (skidBuffer.size() > 0) {
1188             DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1189             inst = skidBuffer.front();
1190             skidBuffer.pop();
1191         } else {
1192             DPRINTF(Commit, "Grabbing rename inst.\n");
1193             inst = fromRename->insts[rename_idx++];
1194         }
1195 #else
1196         inst = fromRename->insts[inst_num];
1197 #endif
1198         int tid = inst->threadNumber;
1199
1200         if (!inst->isSquashed() &&
1201             commitStatus[tid] != ROBSquashing &&
1202             commitStatus[tid] != TrapPending) {
1203             changedROBNumEntries[tid] = true;
1204
1205             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1206                     inst->readPC(), inst->seqNum, tid);
1207
1208             rob->insertInst(inst);
1209
1210             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1211
1212             youngestSeqNum[tid] = inst->seqNum;
1213         } else {
1214             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1215                     "squashed, skipping.\n",
1216                     inst->readPC(), inst->seqNum, tid);
1217         }
1218     }
1219
1220 #if ISA_HAS_DELAY_SLOT
1221     if (rename_idx < fromRename->size) {
1222         DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1223
1224         for (;
1225              rename_idx < fromRename->size;
1226              rename_idx++) {
1227             DynInstPtr inst = fromRename->insts[rename_idx];
1228
1229             if (!inst->isSquashed()) {
1230                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1231                         "skidBuffer.\n", inst->readPC(), inst->seqNum,
1232                         inst->threadNumber);
1233                 skidBuffer.push(inst);
1234             } else {
1235                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1236                         "squashed, skipping.\n",
1237                         inst->readPC(), inst->seqNum, inst->threadNumber);
1238             }
1239         }
1240     }
1241 #endif
1242
1243 }
1244
1245 template <class Impl>
1246 void
1247 DefaultCommit<Impl>::skidInsert()
1248 {
1249     DPRINTF(Commit, "Attempting to any instructions from rename into "
1250             "skidBuffer.\n");
1251
1252     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1253         DynInstPtr inst = fromRename->insts[inst_num];
1254
1255         if (!inst->isSquashed()) {
1256             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1257                     "skidBuffer.\n", inst->readPC(), inst->seqNum,
1258                     inst->threadNumber);
1259             skidBuffer.push(inst);
1260         } else {
1261             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1262                     "squashed, skipping.\n",
1263                     inst->readPC(), inst->seqNum, inst->threadNumber);
1264         }
1265     }
1266 }
1267
1268 template <class Impl>
1269 void
1270 DefaultCommit<Impl>::markCompletedInsts()
1271 {
1272     // Grab completed insts out of the IEW instruction queue, and mark
1273     // instructions completed within the ROB.
1274     for (int inst_num = 0;
1275          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1276          ++inst_num)
1277     {
1278         if (!fromIEW->insts[inst_num]->isSquashed()) {
1279             DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1280                     "within ROB.\n",
1281                     fromIEW->insts[inst_num]->threadNumber,
1282                     fromIEW->insts[inst_num]->readPC(),
1283                     fromIEW->insts[inst_num]->seqNum);
1284
1285             // Mark the instruction as ready to commit.
1286             fromIEW->insts[inst_num]->setCanCommit();
1287         }
1288     }
1289 }
1290
1291 template <class Impl>
1292 bool
1293 DefaultCommit<Impl>::robDoneSquashing()
1294 {
1295     std::list<unsigned>::iterator threads = activeThreads->begin();
1296     std::list<unsigned>::iterator end = activeThreads->end();
1297
1298     while (threads != end) {
1299         unsigned tid = *threads++;
1300
1301         if (!rob->isDoneSquashing(tid))
1302             return false;
1303     }
1304
1305     return true;
1306 }
1307
1308 template <class Impl>
1309 void
1310 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1311 {
1312     unsigned thread = inst->threadNumber;
1313
1314     //
1315     //  Pick off the software prefetches
1316     //
1317 #ifdef TARGET_ALPHA
1318     if (inst->isDataPrefetch()) {
1319         statComSwp[thread]++;
1320     } else {
1321         statComInst[thread]++;
1322     }
1323 #else
1324     statComInst[thread]++;
1325 #endif
1326
1327     //
1328     //  Control Instructions
1329     //
1330     if (inst->isControl())
1331         statComBranches[thread]++;
1332
1333     //
1334     //  Memory references
1335     //
1336     if (inst->isMemRef()) {
1337         statComRefs[thread]++;
1338
1339         if (inst->isLoad()) {
1340             statComLoads[thread]++;
1341         }
1342     }
1343
1344     if (inst->isMemBarrier()) {
1345         statComMembars[thread]++;
1346     }
1347 }
1348
1349 ////////////////////////////////////////
1350 //                                    //
1351 //  SMT COMMIT POLICY MAINTAINED HERE //
1352 //                                    //
1353 ////////////////////////////////////////
1354 template <class Impl>
1355 int
1356 DefaultCommit<Impl>::getCommittingThread()
1357 {
1358     if (numThreads > 1) {
1359         switch (commitPolicy) {
1360
1361           case Aggressive:
1362             //If Policy is Aggressive, commit will call
1363             //this function multiple times per
1364             //cycle
1365             return oldestReady();
1366
1367           case RoundRobin:
1368             return roundRobin();
1369
1370           case OldestReady:
1371             return oldestReady();
1372
1373           default:
1374             return -1;
1375         }
1376     } else {
1377         assert(!activeThreads->empty());
1378         int tid = activeThreads->front();
1379
1380         if (commitStatus[tid] == Running ||
1381             commitStatus[tid] == Idle ||
1382             commitStatus[tid] == FetchTrapPending) {
1383             return tid;
1384         } else {
1385             return -1;
1386         }
1387     }
1388 }
1389
1390 template<class Impl>
1391 int
1392 DefaultCommit<Impl>::roundRobin()
1393 {
1394     std::list<unsigned>::iterator pri_iter = priority_list.begin();
1395     std::list<unsigned>::iterator end      = priority_list.end();
1396
1397     while (pri_iter != end) {
1398         unsigned tid = *pri_iter;
1399
1400         if (commitStatus[tid] == Running ||
1401             commitStatus[tid] == Idle ||
1402             commitStatus[tid] == FetchTrapPending) {
1403
1404             if (rob->isHeadReady(tid)) {
1405                 priority_list.erase(pri_iter);
1406                 priority_list.push_back(tid);
1407
1408                 return tid;
1409             }
1410         }
1411
1412         pri_iter++;
1413     }
1414
1415     return -1;
1416 }
1417
1418 template<class Impl>
1419 int
1420 DefaultCommit<Impl>::oldestReady()
1421 {
1422     unsigned oldest = 0;
1423     bool first = true;
1424
1425     std::list<unsigned>::iterator threads = activeThreads->begin();
1426     std::list<unsigned>::iterator end = activeThreads->end();
1427
1428     while (threads != end) {
1429         unsigned tid = *threads++;
1430
1431         if (!rob->isEmpty(tid) &&
1432             (commitStatus[tid] == Running ||
1433              commitStatus[tid] == Idle ||
1434              commitStatus[tid] == FetchTrapPending)) {
1435
1436             if (rob->isHeadReady(tid)) {
1437
1438                 DynInstPtr head_inst = rob->readHeadInst(tid);
1439
1440                 if (first) {
1441                     oldest = tid;
1442                     first = false;
1443                 } else if (head_inst->seqNum < oldest) {
1444                     oldest = tid;
1445                 }
1446             }
1447         }
1448     }
1449
1450     if (!first) {
1451         return oldest;
1452     } else {
1453         return -1;
1454     }
1455 }