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43 #ifndef __CPU_O3_COMMIT_IMPL_HH__
44 #define __CPU_O3_COMMIT_IMPL_HH__
50 #include "arch/utility.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/cp_annotate.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/checker/cpu.hh"
55 #include "cpu/o3/commit.hh"
56 #include "cpu/o3/thread_state.hh"
57 #include "cpu/base.hh"
58 #include "cpu/exetrace.hh"
59 #include "cpu/timebuf.hh"
60 #include "debug/Activity.hh"
61 #include "debug/Commit.hh"
62 #include "debug/CommitRate.hh"
63 #include "debug/Drain.hh"
64 #include "debug/ExecFaulting.hh"
65 #include "debug/O3PipeView.hh"
66 #include "params/DerivO3CPU.hh"
67 #include "sim/faults.hh"
68 #include "sim/full_system.hh"
73 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
81 DefaultCommit<Impl>::TrapEvent::process()
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
90 DefaultCommit<Impl>::TrapEvent::description() const
96 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
107 trapLatency(params->trapLatency),
108 canHandleInterrupts(true),
109 avoidQuiesceLiveLock(false)
111 if (commitWidth > Impl::MaxWidth)
112 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
113 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
114 commitWidth, static_cast<int>(Impl::MaxWidth));
117 _nextStatus = Inactive;
118 std::string policy = params->smtCommitPolicy;
120 //Convert string to lowercase
121 std::transform(policy.begin(), policy.end(), policy.begin(),
122 (int(*)(int)) tolower);
124 //Assign commit policy
125 if (policy == "aggressive"){
126 commitPolicy = Aggressive;
128 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
129 } else if (policy == "roundrobin"){
130 commitPolicy = RoundRobin;
132 //Set-Up Priority List
133 for (ThreadID tid = 0; tid < numThreads; tid++) {
134 priority_list.push_back(tid);
137 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
138 } else if (policy == "oldestready"){
139 commitPolicy = OldestReady;
141 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
143 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
144 "RoundRobin,OldestReady}");
147 for (ThreadID tid = 0; tid < numThreads; tid++) {
148 commitStatus[tid] = Idle;
149 changedROBNumEntries[tid] = false;
150 checkEmptyROB[tid] = false;
151 trapInFlight[tid] = false;
152 committedStores[tid] = false;
153 trapSquash[tid] = false;
154 tcSquash[tid] = false;
156 lastCommitedSeqNum[tid] = 0;
157 squashAfterInst[tid] = NULL;
162 template <class Impl>
164 DefaultCommit<Impl>::name() const
166 return cpu->name() + ".commit";
169 template <class Impl>
171 DefaultCommit<Impl>::regProbePoints()
173 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
174 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
177 template <class Impl>
179 DefaultCommit<Impl>::regStats()
181 using namespace Stats;
183 .name(name() + ".commitSquashedInsts")
184 .desc("The number of squashed insts skipped by commit")
185 .prereq(commitSquashedInsts);
187 .name(name() + ".commitSquashEvents")
188 .desc("The number of times commit is told to squash")
189 .prereq(commitSquashEvents);
191 .name(name() + ".commitNonSpecStalls")
192 .desc("The number of times commit has been forced to stall to "
193 "communicate backwards")
194 .prereq(commitNonSpecStalls);
196 .name(name() + ".branchMispredicts")
197 .desc("The number of times a branch was mispredicted")
198 .prereq(branchMispredicts);
200 .init(0,commitWidth,1)
201 .name(name() + ".committed_per_cycle")
202 .desc("Number of insts commited each cycle")
207 .init(cpu->numThreads)
208 .name(name() + ".committedInsts")
209 .desc("Number of instructions committed")
214 .init(cpu->numThreads)
215 .name(name() + ".committedOps")
216 .desc("Number of ops (including micro ops) committed")
221 .init(cpu->numThreads)
222 .name(name() + ".swp_count")
223 .desc("Number of s/w prefetches committed")
228 .init(cpu->numThreads)
229 .name(name() + ".refs")
230 .desc("Number of memory references committed")
235 .init(cpu->numThreads)
236 .name(name() + ".loads")
237 .desc("Number of loads committed")
242 .init(cpu->numThreads)
243 .name(name() + ".membars")
244 .desc("Number of memory barriers committed")
249 .init(cpu->numThreads)
250 .name(name() + ".branches")
251 .desc("Number of branches committed")
256 .init(cpu->numThreads)
257 .name(name() + ".fp_insts")
258 .desc("Number of committed floating point instructions.")
263 .init(cpu->numThreads)
264 .name(name()+".int_insts")
265 .desc("Number of committed integer instructions.")
270 .init(cpu->numThreads)
271 .name(name()+".function_calls")
272 .desc("Number of function calls committed.")
276 statCommittedInstType
277 .init(numThreads,Enums::Num_OpClass)
278 .name(name() + ".op_class")
279 .desc("Class of committed instruction")
280 .flags(total | pdf | dist)
282 statCommittedInstType.ysubnames(Enums::OpClassStrings);
285 .init(cpu->numThreads)
286 .name(name() + ".bw_limited")
287 .desc("number of insts not committed due to BW limits")
291 commitEligibleSamples
292 .name(name() + ".bw_lim_events")
293 .desc("number cycles where commit BW limit reached")
297 template <class Impl>
299 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
304 template <class Impl>
306 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
310 // Setup wire to send information back to IEW.
311 toIEW = timeBuffer->getWire(0);
313 // Setup wire to read data from IEW (for the ROB).
314 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
317 template <class Impl>
319 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
323 // Setup wire to get instructions from rename (for the ROB).
324 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
327 template <class Impl>
329 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
331 renameQueue = rq_ptr;
333 // Setup wire to get instructions from rename (for the ROB).
334 fromRename = renameQueue->getWire(-renameToROBDelay);
337 template <class Impl>
339 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
343 // Setup wire to get instructions from IEW.
344 fromIEW = iewQueue->getWire(-iewToCommitDelay);
347 template <class Impl>
349 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
351 iewStage = iew_stage;
356 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
358 activeThreads = at_ptr;
361 template <class Impl>
363 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
365 for (ThreadID tid = 0; tid < numThreads; tid++)
366 renameMap[tid] = &rm_ptr[tid];
369 template <class Impl>
371 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
376 template <class Impl>
378 DefaultCommit<Impl>::startupStage()
380 rob->setActiveThreads(activeThreads);
383 // Broadcast the number of free entries.
384 for (ThreadID tid = 0; tid < numThreads; tid++) {
385 toIEW->commitInfo[tid].usedROB = true;
386 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
387 toIEW->commitInfo[tid].emptyROB = true;
390 // Commit must broadcast the number of free entries it has at the
391 // start of the simulation, so it starts as active.
392 cpu->activateStage(O3CPU::CommitIdx);
394 cpu->activityThisCycle();
397 template <class Impl>
399 DefaultCommit<Impl>::drain()
404 template <class Impl>
406 DefaultCommit<Impl>::drainResume()
408 drainPending = false;
411 template <class Impl>
413 DefaultCommit<Impl>::drainSanityCheck() const
416 rob->drainSanityCheck();
419 template <class Impl>
421 DefaultCommit<Impl>::isDrained() const
423 /* Make sure no one is executing microcode. There are two reasons
425 * - Hardware virtualized CPUs can't switch into the middle of a
426 * microcode sequence.
427 * - The current fetch implementation will most likely get very
428 * confused if it tries to start fetching an instruction that
429 * is executing in the middle of a ucode sequence that changes
430 * address mappings. This can happen on for example x86.
432 for (ThreadID tid = 0; tid < numThreads; tid++) {
433 if (pc[tid].microPC() != 0)
437 /* Make sure that all instructions have finished committing before
438 * declaring the system as drained. We want the pipeline to be
439 * completely empty when we declare the CPU to be drained. This
440 * makes debugging easier since CPU handover and restoring from a
441 * checkpoint with a different CPU should have the same timing.
443 return rob->isEmpty() &&
444 interrupt == NoFault;
447 template <class Impl>
449 DefaultCommit<Impl>::takeOverFrom()
452 _nextStatus = Inactive;
453 for (ThreadID tid = 0; tid < numThreads; tid++) {
454 commitStatus[tid] = Idle;
455 changedROBNumEntries[tid] = false;
456 trapSquash[tid] = false;
457 tcSquash[tid] = false;
458 squashAfterInst[tid] = NULL;
464 template <class Impl>
466 DefaultCommit<Impl>::updateStatus()
468 // reset ROB changed variable
469 list<ThreadID>::iterator threads = activeThreads->begin();
470 list<ThreadID>::iterator end = activeThreads->end();
472 while (threads != end) {
473 ThreadID tid = *threads++;
475 changedROBNumEntries[tid] = false;
477 // Also check if any of the threads has a trap pending
478 if (commitStatus[tid] == TrapPending ||
479 commitStatus[tid] == FetchTrapPending) {
480 _nextStatus = Active;
484 if (_nextStatus == Inactive && _status == Active) {
485 DPRINTF(Activity, "Deactivating stage.\n");
486 cpu->deactivateStage(O3CPU::CommitIdx);
487 } else if (_nextStatus == Active && _status == Inactive) {
488 DPRINTF(Activity, "Activating stage.\n");
489 cpu->activateStage(O3CPU::CommitIdx);
492 _status = _nextStatus;
495 template <class Impl>
497 DefaultCommit<Impl>::setNextStatus()
501 list<ThreadID>::iterator threads = activeThreads->begin();
502 list<ThreadID>::iterator end = activeThreads->end();
504 while (threads != end) {
505 ThreadID tid = *threads++;
507 if (commitStatus[tid] == ROBSquashing) {
512 squashCounter = squashes;
514 // If commit is currently squashing, then it will have activity for the
515 // next cycle. Set its next status as active.
517 _nextStatus = Active;
521 template <class Impl>
523 DefaultCommit<Impl>::changedROBEntries()
525 list<ThreadID>::iterator threads = activeThreads->begin();
526 list<ThreadID>::iterator end = activeThreads->end();
528 while (threads != end) {
529 ThreadID tid = *threads++;
531 if (changedROBNumEntries[tid]) {
539 template <class Impl>
541 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
543 return rob->numFreeEntries(tid);
546 template <class Impl>
548 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
550 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
552 TrapEvent *trap = new TrapEvent(this, tid);
554 cpu->schedule(trap, cpu->clockEdge(trapLatency));
555 trapInFlight[tid] = true;
556 thread[tid]->trapPending = true;
559 template <class Impl>
561 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
563 assert(!trapInFlight[tid]);
564 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
566 tcSquash[tid] = true;
569 template <class Impl>
571 DefaultCommit<Impl>::squashAll(ThreadID tid)
573 // If we want to include the squashing instruction in the squash,
574 // then use one older sequence number.
575 // Hopefully this doesn't mess things up. Basically I want to squash
576 // all instructions of this thread.
577 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
578 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
580 // All younger instructions will be squashed. Set the sequence
581 // number as the youngest instruction in the ROB (0 in this case.
582 // Hopefully nothing breaks.)
583 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
585 rob->squash(squashed_inst, tid);
586 changedROBNumEntries[tid] = true;
588 // Send back the sequence number of the squashed instruction.
589 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
591 // Send back the squash signal to tell stages that they should
593 toIEW->commitInfo[tid].squash = true;
595 // Send back the rob squashing signal so other stages know that
596 // the ROB is in the process of squashing.
597 toIEW->commitInfo[tid].robSquashing = true;
599 toIEW->commitInfo[tid].mispredictInst = NULL;
600 toIEW->commitInfo[tid].squashInst = NULL;
602 toIEW->commitInfo[tid].pc = pc[tid];
605 template <class Impl>
607 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
611 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
613 thread[tid]->trapPending = false;
614 thread[tid]->noSquashFromTC = false;
615 trapInFlight[tid] = false;
617 trapSquash[tid] = false;
619 commitStatus[tid] = ROBSquashing;
620 cpu->activityThisCycle();
623 template <class Impl>
625 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
629 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
631 thread[tid]->noSquashFromTC = false;
632 assert(!thread[tid]->trapPending);
634 commitStatus[tid] = ROBSquashing;
635 cpu->activityThisCycle();
637 tcSquash[tid] = false;
640 template <class Impl>
642 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
644 DPRINTF(Commit, "Squashing after squash after request, "
645 "restarting at PC %s\n", pc[tid]);
648 // Make sure to inform the fetch stage of which instruction caused
649 // the squash. It'll try to re-fetch an instruction executing in
650 // microcode unless this is set.
651 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
652 squashAfterInst[tid] = NULL;
654 commitStatus[tid] = ROBSquashing;
655 cpu->activityThisCycle();
658 template <class Impl>
660 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
662 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
663 tid, head_inst->seqNum);
665 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
666 commitStatus[tid] = SquashAfterPending;
667 squashAfterInst[tid] = head_inst;
670 template <class Impl>
672 DefaultCommit<Impl>::tick()
674 wroteToTimeBuffer = false;
675 _nextStatus = Inactive;
677 if (activeThreads->empty())
680 list<ThreadID>::iterator threads = activeThreads->begin();
681 list<ThreadID>::iterator end = activeThreads->end();
683 // Check if any of the threads are done squashing. Change the
684 // status if they are done.
685 while (threads != end) {
686 ThreadID tid = *threads++;
688 // Clear the bit saying if the thread has committed stores
690 committedStores[tid] = false;
692 if (commitStatus[tid] == ROBSquashing) {
694 if (rob->isDoneSquashing(tid)) {
695 commitStatus[tid] = Running;
697 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
698 " insts this cycle.\n", tid);
700 toIEW->commitInfo[tid].robSquashing = true;
701 wroteToTimeBuffer = true;
708 markCompletedInsts();
710 threads = activeThreads->begin();
712 while (threads != end) {
713 ThreadID tid = *threads++;
715 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
716 // The ROB has more instructions it can commit. Its next status
718 _nextStatus = Active;
720 DynInstPtr inst = rob->readHeadInst(tid);
722 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
723 " ROB and ready to commit\n",
724 tid, inst->seqNum, inst->pcState());
726 } else if (!rob->isEmpty(tid)) {
727 DynInstPtr inst = rob->readHeadInst(tid);
729 ppCommitStall->notify(inst);
731 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
732 "%s is head of ROB and not ready\n",
733 tid, inst->seqNum, inst->pcState());
736 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
737 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
741 if (wroteToTimeBuffer) {
742 DPRINTF(Activity, "Activity This Cycle.\n");
743 cpu->activityThisCycle();
749 template <class Impl>
751 DefaultCommit<Impl>::handleInterrupt()
753 // Verify that we still have an interrupt to handle
754 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
755 DPRINTF(Commit, "Pending interrupt is cleared by master before "
756 "it got handled. Restart fetching from the orig path.\n");
757 toIEW->commitInfo[0].clearInterrupt = true;
759 avoidQuiesceLiveLock = true;
763 // Wait until all in flight instructions are finished before enterring
765 if (canHandleInterrupts && cpu->instList.empty()) {
766 // Squash or record that I need to squash this cycle if
767 // an interrupt needed to be handled.
768 DPRINTF(Commit, "Interrupt detected.\n");
770 // Clear the interrupt now that it's going to be handled
771 toIEW->commitInfo[0].clearInterrupt = true;
773 assert(!thread[0]->noSquashFromTC);
774 thread[0]->noSquashFromTC = true;
777 cpu->checker->handlePendingInt();
780 // CPU will handle interrupt. Note that we ignore the local copy of
781 // interrupt. This is because the local copy may no longer be the
782 // interrupt that the interrupt controller thinks is being handled.
783 cpu->processInterrupts(cpu->getInterrupts());
785 thread[0]->noSquashFromTC = false;
787 commitStatus[0] = TrapPending;
789 // Generate trap squash event.
790 generateTrapEvent(0);
793 avoidQuiesceLiveLock = false;
795 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
796 "flight, ROB is %sempty\n",
797 canHandleInterrupts ? "not " : "",
798 cpu->instList.empty() ? "" : "not " );
802 template <class Impl>
804 DefaultCommit<Impl>::propagateInterrupt()
806 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
810 // Process interrupts if interrupts are enabled, not in PAL
811 // mode, and no other traps or external squashes are currently
813 // @todo: Allow other threads to handle interrupts.
815 // Get any interrupt that happened
816 interrupt = cpu->getInterrupts();
818 // Tell fetch that there is an interrupt pending. This
819 // will make fetch wait until it sees a non PAL-mode PC,
820 // at which point it stops fetching instructions.
821 if (interrupt != NoFault)
822 toIEW->commitInfo[0].interruptPending = true;
825 template <class Impl>
827 DefaultCommit<Impl>::commit()
830 // Check if we have a interrupt and get read to handle it
831 if (cpu->checkInterrupts(cpu->tcBase(0)))
832 propagateInterrupt();
835 ////////////////////////////////////
836 // Check for any possible squashes, handle them first
837 ////////////////////////////////////
838 list<ThreadID>::iterator threads = activeThreads->begin();
839 list<ThreadID>::iterator end = activeThreads->end();
841 while (threads != end) {
842 ThreadID tid = *threads++;
844 // Not sure which one takes priority. I think if we have
845 // both, that's a bad sign.
846 if (trapSquash[tid]) {
847 assert(!tcSquash[tid]);
849 } else if (tcSquash[tid]) {
850 assert(commitStatus[tid] != TrapPending);
852 } else if (commitStatus[tid] == SquashAfterPending) {
853 // A squash from the previous cycle of the commit stage (i.e.,
854 // commitInsts() called squashAfter) is pending. Squash the
856 squashFromSquashAfter(tid);
859 // Squashed sequence number must be older than youngest valid
860 // instruction in the ROB. This prevents squashes from younger
861 // instructions overriding squashes from older instructions.
862 if (fromIEW->squash[tid] &&
863 commitStatus[tid] != TrapPending &&
864 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
866 if (fromIEW->mispredictInst[tid]) {
868 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
870 fromIEW->mispredictInst[tid]->instAddr(),
871 fromIEW->squashedSeqNum[tid]);
874 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
875 tid, fromIEW->squashedSeqNum[tid]);
878 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
880 fromIEW->pc[tid].nextInstAddr());
882 commitStatus[tid] = ROBSquashing;
884 // If we want to include the squashing instruction in the squash,
885 // then use one older sequence number.
886 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
888 if (fromIEW->includeSquashInst[tid]) {
892 // All younger instructions will be squashed. Set the sequence
893 // number as the youngest instruction in the ROB.
894 youngestSeqNum[tid] = squashed_inst;
896 rob->squash(squashed_inst, tid);
897 changedROBNumEntries[tid] = true;
899 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
901 toIEW->commitInfo[tid].squash = true;
903 // Send back the rob squashing signal so other stages know that
904 // the ROB is in the process of squashing.
905 toIEW->commitInfo[tid].robSquashing = true;
907 toIEW->commitInfo[tid].mispredictInst =
908 fromIEW->mispredictInst[tid];
909 toIEW->commitInfo[tid].branchTaken =
910 fromIEW->branchTaken[tid];
911 toIEW->commitInfo[tid].squashInst =
912 rob->findInst(tid, squashed_inst);
913 if (toIEW->commitInfo[tid].mispredictInst) {
914 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
915 toIEW->commitInfo[tid].branchTaken = true;
919 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
921 if (toIEW->commitInfo[tid].mispredictInst) {
930 if (squashCounter != numThreads) {
931 // If we're not currently squashing, then get instructions.
934 // Try to commit any instructions.
938 //Check for any activity
939 threads = activeThreads->begin();
941 while (threads != end) {
942 ThreadID tid = *threads++;
944 if (changedROBNumEntries[tid]) {
945 toIEW->commitInfo[tid].usedROB = true;
946 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
948 wroteToTimeBuffer = true;
949 changedROBNumEntries[tid] = false;
950 if (rob->isEmpty(tid))
951 checkEmptyROB[tid] = true;
954 // ROB is only considered "empty" for previous stages if: a)
955 // ROB is empty, b) there are no outstanding stores, c) IEW
956 // stage has received any information regarding stores that
958 // c) is checked by making sure to not consider the ROB empty
959 // on the same cycle as when stores have been committed.
960 // @todo: Make this handle multi-cycle communication between
962 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
963 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
964 checkEmptyROB[tid] = false;
965 toIEW->commitInfo[tid].usedROB = true;
966 toIEW->commitInfo[tid].emptyROB = true;
967 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
968 wroteToTimeBuffer = true;
974 template <class Impl>
976 DefaultCommit<Impl>::commitInsts()
978 ////////////////////////////////////
980 // Note that commit will be handled prior to putting new
981 // instructions in the ROB so that the ROB only tries to commit
982 // instructions it has in this current cycle, and not instructions
983 // it is writing in during this cycle. Can't commit and squash
984 // things at the same time...
985 ////////////////////////////////////
987 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
989 unsigned num_committed = 0;
991 DynInstPtr head_inst;
993 // Commit as many instructions as possible until the commit bandwidth
994 // limit is reached, or it becomes impossible to commit any more.
995 while (num_committed < commitWidth) {
996 // Check for any interrupt that we've already squashed for
997 // and start processing it.
998 if (interrupt != NoFault)
1001 int commit_thread = getCommittingThread();
1003 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1006 head_inst = rob->readHeadInst(commit_thread);
1008 ThreadID tid = head_inst->threadNumber;
1010 assert(tid == commit_thread);
1012 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1013 head_inst->seqNum, tid);
1015 // If the head instruction is squashed, it is ready to retire
1016 // (be removed from the ROB) at any time.
1017 if (head_inst->isSquashed()) {
1019 DPRINTF(Commit, "Retiring squashed instruction from "
1022 rob->retireHead(commit_thread);
1024 ++commitSquashedInsts;
1026 // Record that the number of ROB entries has changed.
1027 changedROBNumEntries[tid] = true;
1029 pc[tid] = head_inst->pcState();
1031 // Increment the total number of non-speculative instructions
1033 // Hack for now: it really shouldn't happen until after the
1034 // commit is deemed to be successful, but this count is needed
1036 thread[tid]->funcExeInst++;
1038 // Try to commit the head instruction.
1039 bool commit_success = commitHead(head_inst, num_committed);
1041 if (commit_success) {
1043 statCommittedInstType[tid][head_inst->opClass()]++;
1044 ppCommit->notify(head_inst);
1046 changedROBNumEntries[tid] = true;
1048 // Set the doneSeqNum to the youngest committed instruction.
1049 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1052 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1053 ((THE_ISA != ALPHA_ISA) ||
1054 (!(pc[0].instAddr() & 0x3)));
1057 // Updates misc. registers.
1058 head_inst->updateMiscRegs();
1060 // Check instruction execution if it successfully commits and
1061 // is not carrying a fault.
1063 cpu->checker->verify(head_inst);
1066 cpu->traceFunctions(pc[tid].instAddr());
1068 TheISA::advancePC(pc[tid], head_inst->staticInst);
1070 // Keep track of the last sequence number commited
1071 lastCommitedSeqNum[tid] = head_inst->seqNum;
1073 // If this is an instruction that doesn't play nicely with
1074 // others squash everything and restart fetch
1075 if (head_inst->isSquashAfter())
1076 squashAfter(tid, head_inst);
1079 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1080 if (pc[tid].microPC() == 0 && interrupt == NoFault) {
1081 squashAfter(tid, head_inst);
1082 cpu->commitDrained(tid);
1088 // Debug statement. Checks to make sure we're not
1089 // currently updating state while handling PC events.
1090 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1092 oldpc = pc[tid].instAddr();
1093 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1095 } while (oldpc != pc[tid].instAddr());
1098 "PC skip function event, stopping commit\n");
1102 // Check if an instruction just enabled interrupts and we've
1103 // previously had an interrupt pending that was not handled
1104 // because interrupts were subsequently disabled before the
1105 // pipeline reached a place to handle the interrupt. In that
1106 // case squash now to make sure the interrupt is handled.
1108 // If we don't do this, we might end up in a live lock situation
1109 if (!interrupt && avoidQuiesceLiveLock &&
1110 (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
1111 cpu->checkInterrupts(cpu->tcBase(0)))
1112 squashAfter(tid, head_inst);
1114 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1115 "[tid:%i] [sn:%i].\n",
1116 head_inst->pcState(), tid ,head_inst->seqNum);
1122 DPRINTF(CommitRate, "%i\n", num_committed);
1123 numCommittedDist.sample(num_committed);
1125 if (num_committed == commitWidth) {
1126 commitEligibleSamples++;
1130 template <class Impl>
1132 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1136 ThreadID tid = head_inst->threadNumber;
1138 // If the instruction is not executed yet, then it will need extra
1139 // handling. Signal backwards that it should be executed.
1140 if (!head_inst->isExecuted()) {
1141 // Keep this number correct. We have not yet actually executed
1142 // and committed this instruction.
1143 thread[tid]->funcExeInst--;
1145 // Make sure we are only trying to commit un-executed instructions we
1146 // think are possible.
1147 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1148 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1149 (head_inst->isLoad() && head_inst->uncacheable()));
1151 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1152 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1153 head_inst->seqNum, head_inst->pcState());
1155 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1156 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1160 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1162 // Change the instruction so it won't try to commit again until
1164 head_inst->clearCanCommit();
1166 if (head_inst->isLoad() && head_inst->uncacheable()) {
1167 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1168 head_inst->seqNum, head_inst->pcState());
1169 toIEW->commitInfo[tid].uncached = true;
1170 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1172 ++commitNonSpecStalls;
1178 if (head_inst->isThreadSync()) {
1179 // Not handled for now.
1180 panic("Thread sync instructions are not handled yet.\n");
1183 // Check if the instruction caused a fault. If so, trap.
1184 Fault inst_fault = head_inst->getFault();
1186 // Stores mark themselves as completed.
1187 if (!head_inst->isStore() && inst_fault == NoFault) {
1188 head_inst->setCompleted();
1191 if (inst_fault != NoFault) {
1192 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1193 head_inst->seqNum, head_inst->pcState());
1195 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1196 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1200 head_inst->setCompleted();
1202 // If instruction has faulted, let the checker execute it and
1203 // check if it sees the same fault and control flow.
1205 // Need to check the instruction before its fault is processed
1206 cpu->checker->verify(head_inst);
1209 assert(!thread[tid]->noSquashFromTC);
1211 // Mark that we're in state update mode so that the trap's
1212 // execution doesn't generate extra squashes.
1213 thread[tid]->noSquashFromTC = true;
1215 // Execute the trap. Although it's slightly unrealistic in
1216 // terms of timing (as it doesn't wait for the full timing of
1217 // the trap event to complete before updating state), it's
1218 // needed to update the state as soon as possible. This
1219 // prevents external agents from changing any specific state
1220 // that the trap need.
1221 cpu->trap(inst_fault, tid, head_inst->staticInst);
1223 // Exit state update mode to avoid accidental updating.
1224 thread[tid]->noSquashFromTC = false;
1226 commitStatus[tid] = TrapPending;
1228 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1230 if (head_inst->traceData) {
1231 if (DTRACE(ExecFaulting)) {
1232 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1233 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1234 head_inst->traceData->dump();
1236 delete head_inst->traceData;
1237 head_inst->traceData = NULL;
1240 // Generate trap squash event.
1241 generateTrapEvent(tid);
1245 updateComInstStats(head_inst);
1248 if (thread[tid]->profile) {
1249 thread[tid]->profilePC = head_inst->instAddr();
1250 ProfileNode *node = thread[tid]->profile->consume(
1251 thread[tid]->getTC(), head_inst->staticInst);
1254 thread[tid]->profileNode = node;
1256 if (CPA::available()) {
1257 if (head_inst->isControl()) {
1258 ThreadContext *tc = thread[tid]->getTC();
1259 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1263 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1264 head_inst->seqNum, head_inst->pcState());
1265 if (head_inst->traceData) {
1266 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1267 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1268 head_inst->traceData->dump();
1269 delete head_inst->traceData;
1270 head_inst->traceData = NULL;
1272 if (head_inst->isReturn()) {
1273 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1274 head_inst->seqNum, head_inst->pcState());
1277 // Update the commit rename map
1278 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1279 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1280 head_inst->renamedDestRegIdx(i));
1283 // Finally clear the head ROB entry.
1284 rob->retireHead(tid);
1287 if (DTRACE(O3PipeView)) {
1288 head_inst->commitTick = curTick() - head_inst->fetchTick;
1292 // If this was a store, record it for this cycle.
1293 if (head_inst->isStore())
1294 committedStores[tid] = true;
1296 // Return true to indicate that we have committed an instruction.
1300 template <class Impl>
1302 DefaultCommit<Impl>::getInsts()
1304 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1306 // Read any renamed instructions and place them into the ROB.
1307 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1309 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1312 inst = fromRename->insts[inst_num];
1313 ThreadID tid = inst->threadNumber;
1315 if (!inst->isSquashed() &&
1316 commitStatus[tid] != ROBSquashing &&
1317 commitStatus[tid] != TrapPending) {
1318 changedROBNumEntries[tid] = true;
1320 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1321 inst->pcState(), inst->seqNum, tid);
1323 rob->insertInst(inst);
1325 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1327 youngestSeqNum[tid] = inst->seqNum;
1329 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1330 "squashed, skipping.\n",
1331 inst->pcState(), inst->seqNum, tid);
1336 template <class Impl>
1338 DefaultCommit<Impl>::skidInsert()
1340 DPRINTF(Commit, "Attempting to any instructions from rename into "
1343 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1344 DynInstPtr inst = fromRename->insts[inst_num];
1346 if (!inst->isSquashed()) {
1347 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1348 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1349 inst->threadNumber);
1350 skidBuffer.push(inst);
1352 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1353 "squashed, skipping.\n",
1354 inst->pcState(), inst->seqNum, inst->threadNumber);
1359 template <class Impl>
1361 DefaultCommit<Impl>::markCompletedInsts()
1363 // Grab completed insts out of the IEW instruction queue, and mark
1364 // instructions completed within the ROB.
1365 for (int inst_num = 0;
1366 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1369 if (!fromIEW->insts[inst_num]->isSquashed()) {
1370 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1372 fromIEW->insts[inst_num]->threadNumber,
1373 fromIEW->insts[inst_num]->pcState(),
1374 fromIEW->insts[inst_num]->seqNum);
1376 // Mark the instruction as ready to commit.
1377 fromIEW->insts[inst_num]->setCanCommit();
1382 template <class Impl>
1384 DefaultCommit<Impl>::robDoneSquashing()
1386 list<ThreadID>::iterator threads = activeThreads->begin();
1387 list<ThreadID>::iterator end = activeThreads->end();
1389 while (threads != end) {
1390 ThreadID tid = *threads++;
1392 if (!rob->isDoneSquashing(tid))
1399 template <class Impl>
1401 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1403 ThreadID tid = inst->threadNumber;
1405 if (!inst->isMicroop() || inst->isLastMicroop())
1406 instsCommitted[tid]++;
1407 opsCommitted[tid]++;
1409 // To match the old model, don't count nops and instruction
1410 // prefetches towards the total commit count.
1411 if (!inst->isNop() && !inst->isInstPrefetch()) {
1412 cpu->instDone(tid, inst);
1416 // Control Instructions
1418 if (inst->isControl())
1419 statComBranches[tid]++;
1422 // Memory references
1424 if (inst->isMemRef()) {
1427 if (inst->isLoad()) {
1428 statComLoads[tid]++;
1432 if (inst->isMemBarrier()) {
1433 statComMembars[tid]++;
1436 // Integer Instruction
1437 if (inst->isInteger())
1438 statComInteger[tid]++;
1440 // Floating Point Instruction
1441 if (inst->isFloating())
1442 statComFloating[tid]++;
1446 statComFunctionCalls[tid]++;
1450 ////////////////////////////////////////
1452 // SMT COMMIT POLICY MAINTAINED HERE //
1454 ////////////////////////////////////////
1455 template <class Impl>
1457 DefaultCommit<Impl>::getCommittingThread()
1459 if (numThreads > 1) {
1460 switch (commitPolicy) {
1463 //If Policy is Aggressive, commit will call
1464 //this function multiple times per
1466 return oldestReady();
1469 return roundRobin();
1472 return oldestReady();
1475 return InvalidThreadID;
1478 assert(!activeThreads->empty());
1479 ThreadID tid = activeThreads->front();
1481 if (commitStatus[tid] == Running ||
1482 commitStatus[tid] == Idle ||
1483 commitStatus[tid] == FetchTrapPending) {
1486 return InvalidThreadID;
1491 template<class Impl>
1493 DefaultCommit<Impl>::roundRobin()
1495 list<ThreadID>::iterator pri_iter = priority_list.begin();
1496 list<ThreadID>::iterator end = priority_list.end();
1498 while (pri_iter != end) {
1499 ThreadID tid = *pri_iter;
1501 if (commitStatus[tid] == Running ||
1502 commitStatus[tid] == Idle ||
1503 commitStatus[tid] == FetchTrapPending) {
1505 if (rob->isHeadReady(tid)) {
1506 priority_list.erase(pri_iter);
1507 priority_list.push_back(tid);
1516 return InvalidThreadID;
1519 template<class Impl>
1521 DefaultCommit<Impl>::oldestReady()
1523 unsigned oldest = 0;
1526 list<ThreadID>::iterator threads = activeThreads->begin();
1527 list<ThreadID>::iterator end = activeThreads->end();
1529 while (threads != end) {
1530 ThreadID tid = *threads++;
1532 if (!rob->isEmpty(tid) &&
1533 (commitStatus[tid] == Running ||
1534 commitStatus[tid] == Idle ||
1535 commitStatus[tid] == FetchTrapPending)) {
1537 if (rob->isHeadReady(tid)) {
1539 DynInstPtr head_inst = rob->readHeadInst(tid);
1544 } else if (head_inst->seqNum < oldest) {
1554 return InvalidThreadID;
1558 #endif//__CPU_O3_COMMIT_IMPL_HH__