2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
38 #include "arch/utility.hh"
39 #include "base/loader/symtab.hh"
40 #include "base/timebuf.hh"
41 #include "cpu/exetrace.hh"
42 #include "cpu/o3/commit.hh"
43 #include "cpu/o3/thread_state.hh"
46 #include "cpu/checker/cpu.hh"
50 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
54 this->setFlags(Event::AutoDelete);
59 DefaultCommit<Impl>::TrapEvent::process()
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
68 DefaultCommit<Impl>::TrapEvent::description()
74 DefaultCommit<Impl>::DefaultCommit(Params *params)
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
85 trapLatency(params->trapLatency)
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
130 template <class Impl>
132 DefaultCommit<Impl>::name() const
134 return cpu->name() + ".commit";
137 template <class Impl>
139 DefaultCommit<Impl>::regStats()
141 using namespace Stats;
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
225 template <class Impl>
227 DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
236 trapLatency = cpu->cycles(trapLatency);
239 template <class Impl>
241 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
246 template <class Impl>
248 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
260 template <class Impl>
262 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
271 template <class Impl>
273 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
282 template <class Impl>
284 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
293 template <class Impl>
295 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
297 iewStage = iew_stage;
302 DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
308 template <class Impl>
310 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
312 DPRINTF(Commit, "Setting rename map pointers.\n");
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
319 template <class Impl>
321 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
327 template <class Impl>
329 DefaultCommit<Impl>::initStage()
331 rob->setActiveThreads(activeThreads);
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
340 cpu->activityThisCycle();
343 template <class Impl>
345 DefaultCommit<Impl>::drain()
352 template <class Impl>
354 DefaultCommit<Impl>::switchOut()
357 drainPending = false;
361 template <class Impl>
363 DefaultCommit<Impl>::resume()
365 drainPending = false;
368 template <class Impl>
370 DefaultCommit<Impl>::takeOverFrom()
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
385 template <class Impl>
387 DefaultCommit<Impl>::updateStatus()
389 // reset ROB changed variable
390 std::list<unsigned>::iterator threads = activeThreads->begin();
391 std::list<unsigned>::iterator end = activeThreads->end();
393 while (threads != end) {
394 unsigned tid = *threads++;
396 changedROBNumEntries[tid] = false;
398 // Also check if any of the threads has a trap pending
399 if (commitStatus[tid] == TrapPending ||
400 commitStatus[tid] == FetchTrapPending) {
401 _nextStatus = Active;
405 if (_nextStatus == Inactive && _status == Active) {
406 DPRINTF(Activity, "Deactivating stage.\n");
407 cpu->deactivateStage(O3CPU::CommitIdx);
408 } else if (_nextStatus == Active && _status == Inactive) {
409 DPRINTF(Activity, "Activating stage.\n");
410 cpu->activateStage(O3CPU::CommitIdx);
413 _status = _nextStatus;
416 template <class Impl>
418 DefaultCommit<Impl>::setNextStatus()
422 std::list<unsigned>::iterator threads = activeThreads->begin();
423 std::list<unsigned>::iterator end = activeThreads->end();
425 while (threads != end) {
426 unsigned tid = *threads++;
428 if (commitStatus[tid] == ROBSquashing) {
433 squashCounter = squashes;
435 // If commit is currently squashing, then it will have activity for the
436 // next cycle. Set its next status as active.
438 _nextStatus = Active;
442 template <class Impl>
444 DefaultCommit<Impl>::changedROBEntries()
446 std::list<unsigned>::iterator threads = activeThreads->begin();
447 std::list<unsigned>::iterator end = activeThreads->end();
449 while (threads != end) {
450 unsigned tid = *threads++;
452 if (changedROBNumEntries[tid]) {
460 template <class Impl>
462 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
464 return rob->numFreeEntries(tid);
467 template <class Impl>
469 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
473 TrapEvent *trap = new TrapEvent(this, tid);
475 trap->schedule(curTick + trapLatency);
477 thread[tid]->trapPending = true;
480 template <class Impl>
482 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
486 tcSquash[tid] = true;
489 template <class Impl>
491 DefaultCommit<Impl>::squashAll(unsigned tid)
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
498 0 : rob->readHeadInst(tid)->seqNum - 1;;
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
511 // Send back the squash signal to tell stages that they should
513 toIEW->commitInfo[tid].squash = true;
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
519 toIEW->commitInfo[tid].branchMispredict = false;
521 toIEW->commitInfo[tid].nextPC = PC[tid];
522 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
525 template <class Impl>
527 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
531 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
533 thread[tid]->trapPending = false;
534 thread[tid]->inSyscall = false;
536 trapSquash[tid] = false;
538 commitStatus[tid] = ROBSquashing;
539 cpu->activityThisCycle();
542 template <class Impl>
544 DefaultCommit<Impl>::squashFromTC(unsigned tid)
548 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
550 thread[tid]->inSyscall = false;
551 assert(!thread[tid]->trapPending);
553 commitStatus[tid] = ROBSquashing;
554 cpu->activityThisCycle();
556 tcSquash[tid] = false;
559 template <class Impl>
561 DefaultCommit<Impl>::tick()
563 wroteToTimeBuffer = false;
564 _nextStatus = Inactive;
566 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
567 cpu->signalDrained();
568 drainPending = false;
572 if (activeThreads->empty())
575 std::list<unsigned>::iterator threads = activeThreads->begin();
576 std::list<unsigned>::iterator end = activeThreads->end();
578 // Check if any of the threads are done squashing. Change the
579 // status if they are done.
580 while (threads != end) {
581 unsigned tid = *threads++;
583 if (commitStatus[tid] == ROBSquashing) {
585 if (rob->isDoneSquashing(tid)) {
586 commitStatus[tid] = Running;
588 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
589 " insts this cycle.\n", tid);
591 toIEW->commitInfo[tid].robSquashing = true;
592 wroteToTimeBuffer = true;
599 markCompletedInsts();
601 threads = activeThreads->begin();
603 while (threads != end) {
604 unsigned tid = *threads++;
606 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
607 // The ROB has more instructions it can commit. Its next status
609 _nextStatus = Active;
611 DynInstPtr inst = rob->readHeadInst(tid);
613 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
614 " ROB and ready to commit\n",
615 tid, inst->seqNum, inst->readPC());
617 } else if (!rob->isEmpty(tid)) {
618 DynInstPtr inst = rob->readHeadInst(tid);
620 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
621 "%#x is head of ROB and not ready\n",
622 tid, inst->seqNum, inst->readPC());
625 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
626 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
630 if (wroteToTimeBuffer) {
631 DPRINTF(Activity, "Activity This Cycle.\n");
632 cpu->activityThisCycle();
638 template <class Impl>
640 DefaultCommit<Impl>::commit()
643 //////////////////////////////////////
644 // Check for interrupts
645 //////////////////////////////////////
648 if (interrupt != NoFault) {
649 // Wait until the ROB is empty and all stores have drained in
650 // order to enter the interrupt.
651 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
652 // Squash or record that I need to squash this cycle if
653 // an interrupt needed to be handled.
654 DPRINTF(Commit, "Interrupt detected.\n");
656 assert(!thread[0]->inSyscall);
657 thread[0]->inSyscall = true;
659 // CPU will handle interrupt.
660 cpu->processInterrupts(interrupt);
662 thread[0]->inSyscall = false;
664 commitStatus[0] = TrapPending;
666 // Generate trap squash event.
667 generateTrapEvent(0);
669 // Clear the interrupt now that it's been handled
670 toIEW->commitInfo[0].clearInterrupt = true;
673 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
675 } else if (cpu->check_interrupts(cpu->tcBase(0)) &&
676 commitStatus[0] != TrapPending &&
679 // Process interrupts if interrupts are enabled, not in PAL
680 // mode, and no other traps or external squashes are currently
682 // @todo: Allow other threads to handle interrupts.
684 // Get any interrupt that happened
685 interrupt = cpu->getInterrupts();
687 if (interrupt != NoFault) {
688 // Tell fetch that there is an interrupt pending. This
689 // will make fetch wait until it sees a non PAL-mode PC,
690 // at which point it stops fetching instructions.
691 toIEW->commitInfo[0].interruptPending = true;
695 #endif // FULL_SYSTEM
697 ////////////////////////////////////
698 // Check for any possible squashes, handle them first
699 ////////////////////////////////////
700 std::list<unsigned>::iterator threads = activeThreads->begin();
701 std::list<unsigned>::iterator end = activeThreads->end();
703 while (threads != end) {
704 unsigned tid = *threads++;
706 // Not sure which one takes priority. I think if we have
707 // both, that's a bad sign.
708 if (trapSquash[tid] == true) {
709 assert(!tcSquash[tid]);
711 } else if (tcSquash[tid] == true) {
715 // Squashed sequence number must be older than youngest valid
716 // instruction in the ROB. This prevents squashes from younger
717 // instructions overriding squashes from older instructions.
718 if (fromIEW->squash[tid] &&
719 commitStatus[tid] != TrapPending &&
720 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
722 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
724 fromIEW->mispredPC[tid],
725 fromIEW->squashedSeqNum[tid]);
727 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
729 fromIEW->nextPC[tid]);
731 commitStatus[tid] = ROBSquashing;
733 // If we want to include the squashing instruction in the squash,
734 // then use one older sequence number.
735 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
737 #if ISA_HAS_DELAY_SLOT
738 InstSeqNum bdelay_done_seq_num = squashed_inst;
739 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
740 bool branchMispredict = fromIEW->branchMispredict[tid];
742 // Squashing/not squashing the branch delay slot only makes
743 // sense when you're squashing from a branch, ie from a branch
745 if (branchMispredict && !squash_bdelay_slot) {
746 bdelay_done_seq_num++;
750 if (fromIEW->includeSquashInst[tid] == true) {
752 #if ISA_HAS_DELAY_SLOT
753 bdelay_done_seq_num--;
756 // All younger instructions will be squashed. Set the sequence
757 // number as the youngest instruction in the ROB.
758 youngestSeqNum[tid] = squashed_inst;
760 #if ISA_HAS_DELAY_SLOT
761 rob->squash(bdelay_done_seq_num, tid);
762 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
763 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
765 rob->squash(squashed_inst, tid);
766 toIEW->commitInfo[tid].squashDelaySlot = true;
768 changedROBNumEntries[tid] = true;
770 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
772 toIEW->commitInfo[tid].squash = true;
774 // Send back the rob squashing signal so other stages know that
775 // the ROB is in the process of squashing.
776 toIEW->commitInfo[tid].robSquashing = true;
778 toIEW->commitInfo[tid].branchMispredict =
779 fromIEW->branchMispredict[tid];
781 toIEW->commitInfo[tid].branchTaken =
782 fromIEW->branchTaken[tid];
784 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
785 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
787 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
789 if (toIEW->commitInfo[tid].branchMispredict) {
798 if (squashCounter != numThreads) {
799 // If we're not currently squashing, then get instructions.
802 // Try to commit any instructions.
805 #if ISA_HAS_DELAY_SLOT
810 //Check for any activity
811 threads = activeThreads->begin();
813 while (threads != end) {
814 unsigned tid = *threads++;
816 if (changedROBNumEntries[tid]) {
817 toIEW->commitInfo[tid].usedROB = true;
818 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
820 if (rob->isEmpty(tid)) {
821 toIEW->commitInfo[tid].emptyROB = true;
824 wroteToTimeBuffer = true;
825 changedROBNumEntries[tid] = false;
830 template <class Impl>
832 DefaultCommit<Impl>::commitInsts()
834 ////////////////////////////////////
836 // Note that commit will be handled prior to putting new
837 // instructions in the ROB so that the ROB only tries to commit
838 // instructions it has in this current cycle, and not instructions
839 // it is writing in during this cycle. Can't commit and squash
840 // things at the same time...
841 ////////////////////////////////////
843 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
845 unsigned num_committed = 0;
847 DynInstPtr head_inst;
849 // Commit as many instructions as possible until the commit bandwidth
850 // limit is reached, or it becomes impossible to commit any more.
851 while (num_committed < commitWidth) {
852 int commit_thread = getCommittingThread();
854 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
857 head_inst = rob->readHeadInst(commit_thread);
859 int tid = head_inst->threadNumber;
861 assert(tid == commit_thread);
863 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
864 head_inst->seqNum, tid);
866 // If the head instruction is squashed, it is ready to retire
867 // (be removed from the ROB) at any time.
868 if (head_inst->isSquashed()) {
870 DPRINTF(Commit, "Retiring squashed instruction from "
873 rob->retireHead(commit_thread);
875 ++commitSquashedInsts;
877 // Record that the number of ROB entries has changed.
878 changedROBNumEntries[tid] = true;
880 PC[tid] = head_inst->readPC();
881 nextPC[tid] = head_inst->readNextPC();
882 nextNPC[tid] = head_inst->readNextNPC();
884 // Increment the total number of non-speculative instructions
886 // Hack for now: it really shouldn't happen until after the
887 // commit is deemed to be successful, but this count is needed
889 thread[tid]->funcExeInst++;
891 // Try to commit the head instruction.
892 bool commit_success = commitHead(head_inst, num_committed);
894 if (commit_success) {
897 changedROBNumEntries[tid] = true;
899 // Set the doneSeqNum to the youngest committed instruction.
900 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
902 ++commitCommittedInsts;
904 // To match the old model, don't count nops and instruction
905 // prefetches towards the total commit count.
906 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
910 PC[tid] = nextPC[tid];
911 #if ISA_HAS_DELAY_SLOT
912 nextPC[tid] = nextNPC[tid];
913 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
915 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
922 // Debug statement. Checks to make sure we're not
923 // currently updating state while handling PC events.
925 assert(!thread[tid]->inSyscall &&
926 !thread[tid]->trapPending);
928 cpu->system->pcEventQueue.service(
929 thread[tid]->getTC());
931 } while (oldpc != PC[tid]);
933 DPRINTF(Commit, "PC skip function event, stopping commit\n");
938 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
939 "[tid:%i] [sn:%i].\n",
940 head_inst->readPC(), tid ,head_inst->seqNum);
946 DPRINTF(CommitRate, "%i\n", num_committed);
947 numCommittedDist.sample(num_committed);
949 if (num_committed == commitWidth) {
950 commitEligibleSamples++;
954 template <class Impl>
956 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
960 int tid = head_inst->threadNumber;
962 // If the instruction is not executed yet, then it will need extra
963 // handling. Signal backwards that it should be executed.
964 if (!head_inst->isExecuted()) {
965 // Keep this number correct. We have not yet actually executed
966 // and committed this instruction.
967 thread[tid]->funcExeInst--;
969 head_inst->setAtCommit();
971 if (head_inst->isNonSpeculative() ||
972 head_inst->isStoreConditional() ||
973 head_inst->isMemBarrier() ||
974 head_inst->isWriteBarrier()) {
976 DPRINTF(Commit, "Encountered a barrier or non-speculative "
977 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
978 head_inst->seqNum, head_inst->readPC());
980 // Hack to make sure syscalls/memory barriers/quiesces
981 // aren't executed until all stores write back their data.
982 // This direct communication shouldn't be used for
983 // anything other than this.
984 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
985 head_inst->isQuiesce()) &&
986 iewStage->hasStoresToWB())
988 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
990 } else if (inst_num > 0 || iewStage->hasStoresToWB()) {
991 DPRINTF(Commit, "Waiting to become head of commit.\n");
995 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
997 // Change the instruction so it won't try to commit again until
999 head_inst->clearCanCommit();
1001 ++commitNonSpecStalls;
1004 } else if (head_inst->isLoad()) {
1005 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1006 head_inst->seqNum, head_inst->readPC());
1008 // Send back the non-speculative instruction's sequence
1009 // number. Tell the lsq to re-execute the load.
1010 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1011 toIEW->commitInfo[tid].uncached = true;
1012 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1014 head_inst->clearCanCommit();
1018 panic("Trying to commit un-executed instruction "
1019 "of unknown type!\n");
1023 if (head_inst->isThreadSync()) {
1024 // Not handled for now.
1025 panic("Thread sync instructions are not handled yet.\n");
1028 // Stores mark themselves as completed.
1029 if (!head_inst->isStore()) {
1030 head_inst->setCompleted();
1034 // Use checker prior to updating anything due to traps or PC
1037 cpu->checker->verify(head_inst);
1041 // Check if the instruction caused a fault. If so, trap.
1042 Fault inst_fault = head_inst->getFault();
1044 // DTB will sometimes need the machine instruction for when
1045 // faults happen. So we will set it here, prior to the DTB
1046 // possibly needing it for its fault.
1047 thread[tid]->setInst(
1048 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1050 if (inst_fault != NoFault) {
1051 head_inst->setCompleted();
1052 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1053 head_inst->seqNum, head_inst->readPC());
1055 if (iewStage->hasStoresToWB() || inst_num > 0) {
1056 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1061 if (cpu->checker && head_inst->isStore()) {
1062 cpu->checker->verify(head_inst);
1066 assert(!thread[tid]->inSyscall);
1068 // Mark that we're in state update mode so that the trap's
1069 // execution doesn't generate extra squashes.
1070 thread[tid]->inSyscall = true;
1072 // Execute the trap. Although it's slightly unrealistic in
1073 // terms of timing (as it doesn't wait for the full timing of
1074 // the trap event to complete before updating state), it's
1075 // needed to update the state as soon as possible. This
1076 // prevents external agents from changing any specific state
1077 // that the trap need.
1078 cpu->trap(inst_fault, tid);
1080 // Exit state update mode to avoid accidental updating.
1081 thread[tid]->inSyscall = false;
1083 commitStatus[tid] = TrapPending;
1085 // Generate trap squash event.
1086 generateTrapEvent(tid);
1087 // warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1091 updateComInstStats(head_inst);
1094 if (thread[tid]->profile) {
1095 // bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1096 // thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1097 thread[tid]->profilePC = head_inst->readPC();
1098 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1099 head_inst->staticInst);
1102 thread[tid]->profileNode = node;
1106 if (head_inst->traceData) {
1107 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1108 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1109 head_inst->traceData->dump();
1110 delete head_inst->traceData;
1111 head_inst->traceData = NULL;
1114 // Update the commit rename map
1115 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1116 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1117 head_inst->renamedDestRegIdx(i));
1120 if (head_inst->isCopy())
1121 panic("Should not commit any copy instructions!");
1123 // Finally clear the head ROB entry.
1124 rob->retireHead(tid);
1126 // Return true to indicate that we have committed an instruction.
1130 template <class Impl>
1132 DefaultCommit<Impl>::getInsts()
1134 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1136 #if ISA_HAS_DELAY_SLOT
1137 // Read any renamed instructions and place them into the ROB.
1138 int insts_to_process = std::min((int)renameWidth,
1139 (int)(fromRename->size + skidBuffer.size()));
1142 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1143 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1146 // Read any renamed instructions and place them into the ROB.
1147 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1151 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1154 #if ISA_HAS_DELAY_SLOT
1155 // Get insts from skidBuffer or from Rename
1156 if (skidBuffer.size() > 0) {
1157 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1158 inst = skidBuffer.front();
1161 DPRINTF(Commit, "Grabbing rename inst.\n");
1162 inst = fromRename->insts[rename_idx++];
1165 inst = fromRename->insts[inst_num];
1167 int tid = inst->threadNumber;
1169 if (!inst->isSquashed() &&
1170 commitStatus[tid] != ROBSquashing) {
1171 changedROBNumEntries[tid] = true;
1173 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1174 inst->readPC(), inst->seqNum, tid);
1176 rob->insertInst(inst);
1178 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1180 youngestSeqNum[tid] = inst->seqNum;
1182 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1183 "squashed, skipping.\n",
1184 inst->readPC(), inst->seqNum, tid);
1188 #if ISA_HAS_DELAY_SLOT
1189 if (rename_idx < fromRename->size) {
1190 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1193 rename_idx < fromRename->size;
1195 DynInstPtr inst = fromRename->insts[rename_idx];
1197 if (!inst->isSquashed()) {
1198 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1199 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1200 inst->threadNumber);
1201 skidBuffer.push(inst);
1203 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1204 "squashed, skipping.\n",
1205 inst->readPC(), inst->seqNum, inst->threadNumber);
1213 template <class Impl>
1215 DefaultCommit<Impl>::skidInsert()
1217 DPRINTF(Commit, "Attempting to any instructions from rename into "
1220 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1221 DynInstPtr inst = fromRename->insts[inst_num];
1223 if (!inst->isSquashed()) {
1224 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1225 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1226 inst->threadNumber);
1227 skidBuffer.push(inst);
1229 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1230 "squashed, skipping.\n",
1231 inst->readPC(), inst->seqNum, inst->threadNumber);
1236 template <class Impl>
1238 DefaultCommit<Impl>::markCompletedInsts()
1240 // Grab completed insts out of the IEW instruction queue, and mark
1241 // instructions completed within the ROB.
1242 for (int inst_num = 0;
1243 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1246 if (!fromIEW->insts[inst_num]->isSquashed()) {
1247 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1249 fromIEW->insts[inst_num]->threadNumber,
1250 fromIEW->insts[inst_num]->readPC(),
1251 fromIEW->insts[inst_num]->seqNum);
1253 // Mark the instruction as ready to commit.
1254 fromIEW->insts[inst_num]->setCanCommit();
1259 template <class Impl>
1261 DefaultCommit<Impl>::robDoneSquashing()
1263 std::list<unsigned>::iterator threads = activeThreads->begin();
1264 std::list<unsigned>::iterator end = activeThreads->end();
1266 while (threads != end) {
1267 unsigned tid = *threads++;
1269 if (!rob->isDoneSquashing(tid))
1276 template <class Impl>
1278 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1280 unsigned thread = inst->threadNumber;
1283 // Pick off the software prefetches
1286 if (inst->isDataPrefetch()) {
1287 statComSwp[thread]++;
1289 statComInst[thread]++;
1292 statComInst[thread]++;
1296 // Control Instructions
1298 if (inst->isControl())
1299 statComBranches[thread]++;
1302 // Memory references
1304 if (inst->isMemRef()) {
1305 statComRefs[thread]++;
1307 if (inst->isLoad()) {
1308 statComLoads[thread]++;
1312 if (inst->isMemBarrier()) {
1313 statComMembars[thread]++;
1317 ////////////////////////////////////////
1319 // SMT COMMIT POLICY MAINTAINED HERE //
1321 ////////////////////////////////////////
1322 template <class Impl>
1324 DefaultCommit<Impl>::getCommittingThread()
1326 if (numThreads > 1) {
1327 switch (commitPolicy) {
1330 //If Policy is Aggressive, commit will call
1331 //this function multiple times per
1333 return oldestReady();
1336 return roundRobin();
1339 return oldestReady();
1345 assert(!activeThreads->empty());
1346 int tid = activeThreads->front();
1348 if (commitStatus[tid] == Running ||
1349 commitStatus[tid] == Idle ||
1350 commitStatus[tid] == FetchTrapPending) {
1358 template<class Impl>
1360 DefaultCommit<Impl>::roundRobin()
1362 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1363 std::list<unsigned>::iterator end = priority_list.end();
1365 while (pri_iter != end) {
1366 unsigned tid = *pri_iter;
1368 if (commitStatus[tid] == Running ||
1369 commitStatus[tid] == Idle ||
1370 commitStatus[tid] == FetchTrapPending) {
1372 if (rob->isHeadReady(tid)) {
1373 priority_list.erase(pri_iter);
1374 priority_list.push_back(tid);
1386 template<class Impl>
1388 DefaultCommit<Impl>::oldestReady()
1390 unsigned oldest = 0;
1393 std::list<unsigned>::iterator threads = activeThreads->begin();
1394 std::list<unsigned>::iterator end = activeThreads->end();
1396 while (threads != end) {
1397 unsigned tid = *threads++;
1399 if (!rob->isEmpty(tid) &&
1400 (commitStatus[tid] == Running ||
1401 commitStatus[tid] == Idle ||
1402 commitStatus[tid] == FetchTrapPending)) {
1404 if (rob->isHeadReady(tid)) {
1406 DynInstPtr head_inst = rob->readHeadInst(tid);
1411 } else if (head_inst->seqNum < oldest) {