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43 #ifndef __CPU_O3_COMMIT_IMPL_HH__
44 #define __CPU_O3_COMMIT_IMPL_HH__
50 #include "arch/utility.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/cp_annotate.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/checker/cpu.hh"
55 #include "cpu/o3/commit.hh"
56 #include "cpu/o3/thread_state.hh"
57 #include "cpu/base.hh"
58 #include "cpu/exetrace.hh"
59 #include "cpu/timebuf.hh"
60 #include "debug/Activity.hh"
61 #include "debug/Commit.hh"
62 #include "debug/CommitRate.hh"
63 #include "debug/Drain.hh"
64 #include "debug/ExecFaulting.hh"
65 #include "debug/O3PipeView.hh"
66 #include "params/DerivO3CPU.hh"
67 #include "sim/faults.hh"
68 #include "sim/full_system.hh"
73 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
81 DefaultCommit<Impl>::TrapEvent::process()
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
90 DefaultCommit<Impl>::TrapEvent::description() const
96 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
107 trapLatency(params->trapLatency),
108 canHandleInterrupts(true),
109 avoidQuiesceLiveLock(false)
112 _nextStatus = Inactive;
113 std::string policy = params->smtCommitPolicy;
115 //Convert string to lowercase
116 std::transform(policy.begin(), policy.end(), policy.begin(),
117 (int(*)(int)) tolower);
119 //Assign commit policy
120 if (policy == "aggressive"){
121 commitPolicy = Aggressive;
123 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
124 } else if (policy == "roundrobin"){
125 commitPolicy = RoundRobin;
127 //Set-Up Priority List
128 for (ThreadID tid = 0; tid < numThreads; tid++) {
129 priority_list.push_back(tid);
132 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
133 } else if (policy == "oldestready"){
134 commitPolicy = OldestReady;
136 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
138 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
139 "RoundRobin,OldestReady}");
142 for (ThreadID tid = 0; tid < numThreads; tid++) {
143 commitStatus[tid] = Idle;
144 changedROBNumEntries[tid] = false;
145 checkEmptyROB[tid] = false;
146 trapInFlight[tid] = false;
147 committedStores[tid] = false;
148 trapSquash[tid] = false;
149 tcSquash[tid] = false;
151 lastCommitedSeqNum[tid] = 0;
152 squashAfterInst[tid] = NULL;
157 template <class Impl>
159 DefaultCommit<Impl>::name() const
161 return cpu->name() + ".commit";
164 template <class Impl>
166 DefaultCommit<Impl>::regStats()
168 using namespace Stats;
170 .name(name() + ".commitSquashedInsts")
171 .desc("The number of squashed insts skipped by commit")
172 .prereq(commitSquashedInsts);
174 .name(name() + ".commitSquashEvents")
175 .desc("The number of times commit is told to squash")
176 .prereq(commitSquashEvents);
178 .name(name() + ".commitNonSpecStalls")
179 .desc("The number of times commit has been forced to stall to "
180 "communicate backwards")
181 .prereq(commitNonSpecStalls);
183 .name(name() + ".branchMispredicts")
184 .desc("The number of times a branch was mispredicted")
185 .prereq(branchMispredicts);
187 .init(0,commitWidth,1)
188 .name(name() + ".committed_per_cycle")
189 .desc("Number of insts commited each cycle")
194 .init(cpu->numThreads)
195 .name(name() + ".committedInsts")
196 .desc("Number of instructions committed")
201 .init(cpu->numThreads)
202 .name(name() + ".committedOps")
203 .desc("Number of ops (including micro ops) committed")
208 .init(cpu->numThreads)
209 .name(name() + ".swp_count")
210 .desc("Number of s/w prefetches committed")
215 .init(cpu->numThreads)
216 .name(name() + ".refs")
217 .desc("Number of memory references committed")
222 .init(cpu->numThreads)
223 .name(name() + ".loads")
224 .desc("Number of loads committed")
229 .init(cpu->numThreads)
230 .name(name() + ".membars")
231 .desc("Number of memory barriers committed")
236 .init(cpu->numThreads)
237 .name(name() + ".branches")
238 .desc("Number of branches committed")
243 .init(cpu->numThreads)
244 .name(name() + ".fp_insts")
245 .desc("Number of committed floating point instructions.")
250 .init(cpu->numThreads)
251 .name(name()+".int_insts")
252 .desc("Number of committed integer instructions.")
257 .init(cpu->numThreads)
258 .name(name()+".function_calls")
259 .desc("Number of function calls committed.")
264 .init(cpu->numThreads)
265 .name(name() + ".bw_limited")
266 .desc("number of insts not committed due to BW limits")
270 commitEligibleSamples
271 .name(name() + ".bw_lim_events")
272 .desc("number cycles where commit BW limit reached")
276 template <class Impl>
278 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
283 template <class Impl>
285 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
289 // Setup wire to send information back to IEW.
290 toIEW = timeBuffer->getWire(0);
292 // Setup wire to read data from IEW (for the ROB).
293 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
296 template <class Impl>
298 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
302 // Setup wire to get instructions from rename (for the ROB).
303 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
306 template <class Impl>
308 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
310 renameQueue = rq_ptr;
312 // Setup wire to get instructions from rename (for the ROB).
313 fromRename = renameQueue->getWire(-renameToROBDelay);
316 template <class Impl>
318 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
322 // Setup wire to get instructions from IEW.
323 fromIEW = iewQueue->getWire(-iewToCommitDelay);
326 template <class Impl>
328 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
330 iewStage = iew_stage;
335 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
337 activeThreads = at_ptr;
340 template <class Impl>
342 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
344 for (ThreadID tid = 0; tid < numThreads; tid++)
345 renameMap[tid] = &rm_ptr[tid];
348 template <class Impl>
350 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
355 template <class Impl>
357 DefaultCommit<Impl>::startupStage()
359 rob->setActiveThreads(activeThreads);
362 // Broadcast the number of free entries.
363 for (ThreadID tid = 0; tid < numThreads; tid++) {
364 toIEW->commitInfo[tid].usedROB = true;
365 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
366 toIEW->commitInfo[tid].emptyROB = true;
369 // Commit must broadcast the number of free entries it has at the
370 // start of the simulation, so it starts as active.
371 cpu->activateStage(O3CPU::CommitIdx);
373 cpu->activityThisCycle();
376 template <class Impl>
378 DefaultCommit<Impl>::drain()
383 template <class Impl>
385 DefaultCommit<Impl>::drainResume()
387 drainPending = false;
390 template <class Impl>
392 DefaultCommit<Impl>::drainSanityCheck() const
395 rob->drainSanityCheck();
398 template <class Impl>
400 DefaultCommit<Impl>::isDrained() const
402 /* Make sure no one is executing microcode. There are two reasons
404 * - Hardware virtualized CPUs can't switch into the middle of a
405 * microcode sequence.
406 * - The current fetch implementation will most likely get very
407 * confused if it tries to start fetching an instruction that
408 * is executing in the middle of a ucode sequence that changes
409 * address mappings. This can happen on for example x86.
411 for (ThreadID tid = 0; tid < numThreads; tid++) {
412 if (pc[tid].microPC() != 0)
416 /* Make sure that all instructions have finished committing before
417 * declaring the system as drained. We want the pipeline to be
418 * completely empty when we declare the CPU to be drained. This
419 * makes debugging easier since CPU handover and restoring from a
420 * checkpoint with a different CPU should have the same timing.
422 return rob->isEmpty() &&
423 interrupt == NoFault;
426 template <class Impl>
428 DefaultCommit<Impl>::takeOverFrom()
431 _nextStatus = Inactive;
432 for (ThreadID tid = 0; tid < numThreads; tid++) {
433 commitStatus[tid] = Idle;
434 changedROBNumEntries[tid] = false;
435 trapSquash[tid] = false;
436 tcSquash[tid] = false;
437 squashAfterInst[tid] = NULL;
443 template <class Impl>
445 DefaultCommit<Impl>::updateStatus()
447 // reset ROB changed variable
448 list<ThreadID>::iterator threads = activeThreads->begin();
449 list<ThreadID>::iterator end = activeThreads->end();
451 while (threads != end) {
452 ThreadID tid = *threads++;
454 changedROBNumEntries[tid] = false;
456 // Also check if any of the threads has a trap pending
457 if (commitStatus[tid] == TrapPending ||
458 commitStatus[tid] == FetchTrapPending) {
459 _nextStatus = Active;
463 if (_nextStatus == Inactive && _status == Active) {
464 DPRINTF(Activity, "Deactivating stage.\n");
465 cpu->deactivateStage(O3CPU::CommitIdx);
466 } else if (_nextStatus == Active && _status == Inactive) {
467 DPRINTF(Activity, "Activating stage.\n");
468 cpu->activateStage(O3CPU::CommitIdx);
471 _status = _nextStatus;
474 template <class Impl>
476 DefaultCommit<Impl>::setNextStatus()
480 list<ThreadID>::iterator threads = activeThreads->begin();
481 list<ThreadID>::iterator end = activeThreads->end();
483 while (threads != end) {
484 ThreadID tid = *threads++;
486 if (commitStatus[tid] == ROBSquashing) {
491 squashCounter = squashes;
493 // If commit is currently squashing, then it will have activity for the
494 // next cycle. Set its next status as active.
496 _nextStatus = Active;
500 template <class Impl>
502 DefaultCommit<Impl>::changedROBEntries()
504 list<ThreadID>::iterator threads = activeThreads->begin();
505 list<ThreadID>::iterator end = activeThreads->end();
507 while (threads != end) {
508 ThreadID tid = *threads++;
510 if (changedROBNumEntries[tid]) {
518 template <class Impl>
520 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
522 return rob->numFreeEntries(tid);
525 template <class Impl>
527 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
529 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
531 TrapEvent *trap = new TrapEvent(this, tid);
533 cpu->schedule(trap, cpu->clockEdge(trapLatency));
534 trapInFlight[tid] = true;
535 thread[tid]->trapPending = true;
538 template <class Impl>
540 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
542 assert(!trapInFlight[tid]);
543 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
545 tcSquash[tid] = true;
548 template <class Impl>
550 DefaultCommit<Impl>::squashAll(ThreadID tid)
552 // If we want to include the squashing instruction in the squash,
553 // then use one older sequence number.
554 // Hopefully this doesn't mess things up. Basically I want to squash
555 // all instructions of this thread.
556 InstSeqNum squashed_inst = rob->isEmpty() ?
557 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
559 // All younger instructions will be squashed. Set the sequence
560 // number as the youngest instruction in the ROB (0 in this case.
561 // Hopefully nothing breaks.)
562 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
564 rob->squash(squashed_inst, tid);
565 changedROBNumEntries[tid] = true;
567 // Send back the sequence number of the squashed instruction.
568 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
570 // Send back the squash signal to tell stages that they should
572 toIEW->commitInfo[tid].squash = true;
574 // Send back the rob squashing signal so other stages know that
575 // the ROB is in the process of squashing.
576 toIEW->commitInfo[tid].robSquashing = true;
578 toIEW->commitInfo[tid].mispredictInst = NULL;
579 toIEW->commitInfo[tid].squashInst = NULL;
581 toIEW->commitInfo[tid].pc = pc[tid];
584 template <class Impl>
586 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
590 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
592 thread[tid]->trapPending = false;
593 thread[tid]->noSquashFromTC = false;
594 trapInFlight[tid] = false;
596 trapSquash[tid] = false;
598 commitStatus[tid] = ROBSquashing;
599 cpu->activityThisCycle();
602 template <class Impl>
604 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
608 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
610 thread[tid]->noSquashFromTC = false;
611 assert(!thread[tid]->trapPending);
613 commitStatus[tid] = ROBSquashing;
614 cpu->activityThisCycle();
616 tcSquash[tid] = false;
619 template <class Impl>
621 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
623 DPRINTF(Commit, "Squashing after squash after request, "
624 "restarting at PC %s\n", pc[tid]);
627 // Make sure to inform the fetch stage of which instruction caused
628 // the squash. It'll try to re-fetch an instruction executing in
629 // microcode unless this is set.
630 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
631 squashAfterInst[tid] = NULL;
633 commitStatus[tid] = ROBSquashing;
634 cpu->activityThisCycle();
637 template <class Impl>
639 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
641 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
642 tid, head_inst->seqNum);
644 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
645 commitStatus[tid] = SquashAfterPending;
646 squashAfterInst[tid] = head_inst;
649 template <class Impl>
651 DefaultCommit<Impl>::tick()
653 wroteToTimeBuffer = false;
654 _nextStatus = Inactive;
656 if (activeThreads->empty())
659 list<ThreadID>::iterator threads = activeThreads->begin();
660 list<ThreadID>::iterator end = activeThreads->end();
662 // Check if any of the threads are done squashing. Change the
663 // status if they are done.
664 while (threads != end) {
665 ThreadID tid = *threads++;
667 // Clear the bit saying if the thread has committed stores
669 committedStores[tid] = false;
671 if (commitStatus[tid] == ROBSquashing) {
673 if (rob->isDoneSquashing(tid)) {
674 commitStatus[tid] = Running;
676 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
677 " insts this cycle.\n", tid);
679 toIEW->commitInfo[tid].robSquashing = true;
680 wroteToTimeBuffer = true;
687 markCompletedInsts();
689 threads = activeThreads->begin();
691 while (threads != end) {
692 ThreadID tid = *threads++;
694 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
695 // The ROB has more instructions it can commit. Its next status
697 _nextStatus = Active;
699 DynInstPtr inst = rob->readHeadInst(tid);
701 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
702 " ROB and ready to commit\n",
703 tid, inst->seqNum, inst->pcState());
705 } else if (!rob->isEmpty(tid)) {
706 DynInstPtr inst = rob->readHeadInst(tid);
708 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
709 "%s is head of ROB and not ready\n",
710 tid, inst->seqNum, inst->pcState());
713 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
714 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
718 if (wroteToTimeBuffer) {
719 DPRINTF(Activity, "Activity This Cycle.\n");
720 cpu->activityThisCycle();
726 template <class Impl>
728 DefaultCommit<Impl>::handleInterrupt()
730 // Verify that we still have an interrupt to handle
731 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
732 DPRINTF(Commit, "Pending interrupt is cleared by master before "
733 "it got handled. Restart fetching from the orig path.\n");
734 toIEW->commitInfo[0].clearInterrupt = true;
736 avoidQuiesceLiveLock = true;
740 // Wait until all in flight instructions are finished before enterring
742 if (canHandleInterrupts && cpu->instList.empty()) {
743 // Squash or record that I need to squash this cycle if
744 // an interrupt needed to be handled.
745 DPRINTF(Commit, "Interrupt detected.\n");
747 // Clear the interrupt now that it's going to be handled
748 toIEW->commitInfo[0].clearInterrupt = true;
750 assert(!thread[0]->noSquashFromTC);
751 thread[0]->noSquashFromTC = true;
754 cpu->checker->handlePendingInt();
757 // CPU will handle interrupt. Note that we ignore the local copy of
758 // interrupt. This is because the local copy may no longer be the
759 // interrupt that the interrupt controller thinks is being handled.
760 cpu->processInterrupts(cpu->getInterrupts());
762 thread[0]->noSquashFromTC = false;
764 commitStatus[0] = TrapPending;
766 // Generate trap squash event.
767 generateTrapEvent(0);
770 avoidQuiesceLiveLock = false;
772 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
773 "flight, ROB is %sempty\n",
774 canHandleInterrupts ? "not " : "",
775 cpu->instList.empty() ? "" : "not " );
779 template <class Impl>
781 DefaultCommit<Impl>::propagateInterrupt()
783 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
787 // Process interrupts if interrupts are enabled, not in PAL
788 // mode, and no other traps or external squashes are currently
790 // @todo: Allow other threads to handle interrupts.
792 // Get any interrupt that happened
793 interrupt = cpu->getInterrupts();
795 // Tell fetch that there is an interrupt pending. This
796 // will make fetch wait until it sees a non PAL-mode PC,
797 // at which point it stops fetching instructions.
798 if (interrupt != NoFault)
799 toIEW->commitInfo[0].interruptPending = true;
802 template <class Impl>
804 DefaultCommit<Impl>::commit()
807 // Check if we have a interrupt and get read to handle it
808 if (cpu->checkInterrupts(cpu->tcBase(0)))
809 propagateInterrupt();
812 ////////////////////////////////////
813 // Check for any possible squashes, handle them first
814 ////////////////////////////////////
815 list<ThreadID>::iterator threads = activeThreads->begin();
816 list<ThreadID>::iterator end = activeThreads->end();
818 while (threads != end) {
819 ThreadID tid = *threads++;
821 // Not sure which one takes priority. I think if we have
822 // both, that's a bad sign.
823 if (trapSquash[tid] == true) {
824 assert(!tcSquash[tid]);
826 } else if (tcSquash[tid] == true) {
827 assert(commitStatus[tid] != TrapPending);
829 } else if (commitStatus[tid] == SquashAfterPending) {
830 // A squash from the previous cycle of the commit stage (i.e.,
831 // commitInsts() called squashAfter) is pending. Squash the
833 squashFromSquashAfter(tid);
836 // Squashed sequence number must be older than youngest valid
837 // instruction in the ROB. This prevents squashes from younger
838 // instructions overriding squashes from older instructions.
839 if (fromIEW->squash[tid] &&
840 commitStatus[tid] != TrapPending &&
841 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
843 if (fromIEW->mispredictInst[tid]) {
845 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
847 fromIEW->mispredictInst[tid]->instAddr(),
848 fromIEW->squashedSeqNum[tid]);
851 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
852 tid, fromIEW->squashedSeqNum[tid]);
855 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
857 fromIEW->pc[tid].nextInstAddr());
859 commitStatus[tid] = ROBSquashing;
861 // If we want to include the squashing instruction in the squash,
862 // then use one older sequence number.
863 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
865 if (fromIEW->includeSquashInst[tid] == true) {
869 // All younger instructions will be squashed. Set the sequence
870 // number as the youngest instruction in the ROB.
871 youngestSeqNum[tid] = squashed_inst;
873 rob->squash(squashed_inst, tid);
874 changedROBNumEntries[tid] = true;
876 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
878 toIEW->commitInfo[tid].squash = true;
880 // Send back the rob squashing signal so other stages know that
881 // the ROB is in the process of squashing.
882 toIEW->commitInfo[tid].robSquashing = true;
884 toIEW->commitInfo[tid].mispredictInst =
885 fromIEW->mispredictInst[tid];
886 toIEW->commitInfo[tid].branchTaken =
887 fromIEW->branchTaken[tid];
888 toIEW->commitInfo[tid].squashInst =
889 rob->findInst(tid, squashed_inst);
890 if (toIEW->commitInfo[tid].mispredictInst) {
891 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
892 toIEW->commitInfo[tid].branchTaken = true;
896 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
898 if (toIEW->commitInfo[tid].mispredictInst) {
907 if (squashCounter != numThreads) {
908 // If we're not currently squashing, then get instructions.
911 // Try to commit any instructions.
915 //Check for any activity
916 threads = activeThreads->begin();
918 while (threads != end) {
919 ThreadID tid = *threads++;
921 if (changedROBNumEntries[tid]) {
922 toIEW->commitInfo[tid].usedROB = true;
923 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
925 wroteToTimeBuffer = true;
926 changedROBNumEntries[tid] = false;
927 if (rob->isEmpty(tid))
928 checkEmptyROB[tid] = true;
931 // ROB is only considered "empty" for previous stages if: a)
932 // ROB is empty, b) there are no outstanding stores, c) IEW
933 // stage has received any information regarding stores that
935 // c) is checked by making sure to not consider the ROB empty
936 // on the same cycle as when stores have been committed.
937 // @todo: Make this handle multi-cycle communication between
939 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
940 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
941 checkEmptyROB[tid] = false;
942 toIEW->commitInfo[tid].usedROB = true;
943 toIEW->commitInfo[tid].emptyROB = true;
944 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
945 wroteToTimeBuffer = true;
951 template <class Impl>
953 DefaultCommit<Impl>::commitInsts()
955 ////////////////////////////////////
957 // Note that commit will be handled prior to putting new
958 // instructions in the ROB so that the ROB only tries to commit
959 // instructions it has in this current cycle, and not instructions
960 // it is writing in during this cycle. Can't commit and squash
961 // things at the same time...
962 ////////////////////////////////////
964 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
966 unsigned num_committed = 0;
968 DynInstPtr head_inst;
970 // Commit as many instructions as possible until the commit bandwidth
971 // limit is reached, or it becomes impossible to commit any more.
972 while (num_committed < commitWidth) {
973 // Check for any interrupt that we've already squashed for
974 // and start processing it.
975 if (interrupt != NoFault)
978 int commit_thread = getCommittingThread();
980 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
983 head_inst = rob->readHeadInst(commit_thread);
985 ThreadID tid = head_inst->threadNumber;
987 assert(tid == commit_thread);
989 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
990 head_inst->seqNum, tid);
992 // If the head instruction is squashed, it is ready to retire
993 // (be removed from the ROB) at any time.
994 if (head_inst->isSquashed()) {
996 DPRINTF(Commit, "Retiring squashed instruction from "
999 rob->retireHead(commit_thread);
1001 ++commitSquashedInsts;
1003 // Record that the number of ROB entries has changed.
1004 changedROBNumEntries[tid] = true;
1006 pc[tid] = head_inst->pcState();
1008 // Increment the total number of non-speculative instructions
1010 // Hack for now: it really shouldn't happen until after the
1011 // commit is deemed to be successful, but this count is needed
1013 thread[tid]->funcExeInst++;
1015 // Try to commit the head instruction.
1016 bool commit_success = commitHead(head_inst, num_committed);
1018 if (commit_success) {
1021 changedROBNumEntries[tid] = true;
1023 // Set the doneSeqNum to the youngest committed instruction.
1024 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1027 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1028 ((THE_ISA != ALPHA_ISA) ||
1029 (!(pc[0].instAddr() & 0x3)));
1032 // Updates misc. registers.
1033 head_inst->updateMiscRegs();
1035 cpu->traceFunctions(pc[tid].instAddr());
1037 TheISA::advancePC(pc[tid], head_inst->staticInst);
1039 // Keep track of the last sequence number commited
1040 lastCommitedSeqNum[tid] = head_inst->seqNum;
1042 // If this is an instruction that doesn't play nicely with
1043 // others squash everything and restart fetch
1044 if (head_inst->isSquashAfter())
1045 squashAfter(tid, head_inst);
1048 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1049 if (pc[tid].microPC() == 0 && interrupt == NoFault) {
1050 squashAfter(tid, head_inst);
1051 cpu->commitDrained(tid);
1057 // Debug statement. Checks to make sure we're not
1058 // currently updating state while handling PC events.
1059 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1061 oldpc = pc[tid].instAddr();
1062 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1064 } while (oldpc != pc[tid].instAddr());
1067 "PC skip function event, stopping commit\n");
1071 // Check if an instruction just enabled interrupts and we've
1072 // previously had an interrupt pending that was not handled
1073 // because interrupts were subsequently disabled before the
1074 // pipeline reached a place to handle the interrupt. In that
1075 // case squash now to make sure the interrupt is handled.
1077 // If we don't do this, we might end up in a live lock situation
1078 if (!interrupt && avoidQuiesceLiveLock &&
1079 (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
1080 cpu->checkInterrupts(cpu->tcBase(0)))
1081 squashAfter(tid, head_inst);
1083 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1084 "[tid:%i] [sn:%i].\n",
1085 head_inst->pcState(), tid ,head_inst->seqNum);
1091 DPRINTF(CommitRate, "%i\n", num_committed);
1092 numCommittedDist.sample(num_committed);
1094 if (num_committed == commitWidth) {
1095 commitEligibleSamples++;
1099 template <class Impl>
1101 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1105 ThreadID tid = head_inst->threadNumber;
1107 // If the instruction is not executed yet, then it will need extra
1108 // handling. Signal backwards that it should be executed.
1109 if (!head_inst->isExecuted()) {
1110 // Keep this number correct. We have not yet actually executed
1111 // and committed this instruction.
1112 thread[tid]->funcExeInst--;
1114 if (head_inst->isNonSpeculative() ||
1115 head_inst->isStoreConditional() ||
1116 head_inst->isMemBarrier() ||
1117 head_inst->isWriteBarrier()) {
1119 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1120 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1121 head_inst->seqNum, head_inst->pcState());
1123 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1124 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1128 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1130 // Change the instruction so it won't try to commit again until
1132 head_inst->clearCanCommit();
1134 ++commitNonSpecStalls;
1137 } else if (head_inst->isLoad()) {
1138 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1139 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1143 assert(head_inst->uncacheable());
1144 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1145 head_inst->seqNum, head_inst->pcState());
1147 // Send back the non-speculative instruction's sequence
1148 // number. Tell the lsq to re-execute the load.
1149 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1150 toIEW->commitInfo[tid].uncached = true;
1151 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1153 head_inst->clearCanCommit();
1157 panic("Trying to commit un-executed instruction "
1158 "of unknown type!\n");
1162 if (head_inst->isThreadSync()) {
1163 // Not handled for now.
1164 panic("Thread sync instructions are not handled yet.\n");
1167 // Check if the instruction caused a fault. If so, trap.
1168 Fault inst_fault = head_inst->getFault();
1170 // Stores mark themselves as completed.
1171 if (!head_inst->isStore() && inst_fault == NoFault) {
1172 head_inst->setCompleted();
1175 // Use checker prior to updating anything due to traps or PC
1178 cpu->checker->verify(head_inst);
1181 if (inst_fault != NoFault) {
1182 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1183 head_inst->seqNum, head_inst->pcState());
1185 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1186 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1190 head_inst->setCompleted();
1193 // Need to check the instruction before its fault is processed
1194 cpu->checker->verify(head_inst);
1197 assert(!thread[tid]->noSquashFromTC);
1199 // Mark that we're in state update mode so that the trap's
1200 // execution doesn't generate extra squashes.
1201 thread[tid]->noSquashFromTC = true;
1203 // Execute the trap. Although it's slightly unrealistic in
1204 // terms of timing (as it doesn't wait for the full timing of
1205 // the trap event to complete before updating state), it's
1206 // needed to update the state as soon as possible. This
1207 // prevents external agents from changing any specific state
1208 // that the trap need.
1209 cpu->trap(inst_fault, tid, head_inst->staticInst);
1211 // Exit state update mode to avoid accidental updating.
1212 thread[tid]->noSquashFromTC = false;
1214 commitStatus[tid] = TrapPending;
1216 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1218 if (head_inst->traceData) {
1219 if (DTRACE(ExecFaulting)) {
1220 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1221 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1222 head_inst->traceData->dump();
1224 delete head_inst->traceData;
1225 head_inst->traceData = NULL;
1228 // Generate trap squash event.
1229 generateTrapEvent(tid);
1233 updateComInstStats(head_inst);
1236 if (thread[tid]->profile) {
1237 thread[tid]->profilePC = head_inst->instAddr();
1238 ProfileNode *node = thread[tid]->profile->consume(
1239 thread[tid]->getTC(), head_inst->staticInst);
1242 thread[tid]->profileNode = node;
1244 if (CPA::available()) {
1245 if (head_inst->isControl()) {
1246 ThreadContext *tc = thread[tid]->getTC();
1247 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1251 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1252 head_inst->seqNum, head_inst->pcState());
1253 if (head_inst->traceData) {
1254 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1255 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1256 head_inst->traceData->dump();
1257 delete head_inst->traceData;
1258 head_inst->traceData = NULL;
1260 if (head_inst->isReturn()) {
1261 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1262 head_inst->seqNum, head_inst->pcState());
1265 // Update the commit rename map
1266 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1267 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1268 head_inst->renamedDestRegIdx(i));
1271 // Finally clear the head ROB entry.
1272 rob->retireHead(tid);
1275 if (DTRACE(O3PipeView)) {
1276 head_inst->commitTick = curTick() - head_inst->fetchTick;
1280 // If this was a store, record it for this cycle.
1281 if (head_inst->isStore())
1282 committedStores[tid] = true;
1284 // Return true to indicate that we have committed an instruction.
1288 template <class Impl>
1290 DefaultCommit<Impl>::getInsts()
1292 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1294 // Read any renamed instructions and place them into the ROB.
1295 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1297 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1300 inst = fromRename->insts[inst_num];
1301 ThreadID tid = inst->threadNumber;
1303 if (!inst->isSquashed() &&
1304 commitStatus[tid] != ROBSquashing &&
1305 commitStatus[tid] != TrapPending) {
1306 changedROBNumEntries[tid] = true;
1308 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1309 inst->pcState(), inst->seqNum, tid);
1311 rob->insertInst(inst);
1313 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1315 youngestSeqNum[tid] = inst->seqNum;
1317 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1318 "squashed, skipping.\n",
1319 inst->pcState(), inst->seqNum, tid);
1324 template <class Impl>
1326 DefaultCommit<Impl>::skidInsert()
1328 DPRINTF(Commit, "Attempting to any instructions from rename into "
1331 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1332 DynInstPtr inst = fromRename->insts[inst_num];
1334 if (!inst->isSquashed()) {
1335 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1336 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1337 inst->threadNumber);
1338 skidBuffer.push(inst);
1340 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1341 "squashed, skipping.\n",
1342 inst->pcState(), inst->seqNum, inst->threadNumber);
1347 template <class Impl>
1349 DefaultCommit<Impl>::markCompletedInsts()
1351 // Grab completed insts out of the IEW instruction queue, and mark
1352 // instructions completed within the ROB.
1353 for (int inst_num = 0;
1354 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1357 if (!fromIEW->insts[inst_num]->isSquashed()) {
1358 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1360 fromIEW->insts[inst_num]->threadNumber,
1361 fromIEW->insts[inst_num]->pcState(),
1362 fromIEW->insts[inst_num]->seqNum);
1364 // Mark the instruction as ready to commit.
1365 fromIEW->insts[inst_num]->setCanCommit();
1370 template <class Impl>
1372 DefaultCommit<Impl>::robDoneSquashing()
1374 list<ThreadID>::iterator threads = activeThreads->begin();
1375 list<ThreadID>::iterator end = activeThreads->end();
1377 while (threads != end) {
1378 ThreadID tid = *threads++;
1380 if (!rob->isDoneSquashing(tid))
1387 template <class Impl>
1389 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1391 ThreadID tid = inst->threadNumber;
1393 if (!inst->isMicroop() || inst->isLastMicroop())
1394 instsCommitted[tid]++;
1395 opsCommitted[tid]++;
1397 // To match the old model, don't count nops and instruction
1398 // prefetches towards the total commit count.
1399 if (!inst->isNop() && !inst->isInstPrefetch()) {
1400 cpu->instDone(tid, inst);
1404 // Control Instructions
1406 if (inst->isControl())
1407 statComBranches[tid]++;
1410 // Memory references
1412 if (inst->isMemRef()) {
1415 if (inst->isLoad()) {
1416 statComLoads[tid]++;
1420 if (inst->isMemBarrier()) {
1421 statComMembars[tid]++;
1424 // Integer Instruction
1425 if (inst->isInteger())
1426 statComInteger[tid]++;
1428 // Floating Point Instruction
1429 if (inst->isFloating())
1430 statComFloating[tid]++;
1434 statComFunctionCalls[tid]++;
1438 ////////////////////////////////////////
1440 // SMT COMMIT POLICY MAINTAINED HERE //
1442 ////////////////////////////////////////
1443 template <class Impl>
1445 DefaultCommit<Impl>::getCommittingThread()
1447 if (numThreads > 1) {
1448 switch (commitPolicy) {
1451 //If Policy is Aggressive, commit will call
1452 //this function multiple times per
1454 return oldestReady();
1457 return roundRobin();
1460 return oldestReady();
1463 return InvalidThreadID;
1466 assert(!activeThreads->empty());
1467 ThreadID tid = activeThreads->front();
1469 if (commitStatus[tid] == Running ||
1470 commitStatus[tid] == Idle ||
1471 commitStatus[tid] == FetchTrapPending) {
1474 return InvalidThreadID;
1479 template<class Impl>
1481 DefaultCommit<Impl>::roundRobin()
1483 list<ThreadID>::iterator pri_iter = priority_list.begin();
1484 list<ThreadID>::iterator end = priority_list.end();
1486 while (pri_iter != end) {
1487 ThreadID tid = *pri_iter;
1489 if (commitStatus[tid] == Running ||
1490 commitStatus[tid] == Idle ||
1491 commitStatus[tid] == FetchTrapPending) {
1493 if (rob->isHeadReady(tid)) {
1494 priority_list.erase(pri_iter);
1495 priority_list.push_back(tid);
1504 return InvalidThreadID;
1507 template<class Impl>
1509 DefaultCommit<Impl>::oldestReady()
1511 unsigned oldest = 0;
1514 list<ThreadID>::iterator threads = activeThreads->begin();
1515 list<ThreadID>::iterator end = activeThreads->end();
1517 while (threads != end) {
1518 ThreadID tid = *threads++;
1520 if (!rob->isEmpty(tid) &&
1521 (commitStatus[tid] == Running ||
1522 commitStatus[tid] == Idle ||
1523 commitStatus[tid] == FetchTrapPending)) {
1525 if (rob->isHeadReady(tid)) {
1527 DynInstPtr head_inst = rob->readHeadInst(tid);
1532 } else if (head_inst->seqNum < oldest) {
1542 return InvalidThreadID;
1546 #endif//__CPU_O3_COMMIT_IMPL_HH__