src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <algorithm>
  45 #include <string>
  46
  47 #include "arch/utility.hh"
  48 #include "base/cp_annotate.hh"
  49 #include "base/loader/symtab.hh"
  50 #include "cpu/timebuf.hh"
  51 #include "config/full_system.hh"
  52 #include "config/the_isa.hh"
  53 #include "config/use_checker.hh"
  54 #include "cpu/exetrace.hh"
  55 #include "cpu/o3/commit.hh"
  56 #include "cpu/o3/thread_state.hh"
  57 #include "params/DerivO3CPU.hh"
  58
  59 #if USE_CHECKER
  60 #include "cpu/checker/cpu.hh"
  61 #endif
  62
  63 using namespace std;
  64
  65 template <class Impl>
  66 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  67                                           ThreadID _tid)
  68     : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
  69 {
  70     this->setFlags(AutoDelete);
  71 }
  72
  73 template <class Impl>
  74 void
  75 DefaultCommit<Impl>::TrapEvent::process()
  76 {
  77     // This will get reset by commit if it was switched out at the
  78     // time of this event processing.
  79     commit->trapSquash[tid] = true;
  80 }
  81
  82 template <class Impl>
  83 const char *
  84 DefaultCommit<Impl>::TrapEvent::description() const
  85 {
  86     return "Trap";
  87 }
  88
  89 template <class Impl>
  90 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
  91     : cpu(_cpu),
  92       squashCounter(0),
  93       iewToCommitDelay(params->iewToCommitDelay),
  94       commitToIEWDelay(params->commitToIEWDelay),
  95       renameToROBDelay(params->renameToROBDelay),
  96       fetchToCommitDelay(params->commitToFetchDelay),
  97       renameWidth(params->renameWidth),
  98       commitWidth(params->commitWidth),
  99       numThreads(params->numThreads),
 100       drainPending(false),
 101       switchedOut(false),
 102       trapLatency(params->trapLatency)
 103 {
 104     _status = Active;
 105     _nextStatus = Inactive;
 106     std::string policy = params->smtCommitPolicy;
 107
 108     //Convert string to lowercase
 109     std::transform(policy.begin(), policy.end(), policy.begin(),
 110                    (int(*)(int)) tolower);
 111
 112     //Assign commit policy
 113     if (policy == "aggressive"){
 114         commitPolicy = Aggressive;
 115
 116         DPRINTF(Commit,"Commit Policy set to Aggressive.");
 117     } else if (policy == "roundrobin"){
 118         commitPolicy = RoundRobin;
 119
 120         //Set-Up Priority List
 121         for (ThreadID tid = 0; tid < numThreads; tid++) {
 122             priority_list.push_back(tid);
 123         }
 124
 125         DPRINTF(Commit,"Commit Policy set to Round Robin.");
 126     } else if (policy == "oldestready"){
 127         commitPolicy = OldestReady;
 128
 129         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 130     } else {
 131         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 132                "RoundRobin,OldestReady}");
 133     }
 134
 135     for (ThreadID tid = 0; tid < numThreads; tid++) {
 136         commitStatus[tid] = Idle;
 137         changedROBNumEntries[tid] = false;
 138         checkEmptyROB[tid] = false;
 139         trapInFlight[tid] = false;
 140         committedStores[tid] = false;
 141         trapSquash[tid] = false;
 142         tcSquash[tid] = false;
 143         pc[tid].set(0);
 144     }
 145 #if FULL_SYSTEM
 146     interrupt = NoFault;
 147 #endif
 148 }
 149
 150 template <class Impl>
 151 std::string
 152 DefaultCommit<Impl>::name() const
 153 {
 154     return cpu->name() + ".commit";
 155 }
 156
 157 template <class Impl>
 158 void
 159 DefaultCommit<Impl>::regStats()
 160 {
 161     using namespace Stats;
 162     commitCommittedInsts
 163         .name(name() + ".commitCommittedInsts")
 164         .desc("The number of committed instructions")
 165         .prereq(commitCommittedInsts);
 166     commitSquashedInsts
 167         .name(name() + ".commitSquashedInsts")
 168         .desc("The number of squashed insts skipped by commit")
 169         .prereq(commitSquashedInsts);
 170     commitSquashEvents
 171         .name(name() + ".commitSquashEvents")
 172         .desc("The number of times commit is told to squash")
 173         .prereq(commitSquashEvents);
 174     commitNonSpecStalls
 175         .name(name() + ".commitNonSpecStalls")
 176         .desc("The number of times commit has been forced to stall to "
 177               "communicate backwards")
 178         .prereq(commitNonSpecStalls);
 179     branchMispredicts
 180         .name(name() + ".branchMispredicts")
 181         .desc("The number of times a branch was mispredicted")
 182         .prereq(branchMispredicts);
 183     numCommittedDist
 184         .init(0,commitWidth,1)
 185         .name(name() + ".COM:committed_per_cycle")
 186         .desc("Number of insts commited each cycle")
 187         .flags(Stats::pdf)
 188         ;
 189
 190     statComInst
 191         .init(cpu->numThreads)
 192         .name(name() + ".COM:count")
 193         .desc("Number of instructions committed")
 194         .flags(total)
 195         ;
 196
 197     statComSwp
 198         .init(cpu->numThreads)
 199         .name(name() + ".COM:swp_count")
 200         .desc("Number of s/w prefetches committed")
 201         .flags(total)
 202         ;
 203
 204     statComRefs
 205         .init(cpu->numThreads)
 206         .name(name() +  ".COM:refs")
 207         .desc("Number of memory references committed")
 208         .flags(total)
 209         ;
 210
 211     statComLoads
 212         .init(cpu->numThreads)
 213         .name(name() +  ".COM:loads")
 214         .desc("Number of loads committed")
 215         .flags(total)
 216         ;
 217
 218     statComMembars
 219         .init(cpu->numThreads)
 220         .name(name() +  ".COM:membars")
 221         .desc("Number of memory barriers committed")
 222         .flags(total)
 223         ;
 224
 225     statComBranches
 226         .init(cpu->numThreads)
 227         .name(name() + ".COM:branches")
 228         .desc("Number of branches committed")
 229         .flags(total)
 230         ;
 231
 232     commitEligible
 233         .init(cpu->numThreads)
 234         .name(name() + ".COM:bw_limited")
 235         .desc("number of insts not committed due to BW limits")
 236         .flags(total)
 237         ;
 238
 239     commitEligibleSamples
 240         .name(name() + ".COM:bw_lim_events")
 241         .desc("number cycles where commit BW limit reached")
 242         ;
 243 }
 244
 245 template <class Impl>
 246 void
 247 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 248 {
 249     thread = threads;
 250 }
 251
 252 template <class Impl>
 253 void
 254 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 255 {
 256     timeBuffer = tb_ptr;
 257
 258     // Setup wire to send information back to IEW.
 259     toIEW = timeBuffer->getWire(0);
 260
 261     // Setup wire to read data from IEW (for the ROB).
 262     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 263 }
 264
 265 template <class Impl>
 266 void
 267 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 268 {
 269     fetchQueue = fq_ptr;
 270
 271     // Setup wire to get instructions from rename (for the ROB).
 272     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 273 }
 274
 275 template <class Impl>
 276 void
 277 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 278 {
 279     renameQueue = rq_ptr;
 280
 281     // Setup wire to get instructions from rename (for the ROB).
 282     fromRename = renameQueue->getWire(-renameToROBDelay);
 283 }
 284
 285 template <class Impl>
 286 void
 287 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 288 {
 289     iewQueue = iq_ptr;
 290
 291     // Setup wire to get instructions from IEW.
 292     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 293 }
 294
 295 template <class Impl>
 296 void
 297 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 298 {
 299     iewStage = iew_stage;
 300 }
 301
 302 template<class Impl>
 303 void
 304 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 305 {
 306     activeThreads = at_ptr;
 307 }
 308
 309 template <class Impl>
 310 void
 311 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 312 {
 313     for (ThreadID tid = 0; tid < numThreads; tid++)
 314         renameMap[tid] = &rm_ptr[tid];
 315 }
 316
 317 template <class Impl>
 318 void
 319 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 320 {
 321     rob = rob_ptr;
 322 }
 323
 324 template <class Impl>
 325 void
 326 DefaultCommit<Impl>::initStage()
 327 {
 328     rob->setActiveThreads(activeThreads);
 329     rob->resetEntries();
 330
 331     // Broadcast the number of free entries.
 332     for (ThreadID tid = 0; tid < numThreads; tid++) {
 333         toIEW->commitInfo[tid].usedROB = true;
 334         toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 335         toIEW->commitInfo[tid].emptyROB = true;
 336     }
 337
 338     // Commit must broadcast the number of free entries it has at the
 339     // start of the simulation, so it starts as active.
 340     cpu->activateStage(O3CPU::CommitIdx);
 341
 342     cpu->activityThisCycle();
 343     trapLatency = cpu->ticks(trapLatency);
 344 }
 345
 346 template <class Impl>
 347 bool
 348 DefaultCommit<Impl>::drain()
 349 {
 350     drainPending = true;
 351
 352     return false;
 353 }
 354
 355 template <class Impl>
 356 void
 357 DefaultCommit<Impl>::switchOut()
 358 {
 359     switchedOut = true;
 360     drainPending = false;
 361     rob->switchOut();
 362 }
 363
 364 template <class Impl>
 365 void
 366 DefaultCommit<Impl>::resume()
 367 {
 368     drainPending = false;
 369 }
 370
 371 template <class Impl>
 372 void
 373 DefaultCommit<Impl>::takeOverFrom()
 374 {
 375     switchedOut = false;
 376     _status = Active;
 377     _nextStatus = Inactive;
 378     for (ThreadID tid = 0; tid < numThreads; tid++) {
 379         commitStatus[tid] = Idle;
 380         changedROBNumEntries[tid] = false;
 381         trapSquash[tid] = false;
 382         tcSquash[tid] = false;
 383     }
 384     squashCounter = 0;
 385     rob->takeOverFrom();
 386 }
 387
 388 template <class Impl>
 389 void
 390 DefaultCommit<Impl>::updateStatus()
 391 {
 392     // reset ROB changed variable
 393     list<ThreadID>::iterator threads = activeThreads->begin();
 394     list<ThreadID>::iterator end = activeThreads->end();
 395
 396     while (threads != end) {
 397         ThreadID tid = *threads++;
 398
 399         changedROBNumEntries[tid] = false;
 400
 401         // Also check if any of the threads has a trap pending
 402         if (commitStatus[tid] == TrapPending ||
 403             commitStatus[tid] == FetchTrapPending) {
 404             _nextStatus = Active;
 405         }
 406     }
 407
 408     if (_nextStatus == Inactive && _status == Active) {
 409         DPRINTF(Activity, "Deactivating stage.\n");
 410         cpu->deactivateStage(O3CPU::CommitIdx);
 411     } else if (_nextStatus == Active && _status == Inactive) {
 412         DPRINTF(Activity, "Activating stage.\n");
 413         cpu->activateStage(O3CPU::CommitIdx);
 414     }
 415
 416     _status = _nextStatus;
 417 }
 418
 419 template <class Impl>
 420 void
 421 DefaultCommit<Impl>::setNextStatus()
 422 {
 423     int squashes = 0;
 424
 425     list<ThreadID>::iterator threads = activeThreads->begin();
 426     list<ThreadID>::iterator end = activeThreads->end();
 427
 428     while (threads != end) {
 429         ThreadID tid = *threads++;
 430
 431         if (commitStatus[tid] == ROBSquashing) {
 432             squashes++;
 433         }
 434     }
 435
 436     squashCounter = squashes;
 437
 438     // If commit is currently squashing, then it will have activity for the
 439     // next cycle. Set its next status as active.
 440     if (squashCounter) {
 441         _nextStatus = Active;
 442     }
 443 }
 444
 445 template <class Impl>
 446 bool
 447 DefaultCommit<Impl>::changedROBEntries()
 448 {
 449     list<ThreadID>::iterator threads = activeThreads->begin();
 450     list<ThreadID>::iterator end = activeThreads->end();
 451
 452     while (threads != end) {
 453         ThreadID tid = *threads++;
 454
 455         if (changedROBNumEntries[tid]) {
 456             return true;
 457         }
 458     }
 459
 460     return false;
 461 }
 462
 463 template <class Impl>
 464 size_t
 465 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
 466 {
 467     return rob->numFreeEntries(tid);
 468 }
 469
 470 template <class Impl>
 471 void
 472 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
 473 {
 474     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 475
 476     TrapEvent *trap = new TrapEvent(this, tid);
 477
 478     cpu->schedule(trap, curTick() + trapLatency);
 479     trapInFlight[tid] = true;
 480 }
 481
 482 template <class Impl>
 483 void
 484 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
 485 {
 486     assert(!trapInFlight[tid]);
 487     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 488
 489     tcSquash[tid] = true;
 490 }
 491
 492 template <class Impl>
 493 void
 494 DefaultCommit<Impl>::squashAll(ThreadID tid)
 495 {
 496     // If we want to include the squashing instruction in the squash,
 497     // then use one older sequence number.
 498     // Hopefully this doesn't mess things up.  Basically I want to squash
 499     // all instructions of this thread.
 500     InstSeqNum squashed_inst = rob->isEmpty() ?
 501         0 : rob->readHeadInst(tid)->seqNum - 1;
 502
 503     // All younger instructions will be squashed. Set the sequence
 504     // number as the youngest instruction in the ROB (0 in this case.
 505     // Hopefully nothing breaks.)
 506     youngestSeqNum[tid] = 0;
 507
 508     rob->squash(squashed_inst, tid);
 509     changedROBNumEntries[tid] = true;
 510
 511     // Send back the sequence number of the squashed instruction.
 512     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 513
 514     // Send back the squash signal to tell stages that they should
 515     // squash.
 516     toIEW->commitInfo[tid].squash = true;
 517
 518     // Send back the rob squashing signal so other stages know that
 519     // the ROB is in the process of squashing.
 520     toIEW->commitInfo[tid].robSquashing = true;
 521
 522     toIEW->commitInfo[tid].branchMispredict = false;
 523
 524     toIEW->commitInfo[tid].pc = pc[tid];
 525 }
 526
 527 template <class Impl>
 528 void
 529 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
 530 {
 531     squashAll(tid);
 532
 533     DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
 534
 535     thread[tid]->trapPending = false;
 536     thread[tid]->inSyscall = false;
 537     trapInFlight[tid] = false;
 538
 539     trapSquash[tid] = false;
 540
 541     commitStatus[tid] = ROBSquashing;
 542     cpu->activityThisCycle();
 543 }
 544
 545 template <class Impl>
 546 void
 547 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
 548 {
 549     squashAll(tid);
 550
 551     DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
 552
 553     thread[tid]->inSyscall = false;
 554     assert(!thread[tid]->trapPending);
 555
 556     commitStatus[tid] = ROBSquashing;
 557     cpu->activityThisCycle();
 558
 559     tcSquash[tid] = false;
 560 }
 561
 562 template <class Impl>
 563 void
 564 DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
 565 {
 566     youngestSeqNum[tid] = squash_after_seq_num;
 567
 568     rob->squash(squash_after_seq_num, tid);
 569     changedROBNumEntries[tid] = true;
 570
 571     // Send back the sequence number of the squashed instruction.
 572     toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
 573
 574     // Send back the squash signal to tell stages that they should squash.
 575     toIEW->commitInfo[tid].squash = true;
 576
 577     // Send back the rob squashing signal so other stages know that
 578     // the ROB is in the process of squashing.
 579     toIEW->commitInfo[tid].robSquashing = true;
 580
 581     toIEW->commitInfo[tid].branchMispredict = false;
 582
 583     toIEW->commitInfo[tid].pc = pc[tid];
 584     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
 585             tid, squash_after_seq_num);
 586     commitStatus[tid] = ROBSquashing;
 587 }
 588
 589 template <class Impl>
 590 void
 591 DefaultCommit<Impl>::tick()
 592 {
 593     wroteToTimeBuffer = false;
 594     _nextStatus = Inactive;
 595
 596     if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 597         cpu->signalDrained();
 598         drainPending = false;
 599         return;
 600     }
 601
 602     if (activeThreads->empty())
 603         return;
 604
 605     list<ThreadID>::iterator threads = activeThreads->begin();
 606     list<ThreadID>::iterator end = activeThreads->end();
 607
 608     // Check if any of the threads are done squashing.  Change the
 609     // status if they are done.
 610     while (threads != end) {
 611         ThreadID tid = *threads++;
 612
 613         // Clear the bit saying if the thread has committed stores
 614         // this cycle.
 615         committedStores[tid] = false;
 616
 617         if (commitStatus[tid] == ROBSquashing) {
 618
 619             if (rob->isDoneSquashing(tid)) {
 620                 commitStatus[tid] = Running;
 621             } else {
 622                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 623                         " insts this cycle.\n", tid);
 624                 rob->doSquash(tid);
 625                 toIEW->commitInfo[tid].robSquashing = true;
 626                 wroteToTimeBuffer = true;
 627             }
 628         }
 629     }
 630
 631     commit();
 632
 633     markCompletedInsts();
 634
 635     threads = activeThreads->begin();
 636
 637     while (threads != end) {
 638         ThreadID tid = *threads++;
 639
 640         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 641             // The ROB has more instructions it can commit. Its next status
 642             // will be active.
 643             _nextStatus = Active;
 644
 645             DynInstPtr inst = rob->readHeadInst(tid);
 646
 647             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
 648                     " ROB and ready to commit\n",
 649                     tid, inst->seqNum, inst->pcState());
 650
 651         } else if (!rob->isEmpty(tid)) {
 652             DynInstPtr inst = rob->readHeadInst(tid);
 653
 654             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 655                     "%s is head of ROB and not ready\n",
 656                     tid, inst->seqNum, inst->pcState());
 657         }
 658
 659         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 660                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 661     }
 662
 663
 664     if (wroteToTimeBuffer) {
 665         DPRINTF(Activity, "Activity This Cycle.\n");
 666         cpu->activityThisCycle();
 667     }
 668
 669     updateStatus();
 670 }
 671
 672 #if FULL_SYSTEM
 673 template <class Impl>
 674 void
 675 DefaultCommit<Impl>::handleInterrupt()
 676 {
 677     if (interrupt != NoFault) {
 678         // Wait until the ROB is empty and all stores have drained in
 679         // order to enter the interrupt.
 680         if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 681             // Squash or record that I need to squash this cycle if
 682             // an interrupt needed to be handled.
 683             DPRINTF(Commit, "Interrupt detected.\n");
 684
 685             // Clear the interrupt now that it's going to be handled
 686             toIEW->commitInfo[0].clearInterrupt = true;
 687
 688             assert(!thread[0]->inSyscall);
 689             thread[0]->inSyscall = true;
 690
 691             // CPU will handle interrupt.
 692             cpu->processInterrupts(interrupt);
 693
 694             thread[0]->inSyscall = false;
 695
 696             commitStatus[0] = TrapPending;
 697
 698             // Generate trap squash event.
 699             generateTrapEvent(0);
 700
 701             interrupt = NoFault;
 702         } else {
 703             DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 704         }
 705     } else if (commitStatus[0] != TrapPending &&
 706                cpu->checkInterrupts(cpu->tcBase(0)) &&
 707                !trapSquash[0] &&
 708                !tcSquash[0]) {
 709         // Process interrupts if interrupts are enabled, not in PAL
 710         // mode, and no other traps or external squashes are currently
 711         // pending.
 712         // @todo: Allow other threads to handle interrupts.
 713
 714         // Get any interrupt that happened
 715         interrupt = cpu->getInterrupts();
 716
 717         if (interrupt != NoFault) {
 718             // Tell fetch that there is an interrupt pending.  This
 719             // will make fetch wait until it sees a non PAL-mode PC,
 720             // at which point it stops fetching instructions.
 721             toIEW->commitInfo[0].interruptPending = true;
 722         }
 723     }
 724 }
 725 #endif // FULL_SYSTEM
 726
 727 template <class Impl>
 728 void
 729 DefaultCommit<Impl>::commit()
 730 {
 731
 732 #if FULL_SYSTEM
 733     // Check for any interrupt, and start processing it.  Or if we
 734     // have an outstanding interrupt and are at a point when it is
 735     // valid to take an interrupt, process it.
 736     if (cpu->checkInterrupts(cpu->tcBase(0))) {
 737         handleInterrupt();
 738     }
 739 #endif // FULL_SYSTEM
 740
 741     ////////////////////////////////////
 742     // Check for any possible squashes, handle them first
 743     ////////////////////////////////////
 744     list<ThreadID>::iterator threads = activeThreads->begin();
 745     list<ThreadID>::iterator end = activeThreads->end();
 746
 747     while (threads != end) {
 748         ThreadID tid = *threads++;
 749
 750         // Not sure which one takes priority.  I think if we have
 751         // both, that's a bad sign.
 752         if (trapSquash[tid] == true) {
 753             assert(!tcSquash[tid]);
 754             squashFromTrap(tid);
 755         } else if (tcSquash[tid] == true) {
 756             assert(commitStatus[tid] != TrapPending);
 757             squashFromTC(tid);
 758         }
 759
 760         // Squashed sequence number must be older than youngest valid
 761         // instruction in the ROB. This prevents squashes from younger
 762         // instructions overriding squashes from older instructions.
 763         if (fromIEW->squash[tid] &&
 764             commitStatus[tid] != TrapPending &&
 765             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 766
 767             DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
 768                     tid,
 769                     fromIEW->mispredPC[tid],
 770                     fromIEW->squashedSeqNum[tid]);
 771
 772             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 773                     tid,
 774                     fromIEW->pc[tid].nextInstAddr());
 775
 776             commitStatus[tid] = ROBSquashing;
 777
 778             // If we want to include the squashing instruction in the squash,
 779             // then use one older sequence number.
 780             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 781
 782             if (fromIEW->includeSquashInst[tid] == true) {
 783                 squashed_inst--;
 784             }
 785
 786             // All younger instructions will be squashed. Set the sequence
 787             // number as the youngest instruction in the ROB.
 788             youngestSeqNum[tid] = squashed_inst;
 789
 790             rob->squash(squashed_inst, tid);
 791             changedROBNumEntries[tid] = true;
 792
 793             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 794
 795             toIEW->commitInfo[tid].squash = true;
 796
 797             // Send back the rob squashing signal so other stages know that
 798             // the ROB is in the process of squashing.
 799             toIEW->commitInfo[tid].robSquashing = true;
 800
 801             toIEW->commitInfo[tid].branchMispredict =
 802                 fromIEW->branchMispredict[tid];
 803
 804             toIEW->commitInfo[tid].branchTaken =
 805                 fromIEW->branchTaken[tid];
 806
 807             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 808
 809             toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
 810
 811             if (toIEW->commitInfo[tid].branchMispredict) {
 812                 ++branchMispredicts;
 813             }
 814         }
 815
 816     }
 817
 818     setNextStatus();
 819
 820     if (squashCounter != numThreads) {
 821         // If we're not currently squashing, then get instructions.
 822         getInsts();
 823
 824         // Try to commit any instructions.
 825         commitInsts();
 826     }
 827
 828     //Check for any activity
 829     threads = activeThreads->begin();
 830
 831     while (threads != end) {
 832         ThreadID tid = *threads++;
 833
 834         if (changedROBNumEntries[tid]) {
 835             toIEW->commitInfo[tid].usedROB = true;
 836             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 837
 838             wroteToTimeBuffer = true;
 839             changedROBNumEntries[tid] = false;
 840             if (rob->isEmpty(tid))
 841                 checkEmptyROB[tid] = true;
 842         }
 843
 844         // ROB is only considered "empty" for previous stages if: a)
 845         // ROB is empty, b) there are no outstanding stores, c) IEW
 846         // stage has received any information regarding stores that
 847         // committed.
 848         // c) is checked by making sure to not consider the ROB empty
 849         // on the same cycle as when stores have been committed.
 850         // @todo: Make this handle multi-cycle communication between
 851         // commit and IEW.
 852         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
 853             !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
 854             checkEmptyROB[tid] = false;
 855             toIEW->commitInfo[tid].usedROB = true;
 856             toIEW->commitInfo[tid].emptyROB = true;
 857             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 858             wroteToTimeBuffer = true;
 859         }
 860
 861     }
 862 }
 863
 864 template <class Impl>
 865 void
 866 DefaultCommit<Impl>::commitInsts()
 867 {
 868     ////////////////////////////////////
 869     // Handle commit
 870     // Note that commit will be handled prior to putting new
 871     // instructions in the ROB so that the ROB only tries to commit
 872     // instructions it has in this current cycle, and not instructions
 873     // it is writing in during this cycle.  Can't commit and squash
 874     // things at the same time...
 875     ////////////////////////////////////
 876
 877     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 878
 879     unsigned num_committed = 0;
 880
 881     DynInstPtr head_inst;
 882
 883     // Commit as many instructions as possible until the commit bandwidth
 884     // limit is reached, or it becomes impossible to commit any more.
 885     while (num_committed < commitWidth) {
 886         int commit_thread = getCommittingThread();
 887
 888         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 889             break;
 890
 891         head_inst = rob->readHeadInst(commit_thread);
 892
 893         ThreadID tid = head_inst->threadNumber;
 894
 895         assert(tid == commit_thread);
 896
 897         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 898                 head_inst->seqNum, tid);
 899
 900         // If the head instruction is squashed, it is ready to retire
 901         // (be removed from the ROB) at any time.
 902         if (head_inst->isSquashed()) {
 903
 904             DPRINTF(Commit, "Retiring squashed instruction from "
 905                     "ROB.\n");
 906
 907             rob->retireHead(commit_thread);
 908
 909             ++commitSquashedInsts;
 910
 911             // Record that the number of ROB entries has changed.
 912             changedROBNumEntries[tid] = true;
 913         } else {
 914             pc[tid] = head_inst->pcState();
 915
 916             // Increment the total number of non-speculative instructions
 917             // executed.
 918             // Hack for now: it really shouldn't happen until after the
 919             // commit is deemed to be successful, but this count is needed
 920             // for syscalls.
 921             thread[tid]->funcExeInst++;
 922
 923             // Try to commit the head instruction.
 924             bool commit_success = commitHead(head_inst, num_committed);
 925
 926             if (commit_success) {
 927                 ++num_committed;
 928
 929                 changedROBNumEntries[tid] = true;
 930
 931                 // Set the doneSeqNum to the youngest committed instruction.
 932                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 933
 934                 ++commitCommittedInsts;
 935
 936                 // To match the old model, don't count nops and instruction
 937                 // prefetches towards the total commit count.
 938                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 939                     cpu->instDone(tid);
 940                 }
 941
 942                 // Updates misc. registers.
 943                 head_inst->updateMiscRegs();
 944
 945                 TheISA::advancePC(pc[tid], head_inst->staticInst);
 946
 947                 // If this is an instruction that doesn't play nicely with
 948                 // others squash everything and restart fetch
 949                 if (head_inst->isSquashAfter())
 950                     squashAfter(tid, head_inst->seqNum);
 951
 952                 int count = 0;
 953                 Addr oldpc;
 954                 // Debug statement.  Checks to make sure we're not
 955                 // currently updating state while handling PC events.
 956                 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
 957                 do {
 958                     oldpc = pc[tid].instAddr();
 959                     cpu->system->pcEventQueue.service(thread[tid]->getTC());
 960                     count++;
 961                 } while (oldpc != pc[tid].instAddr());
 962                 if (count > 1) {
 963                     DPRINTF(Commit,
 964                             "PC skip function event, stopping commit\n");
 965                     break;
 966                 }
 967             } else {
 968                 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
 969                         "[tid:%i] [sn:%i].\n",
 970                         head_inst->pcState(), tid ,head_inst->seqNum);
 971                 break;
 972             }
 973         }
 974     }
 975
 976     DPRINTF(CommitRate, "%i\n", num_committed);
 977     numCommittedDist.sample(num_committed);
 978
 979     if (num_committed == commitWidth) {
 980         commitEligibleSamples++;
 981     }
 982 }
 983
 984 template <class Impl>
 985 bool
 986 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 987 {
 988     assert(head_inst);
 989
 990     ThreadID tid = head_inst->threadNumber;
 991
 992     // If the instruction is not executed yet, then it will need extra
 993     // handling.  Signal backwards that it should be executed.
 994     if (!head_inst->isExecuted()) {
 995         // Keep this number correct.  We have not yet actually executed
 996         // and committed this instruction.
 997         thread[tid]->funcExeInst--;
 998
 999         if (head_inst->isNonSpeculative() ||
1000             head_inst->isStoreConditional() ||
1001             head_inst->isMemBarrier() ||
1002             head_inst->isWriteBarrier()) {
1003
1004             DPRINTF(Commit, "Encountered a barrier or non-speculative "
1005                     "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1006                     head_inst->seqNum, head_inst->pcState());
1007
1008             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1009                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1010                 return false;
1011             }
1012
1013             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1014
1015             // Change the instruction so it won't try to commit again until
1016             // it is executed.
1017             head_inst->clearCanCommit();
1018
1019             ++commitNonSpecStalls;
1020
1021             return false;
1022         } else if (head_inst->isLoad()) {
1023             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1024                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1025                 return false;
1026             }
1027
1028             assert(head_inst->uncacheable());
1029             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1030                     head_inst->seqNum, head_inst->pcState());
1031
1032             // Send back the non-speculative instruction's sequence
1033             // number.  Tell the lsq to re-execute the load.
1034             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1035             toIEW->commitInfo[tid].uncached = true;
1036             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1037
1038             head_inst->clearCanCommit();
1039
1040             return false;
1041         } else {
1042             panic("Trying to commit un-executed instruction "
1043                   "of unknown type!\n");
1044         }
1045     }
1046
1047     if (head_inst->isThreadSync()) {
1048         // Not handled for now.
1049         panic("Thread sync instructions are not handled yet.\n");
1050     }
1051
1052     // Check if the instruction caused a fault.  If so, trap.
1053     Fault inst_fault = head_inst->getFault();
1054
1055     // Stores mark themselves as completed.
1056     if (!head_inst->isStore() && inst_fault == NoFault) {
1057         head_inst->setCompleted();
1058     }
1059
1060 #if USE_CHECKER
1061     // Use checker prior to updating anything due to traps or PC
1062     // based events.
1063     if (cpu->checker) {
1064         cpu->checker->verify(head_inst);
1065     }
1066 #endif
1067
1068     if (inst_fault != NoFault) {
1069         DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1070                 head_inst->seqNum, head_inst->pcState());
1071
1072         if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1073             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1074             return false;
1075         }
1076
1077         head_inst->setCompleted();
1078
1079 #if USE_CHECKER
1080         if (cpu->checker && head_inst->isStore()) {
1081             cpu->checker->verify(head_inst);
1082         }
1083 #endif
1084
1085         assert(!thread[tid]->inSyscall);
1086
1087         // Mark that we're in state update mode so that the trap's
1088         // execution doesn't generate extra squashes.
1089         thread[tid]->inSyscall = true;
1090
1091         // Execute the trap.  Although it's slightly unrealistic in
1092         // terms of timing (as it doesn't wait for the full timing of
1093         // the trap event to complete before updating state), it's
1094         // needed to update the state as soon as possible.  This
1095         // prevents external agents from changing any specific state
1096         // that the trap need.
1097         cpu->trap(inst_fault, tid, head_inst->staticInst);
1098
1099         // Exit state update mode to avoid accidental updating.
1100         thread[tid]->inSyscall = false;
1101
1102         commitStatus[tid] = TrapPending;
1103
1104         if (head_inst->traceData) {
1105             if (DTRACE(ExecFaulting)) {
1106                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1107                 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1108                 head_inst->traceData->dump();
1109             }
1110             delete head_inst->traceData;
1111             head_inst->traceData = NULL;
1112         }
1113
1114         // Generate trap squash event.
1115         generateTrapEvent(tid);
1116         return false;
1117     }
1118
1119     updateComInstStats(head_inst);
1120
1121 #if FULL_SYSTEM
1122     if (thread[tid]->profile) {
1123         thread[tid]->profilePC = head_inst->instAddr();
1124         ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1125                                                           head_inst->staticInst);
1126
1127         if (node)
1128             thread[tid]->profileNode = node;
1129     }
1130     if (CPA::available()) {
1131         if (head_inst->isControl()) {
1132             ThreadContext *tc = thread[tid]->getTC();
1133             CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1134         }
1135     }
1136 #endif
1137
1138     if (head_inst->traceData) {
1139         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1140         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1141         head_inst->traceData->dump();
1142         delete head_inst->traceData;
1143         head_inst->traceData = NULL;
1144     }
1145
1146     // Update the commit rename map
1147     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1148         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1149                                  head_inst->renamedDestRegIdx(i));
1150     }
1151
1152     if (head_inst->isCopy())
1153         panic("Should not commit any copy instructions!");
1154
1155     // Finally clear the head ROB entry.
1156     rob->retireHead(tid);
1157
1158     // If this was a store, record it for this cycle.
1159     if (head_inst->isStore())
1160         committedStores[tid] = true;
1161
1162     // Return true to indicate that we have committed an instruction.
1163     return true;
1164 }
1165
1166 template <class Impl>
1167 void
1168 DefaultCommit<Impl>::getInsts()
1169 {
1170     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1171
1172     // Read any renamed instructions and place them into the ROB.
1173     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1174
1175     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1176         DynInstPtr inst;
1177
1178         inst = fromRename->insts[inst_num];
1179         ThreadID tid = inst->threadNumber;
1180
1181         if (!inst->isSquashed() &&
1182             commitStatus[tid] != ROBSquashing &&
1183             commitStatus[tid] != TrapPending) {
1184             changedROBNumEntries[tid] = true;
1185
1186             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1187                     inst->pcState(), inst->seqNum, tid);
1188
1189             rob->insertInst(inst);
1190
1191             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1192
1193             youngestSeqNum[tid] = inst->seqNum;
1194         } else {
1195             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1196                     "squashed, skipping.\n",
1197                     inst->pcState(), inst->seqNum, tid);
1198         }
1199     }
1200 }
1201
1202 template <class Impl>
1203 void
1204 DefaultCommit<Impl>::skidInsert()
1205 {
1206     DPRINTF(Commit, "Attempting to any instructions from rename into "
1207             "skidBuffer.\n");
1208
1209     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1210         DynInstPtr inst = fromRename->insts[inst_num];
1211
1212         if (!inst->isSquashed()) {
1213             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1214                     "skidBuffer.\n", inst->pcState(), inst->seqNum,
1215                     inst->threadNumber);
1216             skidBuffer.push(inst);
1217         } else {
1218             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1219                     "squashed, skipping.\n",
1220                     inst->pcState(), inst->seqNum, inst->threadNumber);
1221         }
1222     }
1223 }
1224
1225 template <class Impl>
1226 void
1227 DefaultCommit<Impl>::markCompletedInsts()
1228 {
1229     // Grab completed insts out of the IEW instruction queue, and mark
1230     // instructions completed within the ROB.
1231     for (int inst_num = 0;
1232          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1233          ++inst_num)
1234     {
1235         if (!fromIEW->insts[inst_num]->isSquashed()) {
1236             DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1237                     "within ROB.\n",
1238                     fromIEW->insts[inst_num]->threadNumber,
1239                     fromIEW->insts[inst_num]->pcState(),
1240                     fromIEW->insts[inst_num]->seqNum);
1241
1242             // Mark the instruction as ready to commit.
1243             fromIEW->insts[inst_num]->setCanCommit();
1244         }
1245     }
1246 }
1247
1248 template <class Impl>
1249 bool
1250 DefaultCommit<Impl>::robDoneSquashing()
1251 {
1252     list<ThreadID>::iterator threads = activeThreads->begin();
1253     list<ThreadID>::iterator end = activeThreads->end();
1254
1255     while (threads != end) {
1256         ThreadID tid = *threads++;
1257
1258         if (!rob->isDoneSquashing(tid))
1259             return false;
1260     }
1261
1262     return true;
1263 }
1264
1265 template <class Impl>
1266 void
1267 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1268 {
1269     ThreadID tid = inst->threadNumber;
1270
1271     //
1272     //  Pick off the software prefetches
1273     //
1274 #ifdef TARGET_ALPHA
1275     if (inst->isDataPrefetch()) {
1276         statComSwp[tid]++;
1277     } else {
1278         statComInst[tid]++;
1279     }
1280 #else
1281     statComInst[tid]++;
1282 #endif
1283
1284     //
1285     //  Control Instructions
1286     //
1287     if (inst->isControl())
1288         statComBranches[tid]++;
1289
1290     //
1291     //  Memory references
1292     //
1293     if (inst->isMemRef()) {
1294         statComRefs[tid]++;
1295
1296         if (inst->isLoad()) {
1297             statComLoads[tid]++;
1298         }
1299     }
1300
1301     if (inst->isMemBarrier()) {
1302         statComMembars[tid]++;
1303     }
1304 }
1305
1306 ////////////////////////////////////////
1307 //                                    //
1308 //  SMT COMMIT POLICY MAINTAINED HERE //
1309 //                                    //
1310 ////////////////////////////////////////
1311 template <class Impl>
1312 ThreadID
1313 DefaultCommit<Impl>::getCommittingThread()
1314 {
1315     if (numThreads > 1) {
1316         switch (commitPolicy) {
1317
1318           case Aggressive:
1319             //If Policy is Aggressive, commit will call
1320             //this function multiple times per
1321             //cycle
1322             return oldestReady();
1323
1324           case RoundRobin:
1325             return roundRobin();
1326
1327           case OldestReady:
1328             return oldestReady();
1329
1330           default:
1331             return InvalidThreadID;
1332         }
1333     } else {
1334         assert(!activeThreads->empty());
1335         ThreadID tid = activeThreads->front();
1336
1337         if (commitStatus[tid] == Running ||
1338             commitStatus[tid] == Idle ||
1339             commitStatus[tid] == FetchTrapPending) {
1340             return tid;
1341         } else {
1342             return InvalidThreadID;
1343         }
1344     }
1345 }
1346
1347 template<class Impl>
1348 ThreadID
1349 DefaultCommit<Impl>::roundRobin()
1350 {
1351     list<ThreadID>::iterator pri_iter = priority_list.begin();
1352     list<ThreadID>::iterator end      = priority_list.end();
1353
1354     while (pri_iter != end) {
1355         ThreadID tid = *pri_iter;
1356
1357         if (commitStatus[tid] == Running ||
1358             commitStatus[tid] == Idle ||
1359             commitStatus[tid] == FetchTrapPending) {
1360
1361             if (rob->isHeadReady(tid)) {
1362                 priority_list.erase(pri_iter);
1363                 priority_list.push_back(tid);
1364
1365                 return tid;
1366             }
1367         }
1368
1369         pri_iter++;
1370     }
1371
1372     return InvalidThreadID;
1373 }
1374
1375 template<class Impl>
1376 ThreadID
1377 DefaultCommit<Impl>::oldestReady()
1378 {
1379     unsigned oldest = 0;
1380     bool first = true;
1381
1382     list<ThreadID>::iterator threads = activeThreads->begin();
1383     list<ThreadID>::iterator end = activeThreads->end();
1384
1385     while (threads != end) {
1386         ThreadID tid = *threads++;
1387
1388         if (!rob->isEmpty(tid) &&
1389             (commitStatus[tid] == Running ||
1390              commitStatus[tid] == Idle ||
1391              commitStatus[tid] == FetchTrapPending)) {
1392
1393             if (rob->isHeadReady(tid)) {
1394
1395                 DynInstPtr head_inst = rob->readHeadInst(tid);
1396
1397                 if (first) {
1398                     oldest = tid;
1399                     first = false;
1400                 } else if (head_inst->seqNum < oldest) {
1401                     oldest = tid;
1402                 }
1403             }
1404         }
1405     }
1406
1407     if (!first) {
1408         return oldest;
1409     } else {
1410         return InvalidThreadID;
1411     }
1412 }