src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2010-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <algorithm>
  45 #include <string>
  46
  47 #include "arch/utility.hh"
  48 #include "base/loader/symtab.hh"
  49 #include "base/cp_annotate.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/checker/cpu.hh"
  52 #include "cpu/o3/commit.hh"
  53 #include "cpu/o3/thread_state.hh"
  54 #include "cpu/base.hh"
  55 #include "cpu/exetrace.hh"
  56 #include "cpu/timebuf.hh"
  57 #include "debug/Activity.hh"
  58 #include "debug/Commit.hh"
  59 #include "debug/CommitRate.hh"
  60 #include "debug/ExecFaulting.hh"
  61 #include "params/DerivO3CPU.hh"
  62 #include "sim/faults.hh"
  63 #include "sim/full_system.hh"
  64
  65 using namespace std;
  66
  67 template <class Impl>
  68 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  69                                           ThreadID _tid)
  70     : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
  71 {
  72 }
  73
  74 template <class Impl>
  75 void
  76 DefaultCommit<Impl>::TrapEvent::process()
  77 {
  78     // This will get reset by commit if it was switched out at the
  79     // time of this event processing.
  80     commit->trapSquash[tid] = true;
  81 }
  82
  83 template <class Impl>
  84 const char *
  85 DefaultCommit<Impl>::TrapEvent::description() const
  86 {
  87     return "Trap";
  88 }
  89
  90 template <class Impl>
  91 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
  92     : cpu(_cpu),
  93       squashCounter(0),
  94       iewToCommitDelay(params->iewToCommitDelay),
  95       commitToIEWDelay(params->commitToIEWDelay),
  96       renameToROBDelay(params->renameToROBDelay),
  97       fetchToCommitDelay(params->commitToFetchDelay),
  98       renameWidth(params->renameWidth),
  99       commitWidth(params->commitWidth),
 100       numThreads(params->numThreads),
 101       drainPending(false),
 102       switchedOut(false),
 103       trapLatency(params->trapLatency),
 104       canHandleInterrupts(true)
 105 {
 106     _status = Active;
 107     _nextStatus = Inactive;
 108     std::string policy = params->smtCommitPolicy;
 109
 110     //Convert string to lowercase
 111     std::transform(policy.begin(), policy.end(), policy.begin(),
 112                    (int(*)(int)) tolower);
 113
 114     //Assign commit policy
 115     if (policy == "aggressive"){
 116         commitPolicy = Aggressive;
 117
 118         DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
 119     } else if (policy == "roundrobin"){
 120         commitPolicy = RoundRobin;
 121
 122         //Set-Up Priority List
 123         for (ThreadID tid = 0; tid < numThreads; tid++) {
 124             priority_list.push_back(tid);
 125         }
 126
 127         DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
 128     } else if (policy == "oldestready"){
 129         commitPolicy = OldestReady;
 130
 131         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 132     } else {
 133         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 134                "RoundRobin,OldestReady}");
 135     }
 136
 137     for (ThreadID tid = 0; tid < numThreads; tid++) {
 138         commitStatus[tid] = Idle;
 139         changedROBNumEntries[tid] = false;
 140         checkEmptyROB[tid] = false;
 141         trapInFlight[tid] = false;
 142         committedStores[tid] = false;
 143         trapSquash[tid] = false;
 144         tcSquash[tid] = false;
 145         pc[tid].set(0);
 146         lastCommitedSeqNum[tid] = 0;
 147         squashAfterInst[tid] = NULL;
 148     }
 149     interrupt = NoFault;
 150 }
 151
 152 template <class Impl>
 153 std::string
 154 DefaultCommit<Impl>::name() const
 155 {
 156     return cpu->name() + ".commit";
 157 }
 158
 159 template <class Impl>
 160 void
 161 DefaultCommit<Impl>::regStats()
 162 {
 163     using namespace Stats;
 164     commitSquashedInsts
 165         .name(name() + ".commitSquashedInsts")
 166         .desc("The number of squashed insts skipped by commit")
 167         .prereq(commitSquashedInsts);
 168     commitSquashEvents
 169         .name(name() + ".commitSquashEvents")
 170         .desc("The number of times commit is told to squash")
 171         .prereq(commitSquashEvents);
 172     commitNonSpecStalls
 173         .name(name() + ".commitNonSpecStalls")
 174         .desc("The number of times commit has been forced to stall to "
 175               "communicate backwards")
 176         .prereq(commitNonSpecStalls);
 177     branchMispredicts
 178         .name(name() + ".branchMispredicts")
 179         .desc("The number of times a branch was mispredicted")
 180         .prereq(branchMispredicts);
 181     numCommittedDist
 182         .init(0,commitWidth,1)
 183         .name(name() + ".committed_per_cycle")
 184         .desc("Number of insts commited each cycle")
 185         .flags(Stats::pdf)
 186         ;
 187
 188     instsCommitted
 189         .init(cpu->numThreads)
 190         .name(name() + ".committedInsts")
 191         .desc("Number of instructions committed")
 192         .flags(total)
 193         ;
 194
 195     opsCommitted
 196         .init(cpu->numThreads)
 197         .name(name() + ".committedOps")
 198         .desc("Number of ops (including micro ops) committed")
 199         .flags(total)
 200         ;
 201
 202     statComSwp
 203         .init(cpu->numThreads)
 204         .name(name() + ".swp_count")
 205         .desc("Number of s/w prefetches committed")
 206         .flags(total)
 207         ;
 208
 209     statComRefs
 210         .init(cpu->numThreads)
 211         .name(name() +  ".refs")
 212         .desc("Number of memory references committed")
 213         .flags(total)
 214         ;
 215
 216     statComLoads
 217         .init(cpu->numThreads)
 218         .name(name() +  ".loads")
 219         .desc("Number of loads committed")
 220         .flags(total)
 221         ;
 222
 223     statComMembars
 224         .init(cpu->numThreads)
 225         .name(name() +  ".membars")
 226         .desc("Number of memory barriers committed")
 227         .flags(total)
 228         ;
 229
 230     statComBranches
 231         .init(cpu->numThreads)
 232         .name(name() + ".branches")
 233         .desc("Number of branches committed")
 234         .flags(total)
 235         ;
 236
 237     statComFloating
 238         .init(cpu->numThreads)
 239         .name(name() + ".fp_insts")
 240         .desc("Number of committed floating point instructions.")
 241         .flags(total)
 242         ;
 243
 244     statComInteger
 245         .init(cpu->numThreads)
 246         .name(name()+".int_insts")
 247         .desc("Number of committed integer instructions.")
 248         .flags(total)
 249         ;
 250
 251     statComFunctionCalls
 252         .init(cpu->numThreads)
 253         .name(name()+".function_calls")
 254         .desc("Number of function calls committed.")
 255         .flags(total)
 256         ;
 257
 258     commitEligible
 259         .init(cpu->numThreads)
 260         .name(name() + ".bw_limited")
 261         .desc("number of insts not committed due to BW limits")
 262         .flags(total)
 263         ;
 264
 265     commitEligibleSamples
 266         .name(name() + ".bw_lim_events")
 267         .desc("number cycles where commit BW limit reached")
 268         ;
 269 }
 270
 271 template <class Impl>
 272 void
 273 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 274 {
 275     thread = threads;
 276 }
 277
 278 template <class Impl>
 279 void
 280 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 281 {
 282     timeBuffer = tb_ptr;
 283
 284     // Setup wire to send information back to IEW.
 285     toIEW = timeBuffer->getWire(0);
 286
 287     // Setup wire to read data from IEW (for the ROB).
 288     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 289 }
 290
 291 template <class Impl>
 292 void
 293 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 294 {
 295     fetchQueue = fq_ptr;
 296
 297     // Setup wire to get instructions from rename (for the ROB).
 298     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 299 }
 300
 301 template <class Impl>
 302 void
 303 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 304 {
 305     renameQueue = rq_ptr;
 306
 307     // Setup wire to get instructions from rename (for the ROB).
 308     fromRename = renameQueue->getWire(-renameToROBDelay);
 309 }
 310
 311 template <class Impl>
 312 void
 313 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 314 {
 315     iewQueue = iq_ptr;
 316
 317     // Setup wire to get instructions from IEW.
 318     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 319 }
 320
 321 template <class Impl>
 322 void
 323 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 324 {
 325     iewStage = iew_stage;
 326 }
 327
 328 template<class Impl>
 329 void
 330 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 331 {
 332     activeThreads = at_ptr;
 333 }
 334
 335 template <class Impl>
 336 void
 337 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 338 {
 339     for (ThreadID tid = 0; tid < numThreads; tid++)
 340         renameMap[tid] = &rm_ptr[tid];
 341 }
 342
 343 template <class Impl>
 344 void
 345 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 346 {
 347     rob = rob_ptr;
 348 }
 349
 350 template <class Impl>
 351 void
 352 DefaultCommit<Impl>::startupStage()
 353 {
 354     rob->setActiveThreads(activeThreads);
 355     rob->resetEntries();
 356
 357     // Broadcast the number of free entries.
 358     for (ThreadID tid = 0; tid < numThreads; tid++) {
 359         toIEW->commitInfo[tid].usedROB = true;
 360         toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 361         toIEW->commitInfo[tid].emptyROB = true;
 362     }
 363
 364     // Commit must broadcast the number of free entries it has at the
 365     // start of the simulation, so it starts as active.
 366     cpu->activateStage(O3CPU::CommitIdx);
 367
 368     cpu->activityThisCycle();
 369 }
 370
 371 template <class Impl>
 372 bool
 373 DefaultCommit<Impl>::drain()
 374 {
 375     drainPending = true;
 376
 377     return false;
 378 }
 379
 380 template <class Impl>
 381 void
 382 DefaultCommit<Impl>::switchOut()
 383 {
 384     switchedOut = true;
 385     drainPending = false;
 386     rob->switchOut();
 387 }
 388
 389 template <class Impl>
 390 void
 391 DefaultCommit<Impl>::resume()
 392 {
 393     drainPending = false;
 394 }
 395
 396 template <class Impl>
 397 void
 398 DefaultCommit<Impl>::takeOverFrom()
 399 {
 400     switchedOut = false;
 401     _status = Active;
 402     _nextStatus = Inactive;
 403     for (ThreadID tid = 0; tid < numThreads; tid++) {
 404         commitStatus[tid] = Idle;
 405         changedROBNumEntries[tid] = false;
 406         trapSquash[tid] = false;
 407         tcSquash[tid] = false;
 408         squashAfterInst[tid] = NULL;
 409     }
 410     squashCounter = 0;
 411     rob->takeOverFrom();
 412 }
 413
 414 template <class Impl>
 415 void
 416 DefaultCommit<Impl>::updateStatus()
 417 {
 418     // reset ROB changed variable
 419     list<ThreadID>::iterator threads = activeThreads->begin();
 420     list<ThreadID>::iterator end = activeThreads->end();
 421
 422     while (threads != end) {
 423         ThreadID tid = *threads++;
 424
 425         changedROBNumEntries[tid] = false;
 426
 427         // Also check if any of the threads has a trap pending
 428         if (commitStatus[tid] == TrapPending ||
 429             commitStatus[tid] == FetchTrapPending) {
 430             _nextStatus = Active;
 431         }
 432     }
 433
 434     if (_nextStatus == Inactive && _status == Active) {
 435         DPRINTF(Activity, "Deactivating stage.\n");
 436         cpu->deactivateStage(O3CPU::CommitIdx);
 437     } else if (_nextStatus == Active && _status == Inactive) {
 438         DPRINTF(Activity, "Activating stage.\n");
 439         cpu->activateStage(O3CPU::CommitIdx);
 440     }
 441
 442     _status = _nextStatus;
 443 }
 444
 445 template <class Impl>
 446 void
 447 DefaultCommit<Impl>::setNextStatus()
 448 {
 449     int squashes = 0;
 450
 451     list<ThreadID>::iterator threads = activeThreads->begin();
 452     list<ThreadID>::iterator end = activeThreads->end();
 453
 454     while (threads != end) {
 455         ThreadID tid = *threads++;
 456
 457         if (commitStatus[tid] == ROBSquashing) {
 458             squashes++;
 459         }
 460     }
 461
 462     squashCounter = squashes;
 463
 464     // If commit is currently squashing, then it will have activity for the
 465     // next cycle. Set its next status as active.
 466     if (squashCounter) {
 467         _nextStatus = Active;
 468     }
 469 }
 470
 471 template <class Impl>
 472 bool
 473 DefaultCommit<Impl>::changedROBEntries()
 474 {
 475     list<ThreadID>::iterator threads = activeThreads->begin();
 476     list<ThreadID>::iterator end = activeThreads->end();
 477
 478     while (threads != end) {
 479         ThreadID tid = *threads++;
 480
 481         if (changedROBNumEntries[tid]) {
 482             return true;
 483         }
 484     }
 485
 486     return false;
 487 }
 488
 489 template <class Impl>
 490 size_t
 491 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
 492 {
 493     return rob->numFreeEntries(tid);
 494 }
 495
 496 template <class Impl>
 497 void
 498 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
 499 {
 500     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 501
 502     TrapEvent *trap = new TrapEvent(this, tid);
 503
 504     cpu->schedule(trap, cpu->clockEdge(trapLatency));
 505     trapInFlight[tid] = true;
 506     thread[tid]->trapPending = true;
 507 }
 508
 509 template <class Impl>
 510 void
 511 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
 512 {
 513     assert(!trapInFlight[tid]);
 514     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 515
 516     tcSquash[tid] = true;
 517 }
 518
 519 template <class Impl>
 520 void
 521 DefaultCommit<Impl>::squashAll(ThreadID tid)
 522 {
 523     // If we want to include the squashing instruction in the squash,
 524     // then use one older sequence number.
 525     // Hopefully this doesn't mess things up.  Basically I want to squash
 526     // all instructions of this thread.
 527     InstSeqNum squashed_inst = rob->isEmpty() ?
 528         lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
 529
 530     // All younger instructions will be squashed. Set the sequence
 531     // number as the youngest instruction in the ROB (0 in this case.
 532     // Hopefully nothing breaks.)
 533     youngestSeqNum[tid] = lastCommitedSeqNum[tid];
 534
 535     rob->squash(squashed_inst, tid);
 536     changedROBNumEntries[tid] = true;
 537
 538     // Send back the sequence number of the squashed instruction.
 539     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 540
 541     // Send back the squash signal to tell stages that they should
 542     // squash.
 543     toIEW->commitInfo[tid].squash = true;
 544
 545     // Send back the rob squashing signal so other stages know that
 546     // the ROB is in the process of squashing.
 547     toIEW->commitInfo[tid].robSquashing = true;
 548
 549     toIEW->commitInfo[tid].mispredictInst = NULL;
 550     toIEW->commitInfo[tid].squashInst = NULL;
 551
 552     toIEW->commitInfo[tid].pc = pc[tid];
 553 }
 554
 555 template <class Impl>
 556 void
 557 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
 558 {
 559     squashAll(tid);
 560
 561     DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
 562
 563     thread[tid]->trapPending = false;
 564     thread[tid]->noSquashFromTC = false;
 565     trapInFlight[tid] = false;
 566
 567     trapSquash[tid] = false;
 568
 569     commitStatus[tid] = ROBSquashing;
 570     cpu->activityThisCycle();
 571 }
 572
 573 template <class Impl>
 574 void
 575 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
 576 {
 577     squashAll(tid);
 578
 579     DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
 580
 581     thread[tid]->noSquashFromTC = false;
 582     assert(!thread[tid]->trapPending);
 583
 584     commitStatus[tid] = ROBSquashing;
 585     cpu->activityThisCycle();
 586
 587     tcSquash[tid] = false;
 588 }
 589
 590 template <class Impl>
 591 void
 592 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
 593 {
 594     DPRINTF(Commit, "Squashing after squash after request, "
 595             "restarting at PC %s\n", pc[tid]);
 596
 597     squashAll(tid);
 598     // Make sure to inform the fetch stage of which instruction caused
 599     // the squash. It'll try to re-fetch an instruction executing in
 600     // microcode unless this is set.
 601     toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
 602     squashAfterInst[tid] = NULL;
 603
 604     commitStatus[tid] = ROBSquashing;
 605     cpu->activityThisCycle();
 606 }
 607
 608 template <class Impl>
 609 void
 610 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
 611 {
 612     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
 613             tid, head_inst->seqNum);
 614
 615     assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
 616     commitStatus[tid] = SquashAfterPending;
 617     squashAfterInst[tid] = head_inst;
 618 }
 619
 620 template <class Impl>
 621 void
 622 DefaultCommit<Impl>::tick()
 623 {
 624     wroteToTimeBuffer = false;
 625     _nextStatus = Inactive;
 626
 627     if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
 628         interrupt == NoFault) {
 629         cpu->signalDrained();
 630         drainPending = false;
 631         return;
 632     }
 633
 634     if (activeThreads->empty())
 635         return;
 636
 637     list<ThreadID>::iterator threads = activeThreads->begin();
 638     list<ThreadID>::iterator end = activeThreads->end();
 639
 640     // Check if any of the threads are done squashing.  Change the
 641     // status if they are done.
 642     while (threads != end) {
 643         ThreadID tid = *threads++;
 644
 645         // Clear the bit saying if the thread has committed stores
 646         // this cycle.
 647         committedStores[tid] = false;
 648
 649         if (commitStatus[tid] == ROBSquashing) {
 650
 651             if (rob->isDoneSquashing(tid)) {
 652                 commitStatus[tid] = Running;
 653             } else {
 654                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 655                         " insts this cycle.\n", tid);
 656                 rob->doSquash(tid);
 657                 toIEW->commitInfo[tid].robSquashing = true;
 658                 wroteToTimeBuffer = true;
 659             }
 660         }
 661     }
 662
 663     commit();
 664
 665     markCompletedInsts();
 666
 667     threads = activeThreads->begin();
 668
 669     while (threads != end) {
 670         ThreadID tid = *threads++;
 671
 672         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 673             // The ROB has more instructions it can commit. Its next status
 674             // will be active.
 675             _nextStatus = Active;
 676
 677             DynInstPtr inst = rob->readHeadInst(tid);
 678
 679             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
 680                     " ROB and ready to commit\n",
 681                     tid, inst->seqNum, inst->pcState());
 682
 683         } else if (!rob->isEmpty(tid)) {
 684             DynInstPtr inst = rob->readHeadInst(tid);
 685
 686             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 687                     "%s is head of ROB and not ready\n",
 688                     tid, inst->seqNum, inst->pcState());
 689         }
 690
 691         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 692                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 693     }
 694
 695
 696     if (wroteToTimeBuffer) {
 697         DPRINTF(Activity, "Activity This Cycle.\n");
 698         cpu->activityThisCycle();
 699     }
 700
 701     updateStatus();
 702 }
 703
 704 template <class Impl>
 705 void
 706 DefaultCommit<Impl>::handleInterrupt()
 707 {
 708     // Verify that we still have an interrupt to handle
 709     if (!cpu->checkInterrupts(cpu->tcBase(0))) {
 710         DPRINTF(Commit, "Pending interrupt is cleared by master before "
 711                 "it got handled. Restart fetching from the orig path.\n");
 712         toIEW->commitInfo[0].clearInterrupt = true;
 713         interrupt = NoFault;
 714         return;
 715     }
 716
 717     // Wait until all in flight instructions are finished before enterring
 718     // the interrupt.
 719     if (canHandleInterrupts && cpu->instList.empty()) {
 720         // Squash or record that I need to squash this cycle if
 721         // an interrupt needed to be handled.
 722         DPRINTF(Commit, "Interrupt detected.\n");
 723
 724         // Clear the interrupt now that it's going to be handled
 725         toIEW->commitInfo[0].clearInterrupt = true;
 726
 727         assert(!thread[0]->noSquashFromTC);
 728         thread[0]->noSquashFromTC = true;
 729
 730         if (cpu->checker) {
 731             cpu->checker->handlePendingInt();
 732         }
 733
 734         // CPU will handle interrupt.
 735         cpu->processInterrupts(interrupt);
 736
 737         thread[0]->noSquashFromTC = false;
 738
 739         commitStatus[0] = TrapPending;
 740
 741         // Generate trap squash event.
 742         generateTrapEvent(0);
 743
 744         interrupt = NoFault;
 745     } else {
 746         DPRINTF(Commit, "Interrupt pending: instruction is %sin "
 747                 "flight, ROB is %sempty\n",
 748                 canHandleInterrupts ? "not " : "",
 749                 cpu->instList.empty() ? "" : "not " );
 750     }
 751 }
 752
 753 template <class Impl>
 754 void
 755 DefaultCommit<Impl>::propagateInterrupt()
 756 {
 757     if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
 758             tcSquash[0])
 759         return;
 760
 761     // Process interrupts if interrupts are enabled, not in PAL
 762     // mode, and no other traps or external squashes are currently
 763     // pending.
 764     // @todo: Allow other threads to handle interrupts.
 765
 766     // Get any interrupt that happened
 767     interrupt = cpu->getInterrupts();
 768
 769     // Tell fetch that there is an interrupt pending.  This
 770     // will make fetch wait until it sees a non PAL-mode PC,
 771     // at which point it stops fetching instructions.
 772     if (interrupt != NoFault)
 773         toIEW->commitInfo[0].interruptPending = true;
 774 }
 775
 776 template <class Impl>
 777 void
 778 DefaultCommit<Impl>::commit()
 779 {
 780     if (FullSystem) {
 781         // Check if we have a interrupt and get read to handle it
 782         if (cpu->checkInterrupts(cpu->tcBase(0)))
 783             propagateInterrupt();
 784     }
 785
 786     ////////////////////////////////////
 787     // Check for any possible squashes, handle them first
 788     ////////////////////////////////////
 789     list<ThreadID>::iterator threads = activeThreads->begin();
 790     list<ThreadID>::iterator end = activeThreads->end();
 791
 792     while (threads != end) {
 793         ThreadID tid = *threads++;
 794
 795         // Not sure which one takes priority.  I think if we have
 796         // both, that's a bad sign.
 797         if (trapSquash[tid] == true) {
 798             assert(!tcSquash[tid]);
 799             squashFromTrap(tid);
 800         } else if (tcSquash[tid] == true) {
 801             assert(commitStatus[tid] != TrapPending);
 802             squashFromTC(tid);
 803         } else if (commitStatus[tid] == SquashAfterPending) {
 804             // A squash from the previous cycle of the commit stage (i.e.,
 805             // commitInsts() called squashAfter) is pending. Squash the
 806             // thread now.
 807             squashFromSquashAfter(tid);
 808         }
 809
 810         // Squashed sequence number must be older than youngest valid
 811         // instruction in the ROB. This prevents squashes from younger
 812         // instructions overriding squashes from older instructions.
 813         if (fromIEW->squash[tid] &&
 814             commitStatus[tid] != TrapPending &&
 815             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 816
 817             if (fromIEW->mispredictInst[tid]) {
 818                 DPRINTF(Commit,
 819                     "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
 820                     tid,
 821                     fromIEW->mispredictInst[tid]->instAddr(),
 822                     fromIEW->squashedSeqNum[tid]);
 823             } else {
 824                 DPRINTF(Commit,
 825                     "[tid:%i]: Squashing due to order violation [sn:%i]\n",
 826                     tid, fromIEW->squashedSeqNum[tid]);
 827             }
 828
 829             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 830                     tid,
 831                     fromIEW->pc[tid].nextInstAddr());
 832
 833             commitStatus[tid] = ROBSquashing;
 834
 835             // If we want to include the squashing instruction in the squash,
 836             // then use one older sequence number.
 837             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 838
 839             if (fromIEW->includeSquashInst[tid] == true) {
 840                 squashed_inst--;
 841             }
 842
 843             // All younger instructions will be squashed. Set the sequence
 844             // number as the youngest instruction in the ROB.
 845             youngestSeqNum[tid] = squashed_inst;
 846
 847             rob->squash(squashed_inst, tid);
 848             changedROBNumEntries[tid] = true;
 849
 850             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 851
 852             toIEW->commitInfo[tid].squash = true;
 853
 854             // Send back the rob squashing signal so other stages know that
 855             // the ROB is in the process of squashing.
 856             toIEW->commitInfo[tid].robSquashing = true;
 857
 858             toIEW->commitInfo[tid].mispredictInst =
 859                 fromIEW->mispredictInst[tid];
 860             toIEW->commitInfo[tid].branchTaken =
 861                 fromIEW->branchTaken[tid];
 862             toIEW->commitInfo[tid].squashInst =
 863                                     rob->findInst(tid, squashed_inst);
 864             if (toIEW->commitInfo[tid].mispredictInst) {
 865                 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
 866                      toIEW->commitInfo[tid].branchTaken = true;
 867                 }
 868             }
 869
 870             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 871
 872             if (toIEW->commitInfo[tid].mispredictInst) {
 873                 ++branchMispredicts;
 874             }
 875         }
 876
 877     }
 878
 879     setNextStatus();
 880
 881     if (squashCounter != numThreads) {
 882         // If we're not currently squashing, then get instructions.
 883         getInsts();
 884
 885         // Try to commit any instructions.
 886         commitInsts();
 887     }
 888
 889     //Check for any activity
 890     threads = activeThreads->begin();
 891
 892     while (threads != end) {
 893         ThreadID tid = *threads++;
 894
 895         if (changedROBNumEntries[tid]) {
 896             toIEW->commitInfo[tid].usedROB = true;
 897             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 898
 899             wroteToTimeBuffer = true;
 900             changedROBNumEntries[tid] = false;
 901             if (rob->isEmpty(tid))
 902                 checkEmptyROB[tid] = true;
 903         }
 904
 905         // ROB is only considered "empty" for previous stages if: a)
 906         // ROB is empty, b) there are no outstanding stores, c) IEW
 907         // stage has received any information regarding stores that
 908         // committed.
 909         // c) is checked by making sure to not consider the ROB empty
 910         // on the same cycle as when stores have been committed.
 911         // @todo: Make this handle multi-cycle communication between
 912         // commit and IEW.
 913         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
 914             !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
 915             checkEmptyROB[tid] = false;
 916             toIEW->commitInfo[tid].usedROB = true;
 917             toIEW->commitInfo[tid].emptyROB = true;
 918             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 919             wroteToTimeBuffer = true;
 920         }
 921
 922     }
 923 }
 924
 925 template <class Impl>
 926 void
 927 DefaultCommit<Impl>::commitInsts()
 928 {
 929     ////////////////////////////////////
 930     // Handle commit
 931     // Note that commit will be handled prior to putting new
 932     // instructions in the ROB so that the ROB only tries to commit
 933     // instructions it has in this current cycle, and not instructions
 934     // it is writing in during this cycle.  Can't commit and squash
 935     // things at the same time...
 936     ////////////////////////////////////
 937
 938     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 939
 940     unsigned num_committed = 0;
 941
 942     DynInstPtr head_inst;
 943
 944     // Commit as many instructions as possible until the commit bandwidth
 945     // limit is reached, or it becomes impossible to commit any more.
 946     while (num_committed < commitWidth) {
 947         // Check for any interrupt that we've already squashed for
 948         // and start processing it.
 949         if (interrupt != NoFault)
 950             handleInterrupt();
 951
 952         int commit_thread = getCommittingThread();
 953
 954         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 955             break;
 956
 957         head_inst = rob->readHeadInst(commit_thread);
 958
 959         ThreadID tid = head_inst->threadNumber;
 960
 961         assert(tid == commit_thread);
 962
 963         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 964                 head_inst->seqNum, tid);
 965
 966         // If the head instruction is squashed, it is ready to retire
 967         // (be removed from the ROB) at any time.
 968         if (head_inst->isSquashed()) {
 969
 970             DPRINTF(Commit, "Retiring squashed instruction from "
 971                     "ROB.\n");
 972
 973             rob->retireHead(commit_thread);
 974
 975             ++commitSquashedInsts;
 976
 977             // Record that the number of ROB entries has changed.
 978             changedROBNumEntries[tid] = true;
 979         } else {
 980             pc[tid] = head_inst->pcState();
 981
 982             // Increment the total number of non-speculative instructions
 983             // executed.
 984             // Hack for now: it really shouldn't happen until after the
 985             // commit is deemed to be successful, but this count is needed
 986             // for syscalls.
 987             thread[tid]->funcExeInst++;
 988
 989             // Try to commit the head instruction.
 990             bool commit_success = commitHead(head_inst, num_committed);
 991
 992             if (commit_success) {
 993                 ++num_committed;
 994
 995                 changedROBNumEntries[tid] = true;
 996
 997                 // Set the doneSeqNum to the youngest committed instruction.
 998                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 999
1000                 if (tid == 0) {
1001                     canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
1002                                            ((THE_ISA != ALPHA_ISA) ||
1003                                              (!(pc[0].instAddr() & 0x3)));
1004                 }
1005
1006                 // Updates misc. registers.
1007                 head_inst->updateMiscRegs();
1008
1009                 cpu->traceFunctions(pc[tid].instAddr());
1010
1011                 TheISA::advancePC(pc[tid], head_inst->staticInst);
1012
1013                 // Keep track of the last sequence number commited
1014                 lastCommitedSeqNum[tid] = head_inst->seqNum;
1015
1016                 // If this is an instruction that doesn't play nicely with
1017                 // others squash everything and restart fetch
1018                 if (head_inst->isSquashAfter())
1019                     squashAfter(tid, head_inst);
1020
1021                 int count = 0;
1022                 Addr oldpc;
1023                 // Debug statement.  Checks to make sure we're not
1024                 // currently updating state while handling PC events.
1025                 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1026                 do {
1027                     oldpc = pc[tid].instAddr();
1028                     cpu->system->pcEventQueue.service(thread[tid]->getTC());
1029                     count++;
1030                 } while (oldpc != pc[tid].instAddr());
1031                 if (count > 1) {
1032                     DPRINTF(Commit,
1033                             "PC skip function event, stopping commit\n");
1034                     break;
1035                 }
1036             } else {
1037                 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1038                         "[tid:%i] [sn:%i].\n",
1039                         head_inst->pcState(), tid ,head_inst->seqNum);
1040                 break;
1041             }
1042         }
1043     }
1044
1045     DPRINTF(CommitRate, "%i\n", num_committed);
1046     numCommittedDist.sample(num_committed);
1047
1048     if (num_committed == commitWidth) {
1049         commitEligibleSamples++;
1050     }
1051 }
1052
1053 template <class Impl>
1054 bool
1055 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1056 {
1057     assert(head_inst);
1058
1059     ThreadID tid = head_inst->threadNumber;
1060
1061     // If the instruction is not executed yet, then it will need extra
1062     // handling.  Signal backwards that it should be executed.
1063     if (!head_inst->isExecuted()) {
1064         // Keep this number correct.  We have not yet actually executed
1065         // and committed this instruction.
1066         thread[tid]->funcExeInst--;
1067
1068         if (head_inst->isNonSpeculative() ||
1069             head_inst->isStoreConditional() ||
1070             head_inst->isMemBarrier() ||
1071             head_inst->isWriteBarrier()) {
1072
1073             DPRINTF(Commit, "Encountered a barrier or non-speculative "
1074                     "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1075                     head_inst->seqNum, head_inst->pcState());
1076
1077             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1078                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1079                 return false;
1080             }
1081
1082             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1083
1084             // Change the instruction so it won't try to commit again until
1085             // it is executed.
1086             head_inst->clearCanCommit();
1087
1088             ++commitNonSpecStalls;
1089
1090             return false;
1091         } else if (head_inst->isLoad()) {
1092             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1093                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1094                 return false;
1095             }
1096
1097             assert(head_inst->uncacheable());
1098             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1099                     head_inst->seqNum, head_inst->pcState());
1100
1101             // Send back the non-speculative instruction's sequence
1102             // number.  Tell the lsq to re-execute the load.
1103             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1104             toIEW->commitInfo[tid].uncached = true;
1105             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1106
1107             head_inst->clearCanCommit();
1108
1109             return false;
1110         } else {
1111             panic("Trying to commit un-executed instruction "
1112                   "of unknown type!\n");
1113         }
1114     }
1115
1116     if (head_inst->isThreadSync()) {
1117         // Not handled for now.
1118         panic("Thread sync instructions are not handled yet.\n");
1119     }
1120
1121     // Check if the instruction caused a fault.  If so, trap.
1122     Fault inst_fault = head_inst->getFault();
1123
1124     // Stores mark themselves as completed.
1125     if (!head_inst->isStore() && inst_fault == NoFault) {
1126         head_inst->setCompleted();
1127     }
1128
1129     // Use checker prior to updating anything due to traps or PC
1130     // based events.
1131     if (cpu->checker) {
1132         cpu->checker->verify(head_inst);
1133     }
1134
1135     if (inst_fault != NoFault) {
1136         DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1137                 head_inst->seqNum, head_inst->pcState());
1138
1139         if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1140             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1141             return false;
1142         }
1143
1144         head_inst->setCompleted();
1145
1146         if (cpu->checker) {
1147             // Need to check the instruction before its fault is processed
1148             cpu->checker->verify(head_inst);
1149         }
1150
1151         assert(!thread[tid]->noSquashFromTC);
1152
1153         // Mark that we're in state update mode so that the trap's
1154         // execution doesn't generate extra squashes.
1155         thread[tid]->noSquashFromTC = true;
1156
1157         // Execute the trap.  Although it's slightly unrealistic in
1158         // terms of timing (as it doesn't wait for the full timing of
1159         // the trap event to complete before updating state), it's
1160         // needed to update the state as soon as possible.  This
1161         // prevents external agents from changing any specific state
1162         // that the trap need.
1163         cpu->trap(inst_fault, tid, head_inst->staticInst);
1164
1165         // Exit state update mode to avoid accidental updating.
1166         thread[tid]->noSquashFromTC = false;
1167
1168         commitStatus[tid] = TrapPending;
1169
1170         DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1171             head_inst->seqNum);
1172         if (head_inst->traceData) {
1173             if (DTRACE(ExecFaulting)) {
1174                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1175                 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1176                 head_inst->traceData->dump();
1177             }
1178             delete head_inst->traceData;
1179             head_inst->traceData = NULL;
1180         }
1181
1182         // Generate trap squash event.
1183         generateTrapEvent(tid);
1184         return false;
1185     }
1186
1187     updateComInstStats(head_inst);
1188
1189     if (FullSystem) {
1190         if (thread[tid]->profile) {
1191             thread[tid]->profilePC = head_inst->instAddr();
1192             ProfileNode *node = thread[tid]->profile->consume(
1193                     thread[tid]->getTC(), head_inst->staticInst);
1194
1195             if (node)
1196                 thread[tid]->profileNode = node;
1197         }
1198         if (CPA::available()) {
1199             if (head_inst->isControl()) {
1200                 ThreadContext *tc = thread[tid]->getTC();
1201                 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1202             }
1203         }
1204     }
1205     DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1206             head_inst->seqNum, head_inst->pcState());
1207     if (head_inst->traceData) {
1208         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1209         head_inst->traceData->setCPSeq(thread[tid]->numOp);
1210         head_inst->traceData->dump();
1211         delete head_inst->traceData;
1212         head_inst->traceData = NULL;
1213     }
1214     if (head_inst->isReturn()) {
1215         DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1216                         head_inst->seqNum, head_inst->pcState());
1217     }
1218
1219     // Update the commit rename map
1220     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1221         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1222                                  head_inst->renamedDestRegIdx(i));
1223     }
1224
1225     // Finally clear the head ROB entry.
1226     rob->retireHead(tid);
1227
1228 #if TRACING_ON
1229     head_inst->commitTick = curTick() - head_inst->fetchTick;
1230 #endif
1231
1232     // If this was a store, record it for this cycle.
1233     if (head_inst->isStore())
1234         committedStores[tid] = true;
1235
1236     // Return true to indicate that we have committed an instruction.
1237     return true;
1238 }
1239
1240 template <class Impl>
1241 void
1242 DefaultCommit<Impl>::getInsts()
1243 {
1244     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1245
1246     // Read any renamed instructions and place them into the ROB.
1247     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1248
1249     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1250         DynInstPtr inst;
1251
1252         inst = fromRename->insts[inst_num];
1253         ThreadID tid = inst->threadNumber;
1254
1255         if (!inst->isSquashed() &&
1256             commitStatus[tid] != ROBSquashing &&
1257             commitStatus[tid] != TrapPending) {
1258             changedROBNumEntries[tid] = true;
1259
1260             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1261                     inst->pcState(), inst->seqNum, tid);
1262
1263             rob->insertInst(inst);
1264
1265             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1266
1267             youngestSeqNum[tid] = inst->seqNum;
1268         } else {
1269             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1270                     "squashed, skipping.\n",
1271                     inst->pcState(), inst->seqNum, tid);
1272         }
1273     }
1274 }
1275
1276 template <class Impl>
1277 void
1278 DefaultCommit<Impl>::skidInsert()
1279 {
1280     DPRINTF(Commit, "Attempting to any instructions from rename into "
1281             "skidBuffer.\n");
1282
1283     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1284         DynInstPtr inst = fromRename->insts[inst_num];
1285
1286         if (!inst->isSquashed()) {
1287             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1288                     "skidBuffer.\n", inst->pcState(), inst->seqNum,
1289                     inst->threadNumber);
1290             skidBuffer.push(inst);
1291         } else {
1292             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1293                     "squashed, skipping.\n",
1294                     inst->pcState(), inst->seqNum, inst->threadNumber);
1295         }
1296     }
1297 }
1298
1299 template <class Impl>
1300 void
1301 DefaultCommit<Impl>::markCompletedInsts()
1302 {
1303     // Grab completed insts out of the IEW instruction queue, and mark
1304     // instructions completed within the ROB.
1305     for (int inst_num = 0;
1306          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1307          ++inst_num)
1308     {
1309         if (!fromIEW->insts[inst_num]->isSquashed()) {
1310             DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1311                     "within ROB.\n",
1312                     fromIEW->insts[inst_num]->threadNumber,
1313                     fromIEW->insts[inst_num]->pcState(),
1314                     fromIEW->insts[inst_num]->seqNum);
1315
1316             // Mark the instruction as ready to commit.
1317             fromIEW->insts[inst_num]->setCanCommit();
1318         }
1319     }
1320 }
1321
1322 template <class Impl>
1323 bool
1324 DefaultCommit<Impl>::robDoneSquashing()
1325 {
1326     list<ThreadID>::iterator threads = activeThreads->begin();
1327     list<ThreadID>::iterator end = activeThreads->end();
1328
1329     while (threads != end) {
1330         ThreadID tid = *threads++;
1331
1332         if (!rob->isDoneSquashing(tid))
1333             return false;
1334     }
1335
1336     return true;
1337 }
1338
1339 template <class Impl>
1340 void
1341 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1342 {
1343     ThreadID tid = inst->threadNumber;
1344
1345     if (!inst->isMicroop() || inst->isLastMicroop())
1346         instsCommitted[tid]++;
1347     opsCommitted[tid]++;
1348
1349     // To match the old model, don't count nops and instruction
1350     // prefetches towards the total commit count.
1351     if (!inst->isNop() && !inst->isInstPrefetch()) {
1352         cpu->instDone(tid, inst);
1353     }
1354
1355     //
1356     //  Control Instructions
1357     //
1358     if (inst->isControl())
1359         statComBranches[tid]++;
1360
1361     //
1362     //  Memory references
1363     //
1364     if (inst->isMemRef()) {
1365         statComRefs[tid]++;
1366
1367         if (inst->isLoad()) {
1368             statComLoads[tid]++;
1369         }
1370     }
1371
1372     if (inst->isMemBarrier()) {
1373         statComMembars[tid]++;
1374     }
1375
1376     // Integer Instruction
1377     if (inst->isInteger())
1378         statComInteger[tid]++;
1379
1380     // Floating Point Instruction
1381     if (inst->isFloating())
1382         statComFloating[tid]++;
1383
1384     // Function Calls
1385     if (inst->isCall())
1386         statComFunctionCalls[tid]++;
1387
1388 }
1389
1390 ////////////////////////////////////////
1391 //                                    //
1392 //  SMT COMMIT POLICY MAINTAINED HERE //
1393 //                                    //
1394 ////////////////////////////////////////
1395 template <class Impl>
1396 ThreadID
1397 DefaultCommit<Impl>::getCommittingThread()
1398 {
1399     if (numThreads > 1) {
1400         switch (commitPolicy) {
1401
1402           case Aggressive:
1403             //If Policy is Aggressive, commit will call
1404             //this function multiple times per
1405             //cycle
1406             return oldestReady();
1407
1408           case RoundRobin:
1409             return roundRobin();
1410
1411           case OldestReady:
1412             return oldestReady();
1413
1414           default:
1415             return InvalidThreadID;
1416         }
1417     } else {
1418         assert(!activeThreads->empty());
1419         ThreadID tid = activeThreads->front();
1420
1421         if (commitStatus[tid] == Running ||
1422             commitStatus[tid] == Idle ||
1423             commitStatus[tid] == FetchTrapPending) {
1424             return tid;
1425         } else {
1426             return InvalidThreadID;
1427         }
1428     }
1429 }
1430
1431 template<class Impl>
1432 ThreadID
1433 DefaultCommit<Impl>::roundRobin()
1434 {
1435     list<ThreadID>::iterator pri_iter = priority_list.begin();
1436     list<ThreadID>::iterator end      = priority_list.end();
1437
1438     while (pri_iter != end) {
1439         ThreadID tid = *pri_iter;
1440
1441         if (commitStatus[tid] == Running ||
1442             commitStatus[tid] == Idle ||
1443             commitStatus[tid] == FetchTrapPending) {
1444
1445             if (rob->isHeadReady(tid)) {
1446                 priority_list.erase(pri_iter);
1447                 priority_list.push_back(tid);
1448
1449                 return tid;
1450             }
1451         }
1452
1453         pri_iter++;
1454     }
1455
1456     return InvalidThreadID;
1457 }
1458
1459 template<class Impl>
1460 ThreadID
1461 DefaultCommit<Impl>::oldestReady()
1462 {
1463     unsigned oldest = 0;
1464     bool first = true;
1465
1466     list<ThreadID>::iterator threads = activeThreads->begin();
1467     list<ThreadID>::iterator end = activeThreads->end();
1468
1469     while (threads != end) {
1470         ThreadID tid = *threads++;
1471
1472         if (!rob->isEmpty(tid) &&
1473             (commitStatus[tid] == Running ||
1474              commitStatus[tid] == Idle ||
1475              commitStatus[tid] == FetchTrapPending)) {
1476
1477             if (rob->isHeadReady(tid)) {
1478
1479                 DynInstPtr head_inst = rob->readHeadInst(tid);
1480
1481                 if (first) {
1482                     oldest = tid;
1483                     first = false;
1484                 } else if (head_inst->seqNum < oldest) {
1485                     oldest = tid;
1486                 }
1487             }
1488         }
1489     }
1490
1491     if (!first) {
1492         return oldest;
1493     } else {
1494         return InvalidThreadID;
1495     }
1496 }