src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <algorithm>
  45 #include <string>
  46
  47 #include "arch/utility.hh"
  48 #include "base/cp_annotate.hh"
  49 #include "base/loader/symtab.hh"
  50 #include "cpu/timebuf.hh"
  51 #include "config/full_system.hh"
  52 #include "config/the_isa.hh"
  53 #include "config/use_checker.hh"
  54 #include "cpu/exetrace.hh"
  55 #include "cpu/o3/commit.hh"
  56 #include "cpu/o3/thread_state.hh"
  57 #include "params/DerivO3CPU.hh"
  58
  59 #if USE_CHECKER
  60 #include "cpu/checker/cpu.hh"
  61 #endif
  62
  63 using namespace std;
  64
  65 template <class Impl>
  66 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  67                                           ThreadID _tid)
  68     : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
  69 {
  70     this->setFlags(AutoDelete);
  71 }
  72
  73 template <class Impl>
  74 void
  75 DefaultCommit<Impl>::TrapEvent::process()
  76 {
  77     // This will get reset by commit if it was switched out at the
  78     // time of this event processing.
  79     commit->trapSquash[tid] = true;
  80 }
  81
  82 template <class Impl>
  83 const char *
  84 DefaultCommit<Impl>::TrapEvent::description() const
  85 {
  86     return "Trap";
  87 }
  88
  89 template <class Impl>
  90 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
  91     : cpu(_cpu),
  92       squashCounter(0),
  93       iewToCommitDelay(params->iewToCommitDelay),
  94       commitToIEWDelay(params->commitToIEWDelay),
  95       renameToROBDelay(params->renameToROBDelay),
  96       fetchToCommitDelay(params->commitToFetchDelay),
  97       renameWidth(params->renameWidth),
  98       commitWidth(params->commitWidth),
  99       numThreads(params->numThreads),
 100       drainPending(false),
 101       switchedOut(false),
 102       trapLatency(params->trapLatency)
 103 {
 104     _status = Active;
 105     _nextStatus = Inactive;
 106     std::string policy = params->smtCommitPolicy;
 107
 108     //Convert string to lowercase
 109     std::transform(policy.begin(), policy.end(), policy.begin(),
 110                    (int(*)(int)) tolower);
 111
 112     //Assign commit policy
 113     if (policy == "aggressive"){
 114         commitPolicy = Aggressive;
 115
 116         DPRINTF(Commit,"Commit Policy set to Aggressive.");
 117     } else if (policy == "roundrobin"){
 118         commitPolicy = RoundRobin;
 119
 120         //Set-Up Priority List
 121         for (ThreadID tid = 0; tid < numThreads; tid++) {
 122             priority_list.push_back(tid);
 123         }
 124
 125         DPRINTF(Commit,"Commit Policy set to Round Robin.");
 126     } else if (policy == "oldestready"){
 127         commitPolicy = OldestReady;
 128
 129         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 130     } else {
 131         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 132                "RoundRobin,OldestReady}");
 133     }
 134
 135     for (ThreadID tid = 0; tid < numThreads; tid++) {
 136         commitStatus[tid] = Idle;
 137         changedROBNumEntries[tid] = false;
 138         checkEmptyROB[tid] = false;
 139         trapInFlight[tid] = false;
 140         committedStores[tid] = false;
 141         trapSquash[tid] = false;
 142         tcSquash[tid] = false;
 143         pc[tid].set(0);
 144         lastCommitedSeqNum[tid] = 0;
 145     }
 146 #if FULL_SYSTEM
 147     interrupt = NoFault;
 148 #endif
 149 }
 150
 151 template <class Impl>
 152 std::string
 153 DefaultCommit<Impl>::name() const
 154 {
 155     return cpu->name() + ".commit";
 156 }
 157
 158 template <class Impl>
 159 void
 160 DefaultCommit<Impl>::regStats()
 161 {
 162     using namespace Stats;
 163     commitCommittedInsts
 164         .name(name() + ".commitCommittedInsts")
 165         .desc("The number of committed instructions")
 166         .prereq(commitCommittedInsts);
 167     commitSquashedInsts
 168         .name(name() + ".commitSquashedInsts")
 169         .desc("The number of squashed insts skipped by commit")
 170         .prereq(commitSquashedInsts);
 171     commitSquashEvents
 172         .name(name() + ".commitSquashEvents")
 173         .desc("The number of times commit is told to squash")
 174         .prereq(commitSquashEvents);
 175     commitNonSpecStalls
 176         .name(name() + ".commitNonSpecStalls")
 177         .desc("The number of times commit has been forced to stall to "
 178               "communicate backwards")
 179         .prereq(commitNonSpecStalls);
 180     branchMispredicts
 181         .name(name() + ".branchMispredicts")
 182         .desc("The number of times a branch was mispredicted")
 183         .prereq(branchMispredicts);
 184     numCommittedDist
 185         .init(0,commitWidth,1)
 186         .name(name() + ".COM:committed_per_cycle")
 187         .desc("Number of insts commited each cycle")
 188         .flags(Stats::pdf)
 189         ;
 190
 191     statComInst
 192         .init(cpu->numThreads)
 193         .name(name() + ".COM:count")
 194         .desc("Number of instructions committed")
 195         .flags(total)
 196         ;
 197
 198     statComSwp
 199         .init(cpu->numThreads)
 200         .name(name() + ".COM:swp_count")
 201         .desc("Number of s/w prefetches committed")
 202         .flags(total)
 203         ;
 204
 205     statComRefs
 206         .init(cpu->numThreads)
 207         .name(name() +  ".COM:refs")
 208         .desc("Number of memory references committed")
 209         .flags(total)
 210         ;
 211
 212     statComLoads
 213         .init(cpu->numThreads)
 214         .name(name() +  ".COM:loads")
 215         .desc("Number of loads committed")
 216         .flags(total)
 217         ;
 218
 219     statComMembars
 220         .init(cpu->numThreads)
 221         .name(name() +  ".COM:membars")
 222         .desc("Number of memory barriers committed")
 223         .flags(total)
 224         ;
 225
 226     statComBranches
 227         .init(cpu->numThreads)
 228         .name(name() + ".COM:branches")
 229         .desc("Number of branches committed")
 230         .flags(total)
 231         ;
 232
 233     statComFloating
 234         .init(cpu->numThreads)
 235         .name(name() + ".COM:fp_insts")
 236         .desc("Number of committed floating point instructions.")
 237         .flags(total)
 238         ;
 239
 240     statComInteger
 241         .init(cpu->numThreads)
 242         .name(name()+".COM:int_insts")
 243         .desc("Number of committed integer instructions.")
 244         .flags(total)
 245         ;
 246
 247     statComFunctionCalls
 248         .init(cpu->numThreads)
 249         .name(name()+".COM:function_calls")
 250         .desc("Number of function calls committed.")
 251         .flags(total)
 252         ;
 253
 254     commitEligible
 255         .init(cpu->numThreads)
 256         .name(name() + ".COM:bw_limited")
 257         .desc("number of insts not committed due to BW limits")
 258         .flags(total)
 259         ;
 260
 261     commitEligibleSamples
 262         .name(name() + ".COM:bw_lim_events")
 263         .desc("number cycles where commit BW limit reached")
 264         ;
 265 }
 266
 267 template <class Impl>
 268 void
 269 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 270 {
 271     thread = threads;
 272 }
 273
 274 template <class Impl>
 275 void
 276 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 277 {
 278     timeBuffer = tb_ptr;
 279
 280     // Setup wire to send information back to IEW.
 281     toIEW = timeBuffer->getWire(0);
 282
 283     // Setup wire to read data from IEW (for the ROB).
 284     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 285 }
 286
 287 template <class Impl>
 288 void
 289 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 290 {
 291     fetchQueue = fq_ptr;
 292
 293     // Setup wire to get instructions from rename (for the ROB).
 294     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 295 }
 296
 297 template <class Impl>
 298 void
 299 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 300 {
 301     renameQueue = rq_ptr;
 302
 303     // Setup wire to get instructions from rename (for the ROB).
 304     fromRename = renameQueue->getWire(-renameToROBDelay);
 305 }
 306
 307 template <class Impl>
 308 void
 309 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 310 {
 311     iewQueue = iq_ptr;
 312
 313     // Setup wire to get instructions from IEW.
 314     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 315 }
 316
 317 template <class Impl>
 318 void
 319 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 320 {
 321     iewStage = iew_stage;
 322 }
 323
 324 template<class Impl>
 325 void
 326 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 327 {
 328     activeThreads = at_ptr;
 329 }
 330
 331 template <class Impl>
 332 void
 333 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 334 {
 335     for (ThreadID tid = 0; tid < numThreads; tid++)
 336         renameMap[tid] = &rm_ptr[tid];
 337 }
 338
 339 template <class Impl>
 340 void
 341 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 342 {
 343     rob = rob_ptr;
 344 }
 345
 346 template <class Impl>
 347 void
 348 DefaultCommit<Impl>::initStage()
 349 {
 350     rob->setActiveThreads(activeThreads);
 351     rob->resetEntries();
 352
 353     // Broadcast the number of free entries.
 354     for (ThreadID tid = 0; tid < numThreads; tid++) {
 355         toIEW->commitInfo[tid].usedROB = true;
 356         toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 357         toIEW->commitInfo[tid].emptyROB = true;
 358     }
 359
 360     // Commit must broadcast the number of free entries it has at the
 361     // start of the simulation, so it starts as active.
 362     cpu->activateStage(O3CPU::CommitIdx);
 363
 364     cpu->activityThisCycle();
 365     trapLatency = cpu->ticks(trapLatency);
 366 }
 367
 368 template <class Impl>
 369 bool
 370 DefaultCommit<Impl>::drain()
 371 {
 372     drainPending = true;
 373
 374     return false;
 375 }
 376
 377 template <class Impl>
 378 void
 379 DefaultCommit<Impl>::switchOut()
 380 {
 381     switchedOut = true;
 382     drainPending = false;
 383     rob->switchOut();
 384 }
 385
 386 template <class Impl>
 387 void
 388 DefaultCommit<Impl>::resume()
 389 {
 390     drainPending = false;
 391 }
 392
 393 template <class Impl>
 394 void
 395 DefaultCommit<Impl>::takeOverFrom()
 396 {
 397     switchedOut = false;
 398     _status = Active;
 399     _nextStatus = Inactive;
 400     for (ThreadID tid = 0; tid < numThreads; tid++) {
 401         commitStatus[tid] = Idle;
 402         changedROBNumEntries[tid] = false;
 403         trapSquash[tid] = false;
 404         tcSquash[tid] = false;
 405     }
 406     squashCounter = 0;
 407     rob->takeOverFrom();
 408 }
 409
 410 template <class Impl>
 411 void
 412 DefaultCommit<Impl>::updateStatus()
 413 {
 414     // reset ROB changed variable
 415     list<ThreadID>::iterator threads = activeThreads->begin();
 416     list<ThreadID>::iterator end = activeThreads->end();
 417
 418     while (threads != end) {
 419         ThreadID tid = *threads++;
 420
 421         changedROBNumEntries[tid] = false;
 422
 423         // Also check if any of the threads has a trap pending
 424         if (commitStatus[tid] == TrapPending ||
 425             commitStatus[tid] == FetchTrapPending) {
 426             _nextStatus = Active;
 427         }
 428     }
 429
 430     if (_nextStatus == Inactive && _status == Active) {
 431         DPRINTF(Activity, "Deactivating stage.\n");
 432         cpu->deactivateStage(O3CPU::CommitIdx);
 433     } else if (_nextStatus == Active && _status == Inactive) {
 434         DPRINTF(Activity, "Activating stage.\n");
 435         cpu->activateStage(O3CPU::CommitIdx);
 436     }
 437
 438     _status = _nextStatus;
 439 }
 440
 441 template <class Impl>
 442 void
 443 DefaultCommit<Impl>::setNextStatus()
 444 {
 445     int squashes = 0;
 446
 447     list<ThreadID>::iterator threads = activeThreads->begin();
 448     list<ThreadID>::iterator end = activeThreads->end();
 449
 450     while (threads != end) {
 451         ThreadID tid = *threads++;
 452
 453         if (commitStatus[tid] == ROBSquashing) {
 454             squashes++;
 455         }
 456     }
 457
 458     squashCounter = squashes;
 459
 460     // If commit is currently squashing, then it will have activity for the
 461     // next cycle. Set its next status as active.
 462     if (squashCounter) {
 463         _nextStatus = Active;
 464     }
 465 }
 466
 467 template <class Impl>
 468 bool
 469 DefaultCommit<Impl>::changedROBEntries()
 470 {
 471     list<ThreadID>::iterator threads = activeThreads->begin();
 472     list<ThreadID>::iterator end = activeThreads->end();
 473
 474     while (threads != end) {
 475         ThreadID tid = *threads++;
 476
 477         if (changedROBNumEntries[tid]) {
 478             return true;
 479         }
 480     }
 481
 482     return false;
 483 }
 484
 485 template <class Impl>
 486 size_t
 487 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
 488 {
 489     return rob->numFreeEntries(tid);
 490 }
 491
 492 template <class Impl>
 493 void
 494 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
 495 {
 496     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 497
 498     TrapEvent *trap = new TrapEvent(this, tid);
 499
 500     cpu->schedule(trap, curTick() + trapLatency);
 501     trapInFlight[tid] = true;
 502 }
 503
 504 template <class Impl>
 505 void
 506 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
 507 {
 508     assert(!trapInFlight[tid]);
 509     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 510
 511     tcSquash[tid] = true;
 512 }
 513
 514 template <class Impl>
 515 void
 516 DefaultCommit<Impl>::squashAll(ThreadID tid)
 517 {
 518     // If we want to include the squashing instruction in the squash,
 519     // then use one older sequence number.
 520     // Hopefully this doesn't mess things up.  Basically I want to squash
 521     // all instructions of this thread.
 522     InstSeqNum squashed_inst = rob->isEmpty() ?
 523         lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
 524
 525     // All younger instructions will be squashed. Set the sequence
 526     // number as the youngest instruction in the ROB (0 in this case.
 527     // Hopefully nothing breaks.)
 528     youngestSeqNum[tid] = lastCommitedSeqNum[tid];
 529
 530     rob->squash(squashed_inst, tid);
 531     changedROBNumEntries[tid] = true;
 532
 533     // Send back the sequence number of the squashed instruction.
 534     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 535
 536     // Send back the squash signal to tell stages that they should
 537     // squash.
 538     toIEW->commitInfo[tid].squash = true;
 539
 540     // Send back the rob squashing signal so other stages know that
 541     // the ROB is in the process of squashing.
 542     toIEW->commitInfo[tid].robSquashing = true;
 543
 544     toIEW->commitInfo[tid].branchMispredict = false;
 545     toIEW->commitInfo[tid].mispredictInst = NULL;
 546
 547     toIEW->commitInfo[tid].pc = pc[tid];
 548 }
 549
 550 template <class Impl>
 551 void
 552 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
 553 {
 554     squashAll(tid);
 555
 556     DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
 557
 558     thread[tid]->trapPending = false;
 559     thread[tid]->inSyscall = false;
 560     trapInFlight[tid] = false;
 561
 562     trapSquash[tid] = false;
 563
 564     commitStatus[tid] = ROBSquashing;
 565     cpu->activityThisCycle();
 566 }
 567
 568 template <class Impl>
 569 void
 570 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
 571 {
 572     squashAll(tid);
 573
 574     DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
 575
 576     thread[tid]->inSyscall = false;
 577     assert(!thread[tid]->trapPending);
 578
 579     commitStatus[tid] = ROBSquashing;
 580     cpu->activityThisCycle();
 581
 582     tcSquash[tid] = false;
 583 }
 584
 585 template <class Impl>
 586 void
 587 DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
 588 {
 589     youngestSeqNum[tid] = squash_after_seq_num;
 590
 591     rob->squash(squash_after_seq_num, tid);
 592     changedROBNumEntries[tid] = true;
 593
 594     // Send back the sequence number of the squashed instruction.
 595     toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
 596
 597     // Send back the squash signal to tell stages that they should squash.
 598     toIEW->commitInfo[tid].squash = true;
 599
 600     // Send back the rob squashing signal so other stages know that
 601     // the ROB is in the process of squashing.
 602     toIEW->commitInfo[tid].robSquashing = true;
 603
 604     toIEW->commitInfo[tid].branchMispredict = false;
 605
 606     toIEW->commitInfo[tid].pc = pc[tid];
 607     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
 608             tid, squash_after_seq_num);
 609     commitStatus[tid] = ROBSquashing;
 610 }
 611
 612 template <class Impl>
 613 void
 614 DefaultCommit<Impl>::tick()
 615 {
 616     wroteToTimeBuffer = false;
 617     _nextStatus = Inactive;
 618
 619     if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 620         cpu->signalDrained();
 621         drainPending = false;
 622         return;
 623     }
 624
 625     if (activeThreads->empty())
 626         return;
 627
 628     list<ThreadID>::iterator threads = activeThreads->begin();
 629     list<ThreadID>::iterator end = activeThreads->end();
 630
 631     // Check if any of the threads are done squashing.  Change the
 632     // status if they are done.
 633     while (threads != end) {
 634         ThreadID tid = *threads++;
 635
 636         // Clear the bit saying if the thread has committed stores
 637         // this cycle.
 638         committedStores[tid] = false;
 639
 640         if (commitStatus[tid] == ROBSquashing) {
 641
 642             if (rob->isDoneSquashing(tid)) {
 643                 commitStatus[tid] = Running;
 644             } else {
 645                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 646                         " insts this cycle.\n", tid);
 647                 rob->doSquash(tid);
 648                 toIEW->commitInfo[tid].robSquashing = true;
 649                 wroteToTimeBuffer = true;
 650             }
 651         }
 652     }
 653
 654     commit();
 655
 656     markCompletedInsts();
 657
 658     threads = activeThreads->begin();
 659
 660     while (threads != end) {
 661         ThreadID tid = *threads++;
 662
 663         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 664             // The ROB has more instructions it can commit. Its next status
 665             // will be active.
 666             _nextStatus = Active;
 667
 668             DynInstPtr inst = rob->readHeadInst(tid);
 669
 670             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
 671                     " ROB and ready to commit\n",
 672                     tid, inst->seqNum, inst->pcState());
 673
 674         } else if (!rob->isEmpty(tid)) {
 675             DynInstPtr inst = rob->readHeadInst(tid);
 676
 677             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 678                     "%s is head of ROB and not ready\n",
 679                     tid, inst->seqNum, inst->pcState());
 680         }
 681
 682         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 683                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 684     }
 685
 686
 687     if (wroteToTimeBuffer) {
 688         DPRINTF(Activity, "Activity This Cycle.\n");
 689         cpu->activityThisCycle();
 690     }
 691
 692     updateStatus();
 693 }
 694
 695 #if FULL_SYSTEM
 696 template <class Impl>
 697 void
 698 DefaultCommit<Impl>::handleInterrupt()
 699 {
 700     // Verify that we still have an interrupt to handle
 701     if (!cpu->checkInterrupts(cpu->tcBase(0))) {
 702         DPRINTF(Commit, "Pending interrupt is cleared by master before "
 703                 "it got handled. Restart fetching from the orig path.\n");
 704         toIEW->commitInfo[0].clearInterrupt = true;
 705         interrupt = NoFault;
 706         return;
 707     }
 708
 709     // Wait until the ROB is empty and all stores have drained in
 710     // order to enter the interrupt.
 711     if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
 712         // Squash or record that I need to squash this cycle if
 713         // an interrupt needed to be handled.
 714         DPRINTF(Commit, "Interrupt detected.\n");
 715
 716         // Clear the interrupt now that it's going to be handled
 717         toIEW->commitInfo[0].clearInterrupt = true;
 718
 719         assert(!thread[0]->inSyscall);
 720         thread[0]->inSyscall = true;
 721
 722         // CPU will handle interrupt.
 723         cpu->processInterrupts(interrupt);
 724
 725         thread[0]->inSyscall = false;
 726
 727         commitStatus[0] = TrapPending;
 728
 729         // Generate trap squash event.
 730         generateTrapEvent(0);
 731
 732         interrupt = NoFault;
 733     } else {
 734         DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 735     }
 736 }
 737
 738 template <class Impl>
 739 void
 740 DefaultCommit<Impl>::propagateInterrupt()
 741 {
 742     if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
 743             tcSquash[0])
 744         return;
 745
 746     // Process interrupts if interrupts are enabled, not in PAL
 747     // mode, and no other traps or external squashes are currently
 748     // pending.
 749     // @todo: Allow other threads to handle interrupts.
 750
 751     // Get any interrupt that happened
 752     interrupt = cpu->getInterrupts();
 753
 754     // Tell fetch that there is an interrupt pending.  This
 755     // will make fetch wait until it sees a non PAL-mode PC,
 756     // at which point it stops fetching instructions.
 757     if (interrupt != NoFault)
 758         toIEW->commitInfo[0].interruptPending = true;
 759 }
 760
 761 #endif // FULL_SYSTEM
 762
 763 template <class Impl>
 764 void
 765 DefaultCommit<Impl>::commit()
 766 {
 767
 768 #if FULL_SYSTEM
 769     // Check for any interrupt that we've already squashed for and start processing it.
 770     if (interrupt != NoFault)
 771         handleInterrupt();
 772
 773     // Check if we have a interrupt and get read to handle it
 774     if (cpu->checkInterrupts(cpu->tcBase(0)))
 775         propagateInterrupt();
 776 #endif // FULL_SYSTEM
 777
 778     ////////////////////////////////////
 779     // Check for any possible squashes, handle them first
 780     ////////////////////////////////////
 781     list<ThreadID>::iterator threads = activeThreads->begin();
 782     list<ThreadID>::iterator end = activeThreads->end();
 783
 784     while (threads != end) {
 785         ThreadID tid = *threads++;
 786
 787         // Not sure which one takes priority.  I think if we have
 788         // both, that's a bad sign.
 789         if (trapSquash[tid] == true) {
 790             assert(!tcSquash[tid]);
 791             squashFromTrap(tid);
 792         } else if (tcSquash[tid] == true) {
 793             assert(commitStatus[tid] != TrapPending);
 794             squashFromTC(tid);
 795         }
 796
 797         // Squashed sequence number must be older than youngest valid
 798         // instruction in the ROB. This prevents squashes from younger
 799         // instructions overriding squashes from older instructions.
 800         if (fromIEW->squash[tid] &&
 801             commitStatus[tid] != TrapPending &&
 802             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 803
 804             DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
 805                     tid,
 806                     fromIEW->mispredPC[tid],
 807                     fromIEW->squashedSeqNum[tid]);
 808
 809             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 810                     tid,
 811                     fromIEW->pc[tid].nextInstAddr());
 812
 813             commitStatus[tid] = ROBSquashing;
 814
 815             // If we want to include the squashing instruction in the squash,
 816             // then use one older sequence number.
 817             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 818
 819             if (fromIEW->includeSquashInst[tid] == true) {
 820                 squashed_inst--;
 821             }
 822
 823             // All younger instructions will be squashed. Set the sequence
 824             // number as the youngest instruction in the ROB.
 825             youngestSeqNum[tid] = squashed_inst;
 826
 827             rob->squash(squashed_inst, tid);
 828             changedROBNumEntries[tid] = true;
 829
 830             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 831
 832             toIEW->commitInfo[tid].squash = true;
 833
 834             // Send back the rob squashing signal so other stages know that
 835             // the ROB is in the process of squashing.
 836             toIEW->commitInfo[tid].robSquashing = true;
 837
 838             toIEW->commitInfo[tid].branchMispredict =
 839                 fromIEW->branchMispredict[tid];
 840             toIEW->commitInfo[tid].mispredictInst =
 841                 fromIEW->mispredictInst[tid];
 842             toIEW->commitInfo[tid].branchTaken =
 843                 fromIEW->branchTaken[tid];
 844
 845             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 846
 847             toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
 848
 849             if (toIEW->commitInfo[tid].branchMispredict) {
 850                 ++branchMispredicts;
 851             }
 852         }
 853
 854     }
 855
 856     setNextStatus();
 857
 858     if (squashCounter != numThreads) {
 859         // If we're not currently squashing, then get instructions.
 860         getInsts();
 861
 862         // Try to commit any instructions.
 863         commitInsts();
 864     }
 865
 866     //Check for any activity
 867     threads = activeThreads->begin();
 868
 869     while (threads != end) {
 870         ThreadID tid = *threads++;
 871
 872         if (changedROBNumEntries[tid]) {
 873             toIEW->commitInfo[tid].usedROB = true;
 874             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 875
 876             wroteToTimeBuffer = true;
 877             changedROBNumEntries[tid] = false;
 878             if (rob->isEmpty(tid))
 879                 checkEmptyROB[tid] = true;
 880         }
 881
 882         // ROB is only considered "empty" for previous stages if: a)
 883         // ROB is empty, b) there are no outstanding stores, c) IEW
 884         // stage has received any information regarding stores that
 885         // committed.
 886         // c) is checked by making sure to not consider the ROB empty
 887         // on the same cycle as when stores have been committed.
 888         // @todo: Make this handle multi-cycle communication between
 889         // commit and IEW.
 890         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
 891             !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
 892             checkEmptyROB[tid] = false;
 893             toIEW->commitInfo[tid].usedROB = true;
 894             toIEW->commitInfo[tid].emptyROB = true;
 895             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 896             wroteToTimeBuffer = true;
 897         }
 898
 899     }
 900 }
 901
 902 template <class Impl>
 903 void
 904 DefaultCommit<Impl>::commitInsts()
 905 {
 906     ////////////////////////////////////
 907     // Handle commit
 908     // Note that commit will be handled prior to putting new
 909     // instructions in the ROB so that the ROB only tries to commit
 910     // instructions it has in this current cycle, and not instructions
 911     // it is writing in during this cycle.  Can't commit and squash
 912     // things at the same time...
 913     ////////////////////////////////////
 914
 915     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 916
 917     unsigned num_committed = 0;
 918
 919     DynInstPtr head_inst;
 920
 921     // Commit as many instructions as possible until the commit bandwidth
 922     // limit is reached, or it becomes impossible to commit any more.
 923     while (num_committed < commitWidth) {
 924         int commit_thread = getCommittingThread();
 925
 926         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 927             break;
 928
 929         head_inst = rob->readHeadInst(commit_thread);
 930
 931         ThreadID tid = head_inst->threadNumber;
 932
 933         assert(tid == commit_thread);
 934
 935         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 936                 head_inst->seqNum, tid);
 937
 938         // If the head instruction is squashed, it is ready to retire
 939         // (be removed from the ROB) at any time.
 940         if (head_inst->isSquashed()) {
 941
 942             DPRINTF(Commit, "Retiring squashed instruction from "
 943                     "ROB.\n");
 944
 945             rob->retireHead(commit_thread);
 946
 947             ++commitSquashedInsts;
 948
 949             // Record that the number of ROB entries has changed.
 950             changedROBNumEntries[tid] = true;
 951         } else {
 952             pc[tid] = head_inst->pcState();
 953
 954             // Increment the total number of non-speculative instructions
 955             // executed.
 956             // Hack for now: it really shouldn't happen until after the
 957             // commit is deemed to be successful, but this count is needed
 958             // for syscalls.
 959             thread[tid]->funcExeInst++;
 960
 961             // Try to commit the head instruction.
 962             bool commit_success = commitHead(head_inst, num_committed);
 963
 964             if (commit_success) {
 965                 ++num_committed;
 966
 967                 changedROBNumEntries[tid] = true;
 968
 969                 // Set the doneSeqNum to the youngest committed instruction.
 970                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 971
 972                 ++commitCommittedInsts;
 973
 974                 // To match the old model, don't count nops and instruction
 975                 // prefetches towards the total commit count.
 976                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 977                     cpu->instDone(tid);
 978                 }
 979
 980                 // Updates misc. registers.
 981                 head_inst->updateMiscRegs();
 982
 983                 TheISA::advancePC(pc[tid], head_inst->staticInst);
 984
 985                 // Keep track of the last sequence number commited
 986                 lastCommitedSeqNum[tid] = head_inst->seqNum;
 987
 988                 // If this is an instruction that doesn't play nicely with
 989                 // others squash everything and restart fetch
 990                 if (head_inst->isSquashAfter())
 991                     squashAfter(tid, head_inst->seqNum);
 992
 993                 int count = 0;
 994                 Addr oldpc;
 995                 // Debug statement.  Checks to make sure we're not
 996                 // currently updating state while handling PC events.
 997                 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
 998                 do {
 999                     oldpc = pc[tid].instAddr();
1000                     cpu->system->pcEventQueue.service(thread[tid]->getTC());
1001                     count++;
1002                 } while (oldpc != pc[tid].instAddr());
1003                 if (count > 1) {
1004                     DPRINTF(Commit,
1005                             "PC skip function event, stopping commit\n");
1006                     break;
1007                 }
1008             } else {
1009                 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1010                         "[tid:%i] [sn:%i].\n",
1011                         head_inst->pcState(), tid ,head_inst->seqNum);
1012                 break;
1013             }
1014         }
1015     }
1016
1017     DPRINTF(CommitRate, "%i\n", num_committed);
1018     numCommittedDist.sample(num_committed);
1019
1020     if (num_committed == commitWidth) {
1021         commitEligibleSamples++;
1022     }
1023 }
1024
1025 template <class Impl>
1026 bool
1027 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1028 {
1029     assert(head_inst);
1030
1031     ThreadID tid = head_inst->threadNumber;
1032
1033     // If the instruction is not executed yet, then it will need extra
1034     // handling.  Signal backwards that it should be executed.
1035     if (!head_inst->isExecuted()) {
1036         // Keep this number correct.  We have not yet actually executed
1037         // and committed this instruction.
1038         thread[tid]->funcExeInst--;
1039
1040         if (head_inst->isNonSpeculative() ||
1041             head_inst->isStoreConditional() ||
1042             head_inst->isMemBarrier() ||
1043             head_inst->isWriteBarrier()) {
1044
1045             DPRINTF(Commit, "Encountered a barrier or non-speculative "
1046                     "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1047                     head_inst->seqNum, head_inst->pcState());
1048
1049             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1050                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1051                 return false;
1052             }
1053
1054             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1055
1056             // Change the instruction so it won't try to commit again until
1057             // it is executed.
1058             head_inst->clearCanCommit();
1059
1060             ++commitNonSpecStalls;
1061
1062             return false;
1063         } else if (head_inst->isLoad()) {
1064             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1065                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1066                 return false;
1067             }
1068
1069             assert(head_inst->uncacheable());
1070             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1071                     head_inst->seqNum, head_inst->pcState());
1072
1073             // Send back the non-speculative instruction's sequence
1074             // number.  Tell the lsq to re-execute the load.
1075             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1076             toIEW->commitInfo[tid].uncached = true;
1077             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1078
1079             head_inst->clearCanCommit();
1080
1081             return false;
1082         } else {
1083             panic("Trying to commit un-executed instruction "
1084                   "of unknown type!\n");
1085         }
1086     }
1087
1088     if (head_inst->isThreadSync()) {
1089         // Not handled for now.
1090         panic("Thread sync instructions are not handled yet.\n");
1091     }
1092
1093     // Check if the instruction caused a fault.  If so, trap.
1094     Fault inst_fault = head_inst->getFault();
1095
1096     // Stores mark themselves as completed.
1097     if (!head_inst->isStore() && inst_fault == NoFault) {
1098         head_inst->setCompleted();
1099     }
1100
1101 #if USE_CHECKER
1102     // Use checker prior to updating anything due to traps or PC
1103     // based events.
1104     if (cpu->checker) {
1105         cpu->checker->verify(head_inst);
1106     }
1107 #endif
1108
1109     if (inst_fault != NoFault) {
1110         DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1111                 head_inst->seqNum, head_inst->pcState());
1112
1113         if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1114             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1115             return false;
1116         }
1117
1118         head_inst->setCompleted();
1119
1120 #if USE_CHECKER
1121         if (cpu->checker && head_inst->isStore()) {
1122             cpu->checker->verify(head_inst);
1123         }
1124 #endif
1125
1126         assert(!thread[tid]->inSyscall);
1127
1128         // Mark that we're in state update mode so that the trap's
1129         // execution doesn't generate extra squashes.
1130         thread[tid]->inSyscall = true;
1131
1132         // Execute the trap.  Although it's slightly unrealistic in
1133         // terms of timing (as it doesn't wait for the full timing of
1134         // the trap event to complete before updating state), it's
1135         // needed to update the state as soon as possible.  This
1136         // prevents external agents from changing any specific state
1137         // that the trap need.
1138         cpu->trap(inst_fault, tid, head_inst->staticInst);
1139
1140         // Exit state update mode to avoid accidental updating.
1141         thread[tid]->inSyscall = false;
1142
1143         commitStatus[tid] = TrapPending;
1144
1145         DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1146             head_inst->seqNum);
1147         if (head_inst->traceData) {
1148             if (DTRACE(ExecFaulting)) {
1149                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1150                 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1151                 head_inst->traceData->dump();
1152             }
1153             delete head_inst->traceData;
1154             head_inst->traceData = NULL;
1155         }
1156
1157         // Generate trap squash event.
1158         generateTrapEvent(tid);
1159         return false;
1160     }
1161
1162     updateComInstStats(head_inst);
1163
1164 #if FULL_SYSTEM
1165     if (thread[tid]->profile) {
1166         thread[tid]->profilePC = head_inst->instAddr();
1167         ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1168                                                           head_inst->staticInst);
1169
1170         if (node)
1171             thread[tid]->profileNode = node;
1172     }
1173     if (CPA::available()) {
1174         if (head_inst->isControl()) {
1175             ThreadContext *tc = thread[tid]->getTC();
1176             CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1177         }
1178     }
1179 #endif
1180
1181     if (head_inst->traceData) {
1182         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1183         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1184         head_inst->traceData->dump();
1185         delete head_inst->traceData;
1186         head_inst->traceData = NULL;
1187     }
1188
1189     // Update the commit rename map
1190     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1191         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1192                                  head_inst->renamedDestRegIdx(i));
1193     }
1194
1195     if (head_inst->isCopy())
1196         panic("Should not commit any copy instructions!");
1197
1198     // Finally clear the head ROB entry.
1199     rob->retireHead(tid);
1200
1201     // If this was a store, record it for this cycle.
1202     if (head_inst->isStore())
1203         committedStores[tid] = true;
1204
1205     // Return true to indicate that we have committed an instruction.
1206     return true;
1207 }
1208
1209 template <class Impl>
1210 void
1211 DefaultCommit<Impl>::getInsts()
1212 {
1213     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1214
1215     // Read any renamed instructions and place them into the ROB.
1216     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1217
1218     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1219         DynInstPtr inst;
1220
1221         inst = fromRename->insts[inst_num];
1222         ThreadID tid = inst->threadNumber;
1223
1224         if (!inst->isSquashed() &&
1225             commitStatus[tid] != ROBSquashing &&
1226             commitStatus[tid] != TrapPending) {
1227             changedROBNumEntries[tid] = true;
1228
1229             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1230                     inst->pcState(), inst->seqNum, tid);
1231
1232             rob->insertInst(inst);
1233
1234             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1235
1236             youngestSeqNum[tid] = inst->seqNum;
1237         } else {
1238             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1239                     "squashed, skipping.\n",
1240                     inst->pcState(), inst->seqNum, tid);
1241         }
1242     }
1243 }
1244
1245 template <class Impl>
1246 void
1247 DefaultCommit<Impl>::skidInsert()
1248 {
1249     DPRINTF(Commit, "Attempting to any instructions from rename into "
1250             "skidBuffer.\n");
1251
1252     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1253         DynInstPtr inst = fromRename->insts[inst_num];
1254
1255         if (!inst->isSquashed()) {
1256             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1257                     "skidBuffer.\n", inst->pcState(), inst->seqNum,
1258                     inst->threadNumber);
1259             skidBuffer.push(inst);
1260         } else {
1261             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1262                     "squashed, skipping.\n",
1263                     inst->pcState(), inst->seqNum, inst->threadNumber);
1264         }
1265     }
1266 }
1267
1268 template <class Impl>
1269 void
1270 DefaultCommit<Impl>::markCompletedInsts()
1271 {
1272     // Grab completed insts out of the IEW instruction queue, and mark
1273     // instructions completed within the ROB.
1274     for (int inst_num = 0;
1275          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1276          ++inst_num)
1277     {
1278         if (!fromIEW->insts[inst_num]->isSquashed()) {
1279             DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1280                     "within ROB.\n",
1281                     fromIEW->insts[inst_num]->threadNumber,
1282                     fromIEW->insts[inst_num]->pcState(),
1283                     fromIEW->insts[inst_num]->seqNum);
1284
1285             // Mark the instruction as ready to commit.
1286             fromIEW->insts[inst_num]->setCanCommit();
1287         }
1288     }
1289 }
1290
1291 template <class Impl>
1292 bool
1293 DefaultCommit<Impl>::robDoneSquashing()
1294 {
1295     list<ThreadID>::iterator threads = activeThreads->begin();
1296     list<ThreadID>::iterator end = activeThreads->end();
1297
1298     while (threads != end) {
1299         ThreadID tid = *threads++;
1300
1301         if (!rob->isDoneSquashing(tid))
1302             return false;
1303     }
1304
1305     return true;
1306 }
1307
1308 template <class Impl>
1309 void
1310 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1311 {
1312     ThreadID tid = inst->threadNumber;
1313
1314     //
1315     //  Pick off the software prefetches
1316     //
1317 #ifdef TARGET_ALPHA
1318     if (inst->isDataPrefetch()) {
1319         statComSwp[tid]++;
1320     } else {
1321         statComInst[tid]++;
1322     }
1323 #else
1324     statComInst[tid]++;
1325 #endif
1326
1327     //
1328     //  Control Instructions
1329     //
1330     if (inst->isControl())
1331         statComBranches[tid]++;
1332
1333     //
1334     //  Memory references
1335     //
1336     if (inst->isMemRef()) {
1337         statComRefs[tid]++;
1338
1339         if (inst->isLoad()) {
1340             statComLoads[tid]++;
1341         }
1342     }
1343
1344     if (inst->isMemBarrier()) {
1345         statComMembars[tid]++;
1346     }
1347
1348     // Integer Instruction
1349     if (inst->isInteger())
1350         statComInteger[tid]++;
1351
1352     // Floating Point Instruction
1353     if (inst->isFloating())
1354         statComFloating[tid]++;
1355
1356     // Function Calls
1357     if (inst->isCall())
1358         statComFunctionCalls[tid]++;
1359
1360 }
1361
1362 ////////////////////////////////////////
1363 //                                    //
1364 //  SMT COMMIT POLICY MAINTAINED HERE //
1365 //                                    //
1366 ////////////////////////////////////////
1367 template <class Impl>
1368 ThreadID
1369 DefaultCommit<Impl>::getCommittingThread()
1370 {
1371     if (numThreads > 1) {
1372         switch (commitPolicy) {
1373
1374           case Aggressive:
1375             //If Policy is Aggressive, commit will call
1376             //this function multiple times per
1377             //cycle
1378             return oldestReady();
1379
1380           case RoundRobin:
1381             return roundRobin();
1382
1383           case OldestReady:
1384             return oldestReady();
1385
1386           default:
1387             return InvalidThreadID;
1388         }
1389     } else {
1390         assert(!activeThreads->empty());
1391         ThreadID tid = activeThreads->front();
1392
1393         if (commitStatus[tid] == Running ||
1394             commitStatus[tid] == Idle ||
1395             commitStatus[tid] == FetchTrapPending) {
1396             return tid;
1397         } else {
1398             return InvalidThreadID;
1399         }
1400     }
1401 }
1402
1403 template<class Impl>
1404 ThreadID
1405 DefaultCommit<Impl>::roundRobin()
1406 {
1407     list<ThreadID>::iterator pri_iter = priority_list.begin();
1408     list<ThreadID>::iterator end      = priority_list.end();
1409
1410     while (pri_iter != end) {
1411         ThreadID tid = *pri_iter;
1412
1413         if (commitStatus[tid] == Running ||
1414             commitStatus[tid] == Idle ||
1415             commitStatus[tid] == FetchTrapPending) {
1416
1417             if (rob->isHeadReady(tid)) {
1418                 priority_list.erase(pri_iter);
1419                 priority_list.push_back(tid);
1420
1421                 return tid;
1422             }
1423         }
1424
1425         pri_iter++;
1426     }
1427
1428     return InvalidThreadID;
1429 }
1430
1431 template<class Impl>
1432 ThreadID
1433 DefaultCommit<Impl>::oldestReady()
1434 {
1435     unsigned oldest = 0;
1436     bool first = true;
1437
1438     list<ThreadID>::iterator threads = activeThreads->begin();
1439     list<ThreadID>::iterator end = activeThreads->end();
1440
1441     while (threads != end) {
1442         ThreadID tid = *threads++;
1443
1444         if (!rob->isEmpty(tid) &&
1445             (commitStatus[tid] == Running ||
1446              commitStatus[tid] == Idle ||
1447              commitStatus[tid] == FetchTrapPending)) {
1448
1449             if (rob->isHeadReady(tid)) {
1450
1451                 DynInstPtr head_inst = rob->readHeadInst(tid);
1452
1453                 if (first) {
1454                     oldest = tid;
1455                     first = false;
1456                 } else if (head_inst->seqNum < oldest) {
1457                     oldest = tid;
1458                 }
1459             }
1460         }
1461     }
1462
1463     if (!first) {
1464         return oldest;
1465     } else {
1466         return InvalidThreadID;
1467     }
1468 }