2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
38 #include "arch/utility.hh"
39 #include "base/loader/symtab.hh"
40 #include "base/timebuf.hh"
41 #include "cpu/exetrace.hh"
42 #include "cpu/o3/commit.hh"
43 #include "cpu/o3/thread_state.hh"
46 #include "cpu/checker/cpu.hh"
50 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
54 this->setFlags(Event::AutoDelete);
59 DefaultCommit<Impl>::TrapEvent::process()
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
68 DefaultCommit<Impl>::TrapEvent::description()
74 DefaultCommit<Impl>::DefaultCommit(Params *params)
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
85 trapLatency(params->trapLatency)
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
130 template <class Impl>
132 DefaultCommit<Impl>::name() const
134 return cpu->name() + ".commit";
137 template <class Impl>
139 DefaultCommit<Impl>::regStats()
141 using namespace Stats;
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
225 template <class Impl>
227 DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
236 trapLatency = cpu->cycles(trapLatency);
239 template <class Impl>
241 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
246 template <class Impl>
248 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
260 template <class Impl>
262 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
271 template <class Impl>
273 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
282 template <class Impl>
284 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
293 template <class Impl>
295 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
297 iewStage = iew_stage;
302 DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
308 template <class Impl>
310 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
312 DPRINTF(Commit, "Setting rename map pointers.\n");
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
319 template <class Impl>
321 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
327 template <class Impl>
329 DefaultCommit<Impl>::initStage()
331 rob->setActiveThreads(activeThreads);
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
340 cpu->activityThisCycle();
343 template <class Impl>
345 DefaultCommit<Impl>::drain()
352 template <class Impl>
354 DefaultCommit<Impl>::switchOut()
357 drainPending = false;
361 template <class Impl>
363 DefaultCommit<Impl>::resume()
365 drainPending = false;
368 template <class Impl>
370 DefaultCommit<Impl>::takeOverFrom()
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
385 template <class Impl>
387 DefaultCommit<Impl>::updateStatus()
389 // reset ROB changed variable
390 std::list<unsigned>::iterator threads = activeThreads->begin();
391 std::list<unsigned>::iterator end = activeThreads->end();
393 while (threads != end) {
394 unsigned tid = *threads++;
396 changedROBNumEntries[tid] = false;
398 // Also check if any of the threads has a trap pending
399 if (commitStatus[tid] == TrapPending ||
400 commitStatus[tid] == FetchTrapPending) {
401 _nextStatus = Active;
405 if (_nextStatus == Inactive && _status == Active) {
406 DPRINTF(Activity, "Deactivating stage.\n");
407 cpu->deactivateStage(O3CPU::CommitIdx);
408 } else if (_nextStatus == Active && _status == Inactive) {
409 DPRINTF(Activity, "Activating stage.\n");
410 cpu->activateStage(O3CPU::CommitIdx);
413 _status = _nextStatus;
416 template <class Impl>
418 DefaultCommit<Impl>::setNextStatus()
422 std::list<unsigned>::iterator threads = activeThreads->begin();
423 std::list<unsigned>::iterator end = activeThreads->end();
425 while (threads != end) {
426 unsigned tid = *threads++;
428 if (commitStatus[tid] == ROBSquashing) {
433 squashCounter = squashes;
435 // If commit is currently squashing, then it will have activity for the
436 // next cycle. Set its next status as active.
438 _nextStatus = Active;
442 template <class Impl>
444 DefaultCommit<Impl>::changedROBEntries()
446 std::list<unsigned>::iterator threads = activeThreads->begin();
447 std::list<unsigned>::iterator end = activeThreads->end();
449 while (threads != end) {
450 unsigned tid = *threads++;
452 if (changedROBNumEntries[tid]) {
460 template <class Impl>
462 DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
464 return rob->numFreeEntries(tid);
467 template <class Impl>
469 DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
473 TrapEvent *trap = new TrapEvent(this, tid);
475 trap->schedule(curTick + trapLatency);
477 thread[tid]->trapPending = true;
480 template <class Impl>
482 DefaultCommit<Impl>::generateTCEvent(unsigned tid)
484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
486 tcSquash[tid] = true;
489 template <class Impl>
491 DefaultCommit<Impl>::squashAll(unsigned tid)
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
498 0 : rob->readHeadInst(tid)->seqNum - 1;;
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
511 // Send back the squash signal to tell stages that they should
513 toIEW->commitInfo[tid].squash = true;
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
519 toIEW->commitInfo[tid].branchMispredict = false;
521 toIEW->commitInfo[tid].nextPC = PC[tid];
524 template <class Impl>
526 DefaultCommit<Impl>::squashFromTrap(unsigned tid)
530 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
532 thread[tid]->trapPending = false;
533 thread[tid]->inSyscall = false;
535 trapSquash[tid] = false;
537 commitStatus[tid] = ROBSquashing;
538 cpu->activityThisCycle();
541 template <class Impl>
543 DefaultCommit<Impl>::squashFromTC(unsigned tid)
547 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
549 thread[tid]->inSyscall = false;
550 assert(!thread[tid]->trapPending);
552 commitStatus[tid] = ROBSquashing;
553 cpu->activityThisCycle();
555 tcSquash[tid] = false;
558 template <class Impl>
560 DefaultCommit<Impl>::tick()
562 wroteToTimeBuffer = false;
563 _nextStatus = Inactive;
565 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
566 cpu->signalDrained();
567 drainPending = false;
571 if (activeThreads->empty())
574 std::list<unsigned>::iterator threads = activeThreads->begin();
575 std::list<unsigned>::iterator end = activeThreads->end();
577 // Check if any of the threads are done squashing. Change the
578 // status if they are done.
579 while (threads != end) {
580 unsigned tid = *threads++;
582 if (commitStatus[tid] == ROBSquashing) {
584 if (rob->isDoneSquashing(tid)) {
585 commitStatus[tid] = Running;
587 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
588 " insts this cycle.\n", tid);
590 toIEW->commitInfo[tid].robSquashing = true;
591 wroteToTimeBuffer = true;
598 markCompletedInsts();
600 threads = activeThreads->begin();
602 while (threads != end) {
603 unsigned tid = *threads++;
605 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
606 // The ROB has more instructions it can commit. Its next status
608 _nextStatus = Active;
610 DynInstPtr inst = rob->readHeadInst(tid);
612 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
613 " ROB and ready to commit\n",
614 tid, inst->seqNum, inst->readPC());
616 } else if (!rob->isEmpty(tid)) {
617 DynInstPtr inst = rob->readHeadInst(tid);
619 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
620 "%#x is head of ROB and not ready\n",
621 tid, inst->seqNum, inst->readPC());
624 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
625 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
629 if (wroteToTimeBuffer) {
630 DPRINTF(Activity, "Activity This Cycle.\n");
631 cpu->activityThisCycle();
637 template <class Impl>
639 DefaultCommit<Impl>::commit()
642 //////////////////////////////////////
643 // Check for interrupts
644 //////////////////////////////////////
647 if (interrupt != NoFault) {
648 // Wait until the ROB is empty and all stores have drained in
649 // order to enter the interrupt.
650 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
651 // Squash or record that I need to squash this cycle if
652 // an interrupt needed to be handled.
653 DPRINTF(Commit, "Interrupt detected.\n");
655 assert(!thread[0]->inSyscall);
656 thread[0]->inSyscall = true;
658 // CPU will handle interrupt.
659 cpu->processInterrupts(interrupt);
661 thread[0]->inSyscall = false;
663 commitStatus[0] = TrapPending;
665 // Generate trap squash event.
666 generateTrapEvent(0);
668 // Clear the interrupt now that it's been handled
669 toIEW->commitInfo[0].clearInterrupt = true;
672 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
674 } else if (cpu->checkInterrupts &&
675 cpu->check_interrupts(cpu->tcBase(0)) &&
676 commitStatus[0] != TrapPending &&
679 // Process interrupts if interrupts are enabled, not in PAL
680 // mode, and no other traps or external squashes are currently
682 // @todo: Allow other threads to handle interrupts.
684 // Get any interrupt that happened
685 interrupt = cpu->getInterrupts();
687 if (interrupt != NoFault) {
688 // Tell fetch that there is an interrupt pending. This
689 // will make fetch wait until it sees a non PAL-mode PC,
690 // at which point it stops fetching instructions.
691 toIEW->commitInfo[0].interruptPending = true;
695 #endif // FULL_SYSTEM
697 ////////////////////////////////////
698 // Check for any possible squashes, handle them first
699 ////////////////////////////////////
700 std::list<unsigned>::iterator threads = activeThreads->begin();
701 std::list<unsigned>::iterator end = activeThreads->end();
703 while (threads != end) {
704 unsigned tid = *threads++;
706 // Not sure which one takes priority. I think if we have
707 // both, that's a bad sign.
708 if (trapSquash[tid] == true) {
709 assert(!tcSquash[tid]);
711 } else if (tcSquash[tid] == true) {
715 // Squashed sequence number must be older than youngest valid
716 // instruction in the ROB. This prevents squashes from younger
717 // instructions overriding squashes from older instructions.
718 if (fromIEW->squash[tid] &&
719 commitStatus[tid] != TrapPending &&
720 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
722 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
724 fromIEW->mispredPC[tid],
725 fromIEW->squashedSeqNum[tid]);
727 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
729 fromIEW->nextPC[tid]);
731 commitStatus[tid] = ROBSquashing;
733 // If we want to include the squashing instruction in the squash,
734 // then use one older sequence number.
735 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
737 #if ISA_HAS_DELAY_SLOT
738 InstSeqNum bdelay_done_seq_num;
739 bool squash_bdelay_slot;
741 if (fromIEW->branchMispredict[tid]) {
742 if (fromIEW->branchTaken[tid] &&
743 fromIEW->condDelaySlotBranch[tid]) {
744 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
745 "mispredicted as taken. Squashing after previous "
748 bdelay_done_seq_num = squashed_inst;
749 squash_bdelay_slot = true;
751 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
752 "after delay slot [sn:%i]\n", tid, squashed_inst+1);
753 bdelay_done_seq_num = squashed_inst + 1;
754 squash_bdelay_slot = false;
757 bdelay_done_seq_num = squashed_inst;
758 squash_bdelay_slot = true;
762 if (fromIEW->includeSquashInst[tid] == true) {
764 #if ISA_HAS_DELAY_SLOT
765 bdelay_done_seq_num--;
768 // All younger instructions will be squashed. Set the sequence
769 // number as the youngest instruction in the ROB.
770 youngestSeqNum[tid] = squashed_inst;
772 #if ISA_HAS_DELAY_SLOT
773 rob->squash(bdelay_done_seq_num, tid);
774 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
775 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
777 rob->squash(squashed_inst, tid);
778 toIEW->commitInfo[tid].squashDelaySlot = true;
780 changedROBNumEntries[tid] = true;
782 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
784 toIEW->commitInfo[tid].squash = true;
786 // Send back the rob squashing signal so other stages know that
787 // the ROB is in the process of squashing.
788 toIEW->commitInfo[tid].robSquashing = true;
790 toIEW->commitInfo[tid].branchMispredict =
791 fromIEW->branchMispredict[tid];
793 toIEW->commitInfo[tid].branchTaken =
794 fromIEW->branchTaken[tid];
796 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
798 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
800 if (toIEW->commitInfo[tid].branchMispredict) {
809 if (squashCounter != numThreads) {
810 // If we're not currently squashing, then get instructions.
813 // Try to commit any instructions.
816 #if ISA_HAS_DELAY_SLOT
821 //Check for any activity
822 threads = activeThreads->begin();
824 while (threads != end) {
825 unsigned tid = *threads++;
827 if (changedROBNumEntries[tid]) {
828 toIEW->commitInfo[tid].usedROB = true;
829 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
831 if (rob->isEmpty(tid)) {
832 toIEW->commitInfo[tid].emptyROB = true;
835 wroteToTimeBuffer = true;
836 changedROBNumEntries[tid] = false;
841 template <class Impl>
843 DefaultCommit<Impl>::commitInsts()
845 ////////////////////////////////////
847 // Note that commit will be handled prior to putting new
848 // instructions in the ROB so that the ROB only tries to commit
849 // instructions it has in this current cycle, and not instructions
850 // it is writing in during this cycle. Can't commit and squash
851 // things at the same time...
852 ////////////////////////////////////
854 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
856 unsigned num_committed = 0;
858 DynInstPtr head_inst;
860 // Commit as many instructions as possible until the commit bandwidth
861 // limit is reached, or it becomes impossible to commit any more.
862 while (num_committed < commitWidth) {
863 int commit_thread = getCommittingThread();
865 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
868 head_inst = rob->readHeadInst(commit_thread);
870 int tid = head_inst->threadNumber;
872 assert(tid == commit_thread);
874 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
875 head_inst->seqNum, tid);
877 // If the head instruction is squashed, it is ready to retire
878 // (be removed from the ROB) at any time.
879 if (head_inst->isSquashed()) {
881 DPRINTF(Commit, "Retiring squashed instruction from "
884 rob->retireHead(commit_thread);
886 ++commitSquashedInsts;
888 // Record that the number of ROB entries has changed.
889 changedROBNumEntries[tid] = true;
891 PC[tid] = head_inst->readPC();
892 nextPC[tid] = head_inst->readNextPC();
893 nextNPC[tid] = head_inst->readNextNPC();
895 // Increment the total number of non-speculative instructions
897 // Hack for now: it really shouldn't happen until after the
898 // commit is deemed to be successful, but this count is needed
900 thread[tid]->funcExeInst++;
902 // Try to commit the head instruction.
903 bool commit_success = commitHead(head_inst, num_committed);
905 if (commit_success) {
908 changedROBNumEntries[tid] = true;
910 // Set the doneSeqNum to the youngest committed instruction.
911 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
913 ++commitCommittedInsts;
915 // To match the old model, don't count nops and instruction
916 // prefetches towards the total commit count.
917 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
921 PC[tid] = nextPC[tid];
922 #if ISA_HAS_DELAY_SLOT
923 nextPC[tid] = nextNPC[tid];
924 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
926 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
933 // Debug statement. Checks to make sure we're not
934 // currently updating state while handling PC events.
936 assert(!thread[tid]->inSyscall &&
937 !thread[tid]->trapPending);
939 cpu->system->pcEventQueue.service(
940 thread[tid]->getTC());
942 } while (oldpc != PC[tid]);
944 DPRINTF(Commit, "PC skip function event, stopping commit\n");
949 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
950 "[tid:%i] [sn:%i].\n",
951 head_inst->readPC(), tid ,head_inst->seqNum);
957 DPRINTF(CommitRate, "%i\n", num_committed);
958 numCommittedDist.sample(num_committed);
960 if (num_committed == commitWidth) {
961 commitEligibleSamples++;
965 template <class Impl>
967 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
971 int tid = head_inst->threadNumber;
973 // If the instruction is not executed yet, then it will need extra
974 // handling. Signal backwards that it should be executed.
975 if (!head_inst->isExecuted()) {
976 // Keep this number correct. We have not yet actually executed
977 // and committed this instruction.
978 thread[tid]->funcExeInst--;
980 head_inst->setAtCommit();
982 if (head_inst->isNonSpeculative() ||
983 head_inst->isStoreConditional() ||
984 head_inst->isMemBarrier() ||
985 head_inst->isWriteBarrier()) {
987 DPRINTF(Commit, "Encountered a barrier or non-speculative "
988 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
989 head_inst->seqNum, head_inst->readPC());
991 // Hack to make sure syscalls/memory barriers/quiesces
992 // aren't executed until all stores write back their data.
993 // This direct communication shouldn't be used for
994 // anything other than this.
995 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
996 head_inst->isQuiesce()) &&
997 iewStage->hasStoresToWB())
999 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1001 } else if (inst_num > 0) {
1002 DPRINTF(Commit, "Waiting to become head of commit.\n");
1006 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1008 // Change the instruction so it won't try to commit again until
1010 head_inst->clearCanCommit();
1012 ++commitNonSpecStalls;
1015 } else if (head_inst->isLoad()) {
1016 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1017 head_inst->seqNum, head_inst->readPC());
1019 // Send back the non-speculative instruction's sequence
1020 // number. Tell the lsq to re-execute the load.
1021 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1022 toIEW->commitInfo[tid].uncached = true;
1023 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1025 head_inst->clearCanCommit();
1029 panic("Trying to commit un-executed instruction "
1030 "of unknown type!\n");
1034 if (head_inst->isThreadSync()) {
1035 // Not handled for now.
1036 panic("Thread sync instructions are not handled yet.\n");
1039 // Stores mark themselves as completed.
1040 if (!head_inst->isStore()) {
1041 head_inst->setCompleted();
1045 // Use checker prior to updating anything due to traps or PC
1048 cpu->checker->verify(head_inst);
1052 // Check if the instruction caused a fault. If so, trap.
1053 Fault inst_fault = head_inst->getFault();
1055 // DTB will sometimes need the machine instruction for when
1056 // faults happen. So we will set it here, prior to the DTB
1057 // possibly needing it for its fault.
1058 thread[tid]->setInst(
1059 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1061 if (inst_fault != NoFault) {
1062 head_inst->setCompleted();
1063 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1064 head_inst->seqNum, head_inst->readPC());
1066 if (iewStage->hasStoresToWB() || inst_num > 0) {
1067 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1072 if (cpu->checker && head_inst->isStore()) {
1073 cpu->checker->verify(head_inst);
1077 assert(!thread[tid]->inSyscall);
1079 // Mark that we're in state update mode so that the trap's
1080 // execution doesn't generate extra squashes.
1081 thread[tid]->inSyscall = true;
1083 // Execute the trap. Although it's slightly unrealistic in
1084 // terms of timing (as it doesn't wait for the full timing of
1085 // the trap event to complete before updating state), it's
1086 // needed to update the state as soon as possible. This
1087 // prevents external agents from changing any specific state
1088 // that the trap need.
1089 cpu->trap(inst_fault, tid);
1091 // Exit state update mode to avoid accidental updating.
1092 thread[tid]->inSyscall = false;
1094 commitStatus[tid] = TrapPending;
1096 // Generate trap squash event.
1097 generateTrapEvent(tid);
1098 // warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1102 updateComInstStats(head_inst);
1105 if (thread[tid]->profile) {
1106 // bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1107 // thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1108 thread[tid]->profilePC = head_inst->readPC();
1109 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1110 head_inst->staticInst);
1113 thread[tid]->profileNode = node;
1117 if (head_inst->traceData) {
1118 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1119 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1120 head_inst->traceData->finalize();
1121 head_inst->traceData = NULL;
1124 // Update the commit rename map
1125 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1126 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1127 head_inst->renamedDestRegIdx(i));
1130 if (head_inst->isCopy())
1131 panic("Should not commit any copy instructions!");
1133 // Finally clear the head ROB entry.
1134 rob->retireHead(tid);
1136 // Return true to indicate that we have committed an instruction.
1140 template <class Impl>
1142 DefaultCommit<Impl>::getInsts()
1144 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1146 #if ISA_HAS_DELAY_SLOT
1147 // Read any renamed instructions and place them into the ROB.
1148 int insts_to_process = std::min((int)renameWidth,
1149 (int)(fromRename->size + skidBuffer.size()));
1152 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1153 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1156 // Read any renamed instructions and place them into the ROB.
1157 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1161 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1164 #if ISA_HAS_DELAY_SLOT
1165 // Get insts from skidBuffer or from Rename
1166 if (skidBuffer.size() > 0) {
1167 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1168 inst = skidBuffer.front();
1171 DPRINTF(Commit, "Grabbing rename inst.\n");
1172 inst = fromRename->insts[rename_idx++];
1175 inst = fromRename->insts[inst_num];
1177 int tid = inst->threadNumber;
1179 if (!inst->isSquashed() &&
1180 commitStatus[tid] != ROBSquashing) {
1181 changedROBNumEntries[tid] = true;
1183 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1184 inst->readPC(), inst->seqNum, tid);
1186 rob->insertInst(inst);
1188 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1190 youngestSeqNum[tid] = inst->seqNum;
1192 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1193 "squashed, skipping.\n",
1194 inst->readPC(), inst->seqNum, tid);
1198 #if ISA_HAS_DELAY_SLOT
1199 if (rename_idx < fromRename->size) {
1200 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1203 rename_idx < fromRename->size;
1205 DynInstPtr inst = fromRename->insts[rename_idx];
1207 if (!inst->isSquashed()) {
1208 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1209 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1210 inst->threadNumber);
1211 skidBuffer.push(inst);
1213 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1214 "squashed, skipping.\n",
1215 inst->readPC(), inst->seqNum, inst->threadNumber);
1223 template <class Impl>
1225 DefaultCommit<Impl>::skidInsert()
1227 DPRINTF(Commit, "Attempting to any instructions from rename into "
1230 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1231 DynInstPtr inst = fromRename->insts[inst_num];
1233 if (!inst->isSquashed()) {
1234 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1235 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1236 inst->threadNumber);
1237 skidBuffer.push(inst);
1239 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1240 "squashed, skipping.\n",
1241 inst->readPC(), inst->seqNum, inst->threadNumber);
1246 template <class Impl>
1248 DefaultCommit<Impl>::markCompletedInsts()
1250 // Grab completed insts out of the IEW instruction queue, and mark
1251 // instructions completed within the ROB.
1252 for (int inst_num = 0;
1253 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1256 if (!fromIEW->insts[inst_num]->isSquashed()) {
1257 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1259 fromIEW->insts[inst_num]->threadNumber,
1260 fromIEW->insts[inst_num]->readPC(),
1261 fromIEW->insts[inst_num]->seqNum);
1263 // Mark the instruction as ready to commit.
1264 fromIEW->insts[inst_num]->setCanCommit();
1269 template <class Impl>
1271 DefaultCommit<Impl>::robDoneSquashing()
1273 std::list<unsigned>::iterator threads = activeThreads->begin();
1274 std::list<unsigned>::iterator end = activeThreads->end();
1276 while (threads != end) {
1277 unsigned tid = *threads++;
1279 if (!rob->isDoneSquashing(tid))
1286 template <class Impl>
1288 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1290 unsigned thread = inst->threadNumber;
1293 // Pick off the software prefetches
1296 if (inst->isDataPrefetch()) {
1297 statComSwp[thread]++;
1299 statComInst[thread]++;
1302 statComInst[thread]++;
1306 // Control Instructions
1308 if (inst->isControl())
1309 statComBranches[thread]++;
1312 // Memory references
1314 if (inst->isMemRef()) {
1315 statComRefs[thread]++;
1317 if (inst->isLoad()) {
1318 statComLoads[thread]++;
1322 if (inst->isMemBarrier()) {
1323 statComMembars[thread]++;
1327 ////////////////////////////////////////
1329 // SMT COMMIT POLICY MAINTAINED HERE //
1331 ////////////////////////////////////////
1332 template <class Impl>
1334 DefaultCommit<Impl>::getCommittingThread()
1336 if (numThreads > 1) {
1337 switch (commitPolicy) {
1340 //If Policy is Aggressive, commit will call
1341 //this function multiple times per
1343 return oldestReady();
1346 return roundRobin();
1349 return oldestReady();
1355 assert(!activeThreads->empty());
1356 int tid = activeThreads->front();
1358 if (commitStatus[tid] == Running ||
1359 commitStatus[tid] == Idle ||
1360 commitStatus[tid] == FetchTrapPending) {
1368 template<class Impl>
1370 DefaultCommit<Impl>::roundRobin()
1372 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1373 std::list<unsigned>::iterator end = priority_list.end();
1375 while (pri_iter != end) {
1376 unsigned tid = *pri_iter;
1378 if (commitStatus[tid] == Running ||
1379 commitStatus[tid] == Idle ||
1380 commitStatus[tid] == FetchTrapPending) {
1382 if (rob->isHeadReady(tid)) {
1383 priority_list.erase(pri_iter);
1384 priority_list.push_back(tid);
1396 template<class Impl>
1398 DefaultCommit<Impl>::oldestReady()
1400 unsigned oldest = 0;
1403 std::list<unsigned>::iterator threads = activeThreads->begin();
1404 std::list<unsigned>::iterator end = activeThreads->end();
1406 while (threads != end) {
1407 unsigned tid = *threads++;
1409 if (!rob->isEmpty(tid) &&
1410 (commitStatus[tid] == Running ||
1411 commitStatus[tid] == Idle ||
1412 commitStatus[tid] == FetchTrapPending)) {
1414 if (rob->isHeadReady(tid)) {
1416 DynInstPtr head_inst = rob->readHeadInst(tid);
1421 } else if (head_inst->seqNum < oldest) {