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44 #ifndef __CPU_O3_COMMIT_IMPL_HH__
45 #define __CPU_O3_COMMIT_IMPL_HH__
51 #include "arch/utility.hh"
52 #include "base/loader/symtab.hh"
53 #include "base/cp_annotate.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/checker/cpu.hh"
56 #include "cpu/o3/commit.hh"
57 #include "cpu/o3/thread_state.hh"
58 #include "cpu/base.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/timebuf.hh"
61 #include "debug/Activity.hh"
62 #include "debug/Commit.hh"
63 #include "debug/CommitRate.hh"
64 #include "debug/Drain.hh"
65 #include "debug/ExecFaulting.hh"
66 #include "debug/O3PipeView.hh"
67 #include "params/DerivO3CPU.hh"
68 #include "sim/faults.hh"
69 #include "sim/full_system.hh"
74 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
76 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
82 DefaultCommit<Impl>::TrapEvent::process()
84 // This will get reset by commit if it was switched out at the
85 // time of this event processing.
86 commit->trapSquash[tid] = true;
91 DefaultCommit<Impl>::TrapEvent::description() const
97 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
100 iewToCommitDelay(params->iewToCommitDelay),
101 commitToIEWDelay(params->commitToIEWDelay),
102 renameToROBDelay(params->renameToROBDelay),
103 fetchToCommitDelay(params->commitToFetchDelay),
104 renameWidth(params->renameWidth),
105 commitWidth(params->commitWidth),
106 numThreads(params->numThreads),
108 drainImminent(false),
109 trapLatency(params->trapLatency),
110 canHandleInterrupts(true),
111 avoidQuiesceLiveLock(false)
113 if (commitWidth > Impl::MaxWidth)
114 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
115 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
116 commitWidth, static_cast<int>(Impl::MaxWidth));
119 _nextStatus = Inactive;
120 std::string policy = params->smtCommitPolicy;
122 //Convert string to lowercase
123 std::transform(policy.begin(), policy.end(), policy.begin(),
124 (int(*)(int)) tolower);
126 //Assign commit policy
127 if (policy == "aggressive"){
128 commitPolicy = Aggressive;
130 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
131 } else if (policy == "roundrobin"){
132 commitPolicy = RoundRobin;
134 //Set-Up Priority List
135 for (ThreadID tid = 0; tid < numThreads; tid++) {
136 priority_list.push_back(tid);
139 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
140 } else if (policy == "oldestready"){
141 commitPolicy = OldestReady;
143 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
145 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
146 "RoundRobin,OldestReady}");
149 for (ThreadID tid = 0; tid < numThreads; tid++) {
150 commitStatus[tid] = Idle;
151 changedROBNumEntries[tid] = false;
152 checkEmptyROB[tid] = false;
153 trapInFlight[tid] = false;
154 committedStores[tid] = false;
155 trapSquash[tid] = false;
156 tcSquash[tid] = false;
158 lastCommitedSeqNum[tid] = 0;
159 squashAfterInst[tid] = NULL;
164 template <class Impl>
166 DefaultCommit<Impl>::name() const
168 return cpu->name() + ".commit";
171 template <class Impl>
173 DefaultCommit<Impl>::regProbePoints()
175 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
176 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
179 template <class Impl>
181 DefaultCommit<Impl>::regStats()
183 using namespace Stats;
185 .name(name() + ".commitSquashedInsts")
186 .desc("The number of squashed insts skipped by commit")
187 .prereq(commitSquashedInsts);
189 .name(name() + ".commitSquashEvents")
190 .desc("The number of times commit is told to squash")
191 .prereq(commitSquashEvents);
193 .name(name() + ".commitNonSpecStalls")
194 .desc("The number of times commit has been forced to stall to "
195 "communicate backwards")
196 .prereq(commitNonSpecStalls);
198 .name(name() + ".branchMispredicts")
199 .desc("The number of times a branch was mispredicted")
200 .prereq(branchMispredicts);
202 .init(0,commitWidth,1)
203 .name(name() + ".committed_per_cycle")
204 .desc("Number of insts commited each cycle")
209 .init(cpu->numThreads)
210 .name(name() + ".committedInsts")
211 .desc("Number of instructions committed")
216 .init(cpu->numThreads)
217 .name(name() + ".committedOps")
218 .desc("Number of ops (including micro ops) committed")
223 .init(cpu->numThreads)
224 .name(name() + ".swp_count")
225 .desc("Number of s/w prefetches committed")
230 .init(cpu->numThreads)
231 .name(name() + ".refs")
232 .desc("Number of memory references committed")
237 .init(cpu->numThreads)
238 .name(name() + ".loads")
239 .desc("Number of loads committed")
244 .init(cpu->numThreads)
245 .name(name() + ".membars")
246 .desc("Number of memory barriers committed")
251 .init(cpu->numThreads)
252 .name(name() + ".branches")
253 .desc("Number of branches committed")
258 .init(cpu->numThreads)
259 .name(name() + ".fp_insts")
260 .desc("Number of committed floating point instructions.")
265 .init(cpu->numThreads)
266 .name(name()+".int_insts")
267 .desc("Number of committed integer instructions.")
272 .init(cpu->numThreads)
273 .name(name()+".function_calls")
274 .desc("Number of function calls committed.")
278 statCommittedInstType
279 .init(numThreads,Enums::Num_OpClass)
280 .name(name() + ".op_class")
281 .desc("Class of committed instruction")
282 .flags(total | pdf | dist)
284 statCommittedInstType.ysubnames(Enums::OpClassStrings);
287 .init(cpu->numThreads)
288 .name(name() + ".bw_limited")
289 .desc("number of insts not committed due to BW limits")
293 commitEligibleSamples
294 .name(name() + ".bw_lim_events")
295 .desc("number cycles where commit BW limit reached")
299 template <class Impl>
301 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
306 template <class Impl>
308 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
312 // Setup wire to send information back to IEW.
313 toIEW = timeBuffer->getWire(0);
315 // Setup wire to read data from IEW (for the ROB).
316 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
319 template <class Impl>
321 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
325 // Setup wire to get instructions from rename (for the ROB).
326 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
329 template <class Impl>
331 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
333 renameQueue = rq_ptr;
335 // Setup wire to get instructions from rename (for the ROB).
336 fromRename = renameQueue->getWire(-renameToROBDelay);
339 template <class Impl>
341 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
345 // Setup wire to get instructions from IEW.
346 fromIEW = iewQueue->getWire(-iewToCommitDelay);
349 template <class Impl>
351 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
353 iewStage = iew_stage;
358 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
360 activeThreads = at_ptr;
363 template <class Impl>
365 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
367 for (ThreadID tid = 0; tid < numThreads; tid++)
368 renameMap[tid] = &rm_ptr[tid];
371 template <class Impl>
373 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
378 template <class Impl>
380 DefaultCommit<Impl>::startupStage()
382 rob->setActiveThreads(activeThreads);
385 // Broadcast the number of free entries.
386 for (ThreadID tid = 0; tid < numThreads; tid++) {
387 toIEW->commitInfo[tid].usedROB = true;
388 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
389 toIEW->commitInfo[tid].emptyROB = true;
392 // Commit must broadcast the number of free entries it has at the
393 // start of the simulation, so it starts as active.
394 cpu->activateStage(O3CPU::CommitIdx);
396 cpu->activityThisCycle();
399 template <class Impl>
401 DefaultCommit<Impl>::drain()
406 template <class Impl>
408 DefaultCommit<Impl>::drainResume()
410 drainPending = false;
411 drainImminent = false;
414 template <class Impl>
416 DefaultCommit<Impl>::drainSanityCheck() const
419 rob->drainSanityCheck();
422 template <class Impl>
424 DefaultCommit<Impl>::isDrained() const
426 /* Make sure no one is executing microcode. There are two reasons
428 * - Hardware virtualized CPUs can't switch into the middle of a
429 * microcode sequence.
430 * - The current fetch implementation will most likely get very
431 * confused if it tries to start fetching an instruction that
432 * is executing in the middle of a ucode sequence that changes
433 * address mappings. This can happen on for example x86.
435 for (ThreadID tid = 0; tid < numThreads; tid++) {
436 if (pc[tid].microPC() != 0)
440 /* Make sure that all instructions have finished committing before
441 * declaring the system as drained. We want the pipeline to be
442 * completely empty when we declare the CPU to be drained. This
443 * makes debugging easier since CPU handover and restoring from a
444 * checkpoint with a different CPU should have the same timing.
446 return rob->isEmpty() &&
447 interrupt == NoFault;
450 template <class Impl>
452 DefaultCommit<Impl>::takeOverFrom()
455 _nextStatus = Inactive;
456 for (ThreadID tid = 0; tid < numThreads; tid++) {
457 commitStatus[tid] = Idle;
458 changedROBNumEntries[tid] = false;
459 trapSquash[tid] = false;
460 tcSquash[tid] = false;
461 squashAfterInst[tid] = NULL;
467 template <class Impl>
469 DefaultCommit<Impl>::deactivateThread(ThreadID tid)
471 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
472 priority_list.end(), tid);
474 if (thread_it != priority_list.end()) {
475 priority_list.erase(thread_it);
480 template <class Impl>
482 DefaultCommit<Impl>::updateStatus()
484 // reset ROB changed variable
485 list<ThreadID>::iterator threads = activeThreads->begin();
486 list<ThreadID>::iterator end = activeThreads->end();
488 while (threads != end) {
489 ThreadID tid = *threads++;
491 changedROBNumEntries[tid] = false;
493 // Also check if any of the threads has a trap pending
494 if (commitStatus[tid] == TrapPending ||
495 commitStatus[tid] == FetchTrapPending) {
496 _nextStatus = Active;
500 if (_nextStatus == Inactive && _status == Active) {
501 DPRINTF(Activity, "Deactivating stage.\n");
502 cpu->deactivateStage(O3CPU::CommitIdx);
503 } else if (_nextStatus == Active && _status == Inactive) {
504 DPRINTF(Activity, "Activating stage.\n");
505 cpu->activateStage(O3CPU::CommitIdx);
508 _status = _nextStatus;
511 template <class Impl>
513 DefaultCommit<Impl>::setNextStatus()
517 list<ThreadID>::iterator threads = activeThreads->begin();
518 list<ThreadID>::iterator end = activeThreads->end();
520 while (threads != end) {
521 ThreadID tid = *threads++;
523 if (commitStatus[tid] == ROBSquashing) {
528 squashCounter = squashes;
530 // If commit is currently squashing, then it will have activity for the
531 // next cycle. Set its next status as active.
533 _nextStatus = Active;
537 template <class Impl>
539 DefaultCommit<Impl>::changedROBEntries()
541 list<ThreadID>::iterator threads = activeThreads->begin();
542 list<ThreadID>::iterator end = activeThreads->end();
544 while (threads != end) {
545 ThreadID tid = *threads++;
547 if (changedROBNumEntries[tid]) {
555 template <class Impl>
557 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
559 return rob->numFreeEntries(tid);
562 template <class Impl>
564 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
566 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
568 TrapEvent *trap = new TrapEvent(this, tid);
570 cpu->schedule(trap, cpu->clockEdge(trapLatency));
571 trapInFlight[tid] = true;
572 thread[tid]->trapPending = true;
575 template <class Impl>
577 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
579 assert(!trapInFlight[tid]);
580 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
582 tcSquash[tid] = true;
585 template <class Impl>
587 DefaultCommit<Impl>::squashAll(ThreadID tid)
589 // If we want to include the squashing instruction in the squash,
590 // then use one older sequence number.
591 // Hopefully this doesn't mess things up. Basically I want to squash
592 // all instructions of this thread.
593 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
594 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
596 // All younger instructions will be squashed. Set the sequence
597 // number as the youngest instruction in the ROB (0 in this case.
598 // Hopefully nothing breaks.)
599 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
601 rob->squash(squashed_inst, tid);
602 changedROBNumEntries[tid] = true;
604 // Send back the sequence number of the squashed instruction.
605 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
607 // Send back the squash signal to tell stages that they should
609 toIEW->commitInfo[tid].squash = true;
611 // Send back the rob squashing signal so other stages know that
612 // the ROB is in the process of squashing.
613 toIEW->commitInfo[tid].robSquashing = true;
615 toIEW->commitInfo[tid].mispredictInst = NULL;
616 toIEW->commitInfo[tid].squashInst = NULL;
618 toIEW->commitInfo[tid].pc = pc[tid];
621 template <class Impl>
623 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
627 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
629 thread[tid]->trapPending = false;
630 thread[tid]->noSquashFromTC = false;
631 trapInFlight[tid] = false;
633 trapSquash[tid] = false;
635 commitStatus[tid] = ROBSquashing;
636 cpu->activityThisCycle();
639 template <class Impl>
641 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
645 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
647 thread[tid]->noSquashFromTC = false;
648 assert(!thread[tid]->trapPending);
650 commitStatus[tid] = ROBSquashing;
651 cpu->activityThisCycle();
653 tcSquash[tid] = false;
656 template <class Impl>
658 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
660 DPRINTF(Commit, "Squashing after squash after request, "
661 "restarting at PC %s\n", pc[tid]);
664 // Make sure to inform the fetch stage of which instruction caused
665 // the squash. It'll try to re-fetch an instruction executing in
666 // microcode unless this is set.
667 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
668 squashAfterInst[tid] = NULL;
670 commitStatus[tid] = ROBSquashing;
671 cpu->activityThisCycle();
674 template <class Impl>
676 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
678 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
679 tid, head_inst->seqNum);
681 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
682 commitStatus[tid] = SquashAfterPending;
683 squashAfterInst[tid] = head_inst;
686 template <class Impl>
688 DefaultCommit<Impl>::tick()
690 wroteToTimeBuffer = false;
691 _nextStatus = Inactive;
693 if (activeThreads->empty())
696 list<ThreadID>::iterator threads = activeThreads->begin();
697 list<ThreadID>::iterator end = activeThreads->end();
699 // Check if any of the threads are done squashing. Change the
700 // status if they are done.
701 while (threads != end) {
702 ThreadID tid = *threads++;
704 // Clear the bit saying if the thread has committed stores
706 committedStores[tid] = false;
708 if (commitStatus[tid] == ROBSquashing) {
710 if (rob->isDoneSquashing(tid)) {
711 commitStatus[tid] = Running;
713 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
714 " insts this cycle.\n", tid);
716 toIEW->commitInfo[tid].robSquashing = true;
717 wroteToTimeBuffer = true;
724 markCompletedInsts();
726 threads = activeThreads->begin();
728 while (threads != end) {
729 ThreadID tid = *threads++;
731 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
732 // The ROB has more instructions it can commit. Its next status
734 _nextStatus = Active;
736 DynInstPtr inst = rob->readHeadInst(tid);
738 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
739 " ROB and ready to commit\n",
740 tid, inst->seqNum, inst->pcState());
742 } else if (!rob->isEmpty(tid)) {
743 DynInstPtr inst = rob->readHeadInst(tid);
745 ppCommitStall->notify(inst);
747 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
748 "%s is head of ROB and not ready\n",
749 tid, inst->seqNum, inst->pcState());
752 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
753 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
757 if (wroteToTimeBuffer) {
758 DPRINTF(Activity, "Activity This Cycle.\n");
759 cpu->activityThisCycle();
765 template <class Impl>
767 DefaultCommit<Impl>::handleInterrupt()
769 // Verify that we still have an interrupt to handle
770 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
771 DPRINTF(Commit, "Pending interrupt is cleared by master before "
772 "it got handled. Restart fetching from the orig path.\n");
773 toIEW->commitInfo[0].clearInterrupt = true;
775 avoidQuiesceLiveLock = true;
779 // Wait until all in flight instructions are finished before enterring
781 if (canHandleInterrupts && cpu->instList.empty()) {
782 // Squash or record that I need to squash this cycle if
783 // an interrupt needed to be handled.
784 DPRINTF(Commit, "Interrupt detected.\n");
786 // Clear the interrupt now that it's going to be handled
787 toIEW->commitInfo[0].clearInterrupt = true;
789 assert(!thread[0]->noSquashFromTC);
790 thread[0]->noSquashFromTC = true;
793 cpu->checker->handlePendingInt();
796 // CPU will handle interrupt. Note that we ignore the local copy of
797 // interrupt. This is because the local copy may no longer be the
798 // interrupt that the interrupt controller thinks is being handled.
799 cpu->processInterrupts(cpu->getInterrupts());
801 thread[0]->noSquashFromTC = false;
803 commitStatus[0] = TrapPending;
805 // Generate trap squash event.
806 generateTrapEvent(0);
809 avoidQuiesceLiveLock = false;
811 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
812 "flight, ROB is %sempty\n",
813 canHandleInterrupts ? "not " : "",
814 cpu->instList.empty() ? "" : "not " );
818 template <class Impl>
820 DefaultCommit<Impl>::propagateInterrupt()
822 // Don't propagate intterupts if we are currently handling a trap or
823 // in draining and the last observable instruction has been committed.
824 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
825 tcSquash[0] || drainImminent)
828 // Process interrupts if interrupts are enabled, not in PAL
829 // mode, and no other traps or external squashes are currently
831 // @todo: Allow other threads to handle interrupts.
833 // Get any interrupt that happened
834 interrupt = cpu->getInterrupts();
836 // Tell fetch that there is an interrupt pending. This
837 // will make fetch wait until it sees a non PAL-mode PC,
838 // at which point it stops fetching instructions.
839 if (interrupt != NoFault)
840 toIEW->commitInfo[0].interruptPending = true;
843 template <class Impl>
845 DefaultCommit<Impl>::commit()
848 // Check if we have a interrupt and get read to handle it
849 if (cpu->checkInterrupts(cpu->tcBase(0)))
850 propagateInterrupt();
853 ////////////////////////////////////
854 // Check for any possible squashes, handle them first
855 ////////////////////////////////////
856 list<ThreadID>::iterator threads = activeThreads->begin();
857 list<ThreadID>::iterator end = activeThreads->end();
859 while (threads != end) {
860 ThreadID tid = *threads++;
862 // Not sure which one takes priority. I think if we have
863 // both, that's a bad sign.
864 if (trapSquash[tid]) {
865 assert(!tcSquash[tid]);
867 } else if (tcSquash[tid]) {
868 assert(commitStatus[tid] != TrapPending);
870 } else if (commitStatus[tid] == SquashAfterPending) {
871 // A squash from the previous cycle of the commit stage (i.e.,
872 // commitInsts() called squashAfter) is pending. Squash the
874 squashFromSquashAfter(tid);
877 // Squashed sequence number must be older than youngest valid
878 // instruction in the ROB. This prevents squashes from younger
879 // instructions overriding squashes from older instructions.
880 if (fromIEW->squash[tid] &&
881 commitStatus[tid] != TrapPending &&
882 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
884 if (fromIEW->mispredictInst[tid]) {
886 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
888 fromIEW->mispredictInst[tid]->instAddr(),
889 fromIEW->squashedSeqNum[tid]);
892 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
893 tid, fromIEW->squashedSeqNum[tid]);
896 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
898 fromIEW->pc[tid].nextInstAddr());
900 commitStatus[tid] = ROBSquashing;
902 // If we want to include the squashing instruction in the squash,
903 // then use one older sequence number.
904 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
906 if (fromIEW->includeSquashInst[tid]) {
910 // All younger instructions will be squashed. Set the sequence
911 // number as the youngest instruction in the ROB.
912 youngestSeqNum[tid] = squashed_inst;
914 rob->squash(squashed_inst, tid);
915 changedROBNumEntries[tid] = true;
917 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
919 toIEW->commitInfo[tid].squash = true;
921 // Send back the rob squashing signal so other stages know that
922 // the ROB is in the process of squashing.
923 toIEW->commitInfo[tid].robSquashing = true;
925 toIEW->commitInfo[tid].mispredictInst =
926 fromIEW->mispredictInst[tid];
927 toIEW->commitInfo[tid].branchTaken =
928 fromIEW->branchTaken[tid];
929 toIEW->commitInfo[tid].squashInst =
930 rob->findInst(tid, squashed_inst);
931 if (toIEW->commitInfo[tid].mispredictInst) {
932 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
933 toIEW->commitInfo[tid].branchTaken = true;
937 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
939 if (toIEW->commitInfo[tid].mispredictInst) {
948 if (squashCounter != numThreads) {
949 // If we're not currently squashing, then get instructions.
952 // Try to commit any instructions.
956 //Check for any activity
957 threads = activeThreads->begin();
959 while (threads != end) {
960 ThreadID tid = *threads++;
962 if (changedROBNumEntries[tid]) {
963 toIEW->commitInfo[tid].usedROB = true;
964 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
966 wroteToTimeBuffer = true;
967 changedROBNumEntries[tid] = false;
968 if (rob->isEmpty(tid))
969 checkEmptyROB[tid] = true;
972 // ROB is only considered "empty" for previous stages if: a)
973 // ROB is empty, b) there are no outstanding stores, c) IEW
974 // stage has received any information regarding stores that
976 // c) is checked by making sure to not consider the ROB empty
977 // on the same cycle as when stores have been committed.
978 // @todo: Make this handle multi-cycle communication between
980 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
981 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
982 checkEmptyROB[tid] = false;
983 toIEW->commitInfo[tid].usedROB = true;
984 toIEW->commitInfo[tid].emptyROB = true;
985 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
986 wroteToTimeBuffer = true;
992 template <class Impl>
994 DefaultCommit<Impl>::commitInsts()
996 ////////////////////////////////////
998 // Note that commit will be handled prior to putting new
999 // instructions in the ROB so that the ROB only tries to commit
1000 // instructions it has in this current cycle, and not instructions
1001 // it is writing in during this cycle. Can't commit and squash
1002 // things at the same time...
1003 ////////////////////////////////////
1005 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
1007 unsigned num_committed = 0;
1009 DynInstPtr head_inst;
1011 // Commit as many instructions as possible until the commit bandwidth
1012 // limit is reached, or it becomes impossible to commit any more.
1013 while (num_committed < commitWidth) {
1014 // Check for any interrupt that we've already squashed for
1015 // and start processing it.
1016 if (interrupt != NoFault)
1019 int commit_thread = getCommittingThread();
1021 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1024 head_inst = rob->readHeadInst(commit_thread);
1026 ThreadID tid = head_inst->threadNumber;
1028 assert(tid == commit_thread);
1030 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1031 head_inst->seqNum, tid);
1033 // If the head instruction is squashed, it is ready to retire
1034 // (be removed from the ROB) at any time.
1035 if (head_inst->isSquashed()) {
1037 DPRINTF(Commit, "Retiring squashed instruction from "
1040 rob->retireHead(commit_thread);
1042 ++commitSquashedInsts;
1044 // Record that the number of ROB entries has changed.
1045 changedROBNumEntries[tid] = true;
1047 pc[tid] = head_inst->pcState();
1049 // Increment the total number of non-speculative instructions
1051 // Hack for now: it really shouldn't happen until after the
1052 // commit is deemed to be successful, but this count is needed
1054 thread[tid]->funcExeInst++;
1056 // Try to commit the head instruction.
1057 bool commit_success = commitHead(head_inst, num_committed);
1059 if (commit_success) {
1061 statCommittedInstType[tid][head_inst->opClass()]++;
1062 ppCommit->notify(head_inst);
1064 changedROBNumEntries[tid] = true;
1066 // Set the doneSeqNum to the youngest committed instruction.
1067 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1070 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1071 ((THE_ISA != ALPHA_ISA) ||
1072 (!(pc[0].instAddr() & 0x3)));
1075 // Updates misc. registers.
1076 head_inst->updateMiscRegs();
1078 // Check instruction execution if it successfully commits and
1079 // is not carrying a fault.
1081 cpu->checker->verify(head_inst);
1084 cpu->traceFunctions(pc[tid].instAddr());
1086 TheISA::advancePC(pc[tid], head_inst->staticInst);
1088 // Keep track of the last sequence number commited
1089 lastCommitedSeqNum[tid] = head_inst->seqNum;
1091 // If this is an instruction that doesn't play nicely with
1092 // others squash everything and restart fetch
1093 if (head_inst->isSquashAfter())
1094 squashAfter(tid, head_inst);
1097 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1098 !thread[tid]->trapPending) {
1099 // Last architectually committed instruction.
1100 // Squash the pipeline, stall fetch, and use
1101 // drainImminent to disable interrupts
1102 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1103 squashAfter(tid, head_inst);
1104 cpu->commitDrained(tid);
1105 drainImminent = true;
1109 bool onInstBoundary = !head_inst->isMicroop() ||
1110 head_inst->isLastMicroop() ||
1111 !head_inst->isDelayedCommit();
1113 if (onInstBoundary) {
1116 // Make sure we're not currently updating state while
1117 // handling PC events.
1118 assert(!thread[tid]->noSquashFromTC &&
1119 !thread[tid]->trapPending);
1121 oldpc = pc[tid].instAddr();
1122 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1124 } while (oldpc != pc[tid].instAddr());
1127 "PC skip function event, stopping commit\n");
1132 // Check if an instruction just enabled interrupts and we've
1133 // previously had an interrupt pending that was not handled
1134 // because interrupts were subsequently disabled before the
1135 // pipeline reached a place to handle the interrupt. In that
1136 // case squash now to make sure the interrupt is handled.
1138 // If we don't do this, we might end up in a live lock situation
1139 if (!interrupt && avoidQuiesceLiveLock &&
1140 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1141 squashAfter(tid, head_inst);
1143 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1144 "[tid:%i] [sn:%i].\n",
1145 head_inst->pcState(), tid ,head_inst->seqNum);
1151 DPRINTF(CommitRate, "%i\n", num_committed);
1152 numCommittedDist.sample(num_committed);
1154 if (num_committed == commitWidth) {
1155 commitEligibleSamples++;
1159 template <class Impl>
1161 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1165 ThreadID tid = head_inst->threadNumber;
1167 // If the instruction is not executed yet, then it will need extra
1168 // handling. Signal backwards that it should be executed.
1169 if (!head_inst->isExecuted()) {
1170 // Keep this number correct. We have not yet actually executed
1171 // and committed this instruction.
1172 thread[tid]->funcExeInst--;
1174 // Make sure we are only trying to commit un-executed instructions we
1175 // think are possible.
1176 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1177 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1178 (head_inst->isLoad() && head_inst->uncacheable()));
1180 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1181 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1182 head_inst->seqNum, head_inst->pcState());
1184 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1185 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1189 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1191 // Change the instruction so it won't try to commit again until
1193 head_inst->clearCanCommit();
1195 if (head_inst->isLoad() && head_inst->uncacheable()) {
1196 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1197 head_inst->seqNum, head_inst->pcState());
1198 toIEW->commitInfo[tid].uncached = true;
1199 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1201 ++commitNonSpecStalls;
1207 if (head_inst->isThreadSync()) {
1208 // Not handled for now.
1209 panic("Thread sync instructions are not handled yet.\n");
1212 // Check if the instruction caused a fault. If so, trap.
1213 Fault inst_fault = head_inst->getFault();
1215 // Stores mark themselves as completed.
1216 if (!head_inst->isStore() && inst_fault == NoFault) {
1217 head_inst->setCompleted();
1220 if (inst_fault != NoFault) {
1221 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1222 head_inst->seqNum, head_inst->pcState());
1224 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1225 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1229 head_inst->setCompleted();
1231 // If instruction has faulted, let the checker execute it and
1232 // check if it sees the same fault and control flow.
1234 // Need to check the instruction before its fault is processed
1235 cpu->checker->verify(head_inst);
1238 assert(!thread[tid]->noSquashFromTC);
1240 // Mark that we're in state update mode so that the trap's
1241 // execution doesn't generate extra squashes.
1242 thread[tid]->noSquashFromTC = true;
1244 // Execute the trap. Although it's slightly unrealistic in
1245 // terms of timing (as it doesn't wait for the full timing of
1246 // the trap event to complete before updating state), it's
1247 // needed to update the state as soon as possible. This
1248 // prevents external agents from changing any specific state
1249 // that the trap need.
1250 cpu->trap(inst_fault, tid, head_inst->staticInst);
1252 // Exit state update mode to avoid accidental updating.
1253 thread[tid]->noSquashFromTC = false;
1255 commitStatus[tid] = TrapPending;
1257 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1259 if (head_inst->traceData) {
1260 if (DTRACE(ExecFaulting)) {
1261 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1262 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1263 head_inst->traceData->dump();
1265 delete head_inst->traceData;
1266 head_inst->traceData = NULL;
1269 // Generate trap squash event.
1270 generateTrapEvent(tid);
1274 updateComInstStats(head_inst);
1277 if (thread[tid]->profile) {
1278 thread[tid]->profilePC = head_inst->instAddr();
1279 ProfileNode *node = thread[tid]->profile->consume(
1280 thread[tid]->getTC(), head_inst->staticInst);
1283 thread[tid]->profileNode = node;
1285 if (CPA::available()) {
1286 if (head_inst->isControl()) {
1287 ThreadContext *tc = thread[tid]->getTC();
1288 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1292 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1293 head_inst->seqNum, head_inst->pcState());
1294 if (head_inst->traceData) {
1295 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1296 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1297 head_inst->traceData->dump();
1298 delete head_inst->traceData;
1299 head_inst->traceData = NULL;
1301 if (head_inst->isReturn()) {
1302 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1303 head_inst->seqNum, head_inst->pcState());
1306 // Update the commit rename map
1307 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1308 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1309 head_inst->renamedDestRegIdx(i));
1312 // Finally clear the head ROB entry.
1313 rob->retireHead(tid);
1316 if (DTRACE(O3PipeView)) {
1317 head_inst->commitTick = curTick() - head_inst->fetchTick;
1321 // If this was a store, record it for this cycle.
1322 if (head_inst->isStore())
1323 committedStores[tid] = true;
1325 // Return true to indicate that we have committed an instruction.
1329 template <class Impl>
1331 DefaultCommit<Impl>::getInsts()
1333 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1335 // Read any renamed instructions and place them into the ROB.
1336 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1338 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1341 inst = fromRename->insts[inst_num];
1342 ThreadID tid = inst->threadNumber;
1344 if (!inst->isSquashed() &&
1345 commitStatus[tid] != ROBSquashing &&
1346 commitStatus[tid] != TrapPending) {
1347 changedROBNumEntries[tid] = true;
1349 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1350 inst->pcState(), inst->seqNum, tid);
1352 rob->insertInst(inst);
1354 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1356 youngestSeqNum[tid] = inst->seqNum;
1358 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1359 "squashed, skipping.\n",
1360 inst->pcState(), inst->seqNum, tid);
1365 template <class Impl>
1367 DefaultCommit<Impl>::markCompletedInsts()
1369 // Grab completed insts out of the IEW instruction queue, and mark
1370 // instructions completed within the ROB.
1371 for (int inst_num = 0;
1372 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1375 if (!fromIEW->insts[inst_num]->isSquashed()) {
1376 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1378 fromIEW->insts[inst_num]->threadNumber,
1379 fromIEW->insts[inst_num]->pcState(),
1380 fromIEW->insts[inst_num]->seqNum);
1382 // Mark the instruction as ready to commit.
1383 fromIEW->insts[inst_num]->setCanCommit();
1388 template <class Impl>
1390 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1392 ThreadID tid = inst->threadNumber;
1394 if (!inst->isMicroop() || inst->isLastMicroop())
1395 instsCommitted[tid]++;
1396 opsCommitted[tid]++;
1398 // To match the old model, don't count nops and instruction
1399 // prefetches towards the total commit count.
1400 if (!inst->isNop() && !inst->isInstPrefetch()) {
1401 cpu->instDone(tid, inst);
1405 // Control Instructions
1407 if (inst->isControl())
1408 statComBranches[tid]++;
1411 // Memory references
1413 if (inst->isMemRef()) {
1416 if (inst->isLoad()) {
1417 statComLoads[tid]++;
1421 if (inst->isMemBarrier()) {
1422 statComMembars[tid]++;
1425 // Integer Instruction
1426 if (inst->isInteger())
1427 statComInteger[tid]++;
1429 // Floating Point Instruction
1430 if (inst->isFloating())
1431 statComFloating[tid]++;
1435 statComFunctionCalls[tid]++;
1439 ////////////////////////////////////////
1441 // SMT COMMIT POLICY MAINTAINED HERE //
1443 ////////////////////////////////////////
1444 template <class Impl>
1446 DefaultCommit<Impl>::getCommittingThread()
1448 if (numThreads > 1) {
1449 switch (commitPolicy) {
1452 //If Policy is Aggressive, commit will call
1453 //this function multiple times per
1455 return oldestReady();
1458 return roundRobin();
1461 return oldestReady();
1464 return InvalidThreadID;
1467 assert(!activeThreads->empty());
1468 ThreadID tid = activeThreads->front();
1470 if (commitStatus[tid] == Running ||
1471 commitStatus[tid] == Idle ||
1472 commitStatus[tid] == FetchTrapPending) {
1475 return InvalidThreadID;
1480 template<class Impl>
1482 DefaultCommit<Impl>::roundRobin()
1484 list<ThreadID>::iterator pri_iter = priority_list.begin();
1485 list<ThreadID>::iterator end = priority_list.end();
1487 while (pri_iter != end) {
1488 ThreadID tid = *pri_iter;
1490 if (commitStatus[tid] == Running ||
1491 commitStatus[tid] == Idle ||
1492 commitStatus[tid] == FetchTrapPending) {
1494 if (rob->isHeadReady(tid)) {
1495 priority_list.erase(pri_iter);
1496 priority_list.push_back(tid);
1505 return InvalidThreadID;
1508 template<class Impl>
1510 DefaultCommit<Impl>::oldestReady()
1512 unsigned oldest = 0;
1515 list<ThreadID>::iterator threads = activeThreads->begin();
1516 list<ThreadID>::iterator end = activeThreads->end();
1518 while (threads != end) {
1519 ThreadID tid = *threads++;
1521 if (!rob->isEmpty(tid) &&
1522 (commitStatus[tid] == Running ||
1523 commitStatus[tid] == Idle ||
1524 commitStatus[tid] == FetchTrapPending)) {
1526 if (rob->isHeadReady(tid)) {
1528 DynInstPtr head_inst = rob->readHeadInst(tid);
1533 } else if (head_inst->seqNum < oldest) {
1543 return InvalidThreadID;
1547 #endif//__CPU_O3_COMMIT_IMPL_HH__