src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2010-2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <algorithm>
  45 #include <string>
  46
  47 #include "arch/utility.hh"
  48 #include "base/loader/symtab.hh"
  49 #include "base/cp_annotate.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/checker/cpu.hh"
  52 #include "cpu/o3/commit.hh"
  53 #include "cpu/o3/thread_state.hh"
  54 #include "cpu/base.hh"
  55 #include "cpu/exetrace.hh"
  56 #include "cpu/timebuf.hh"
  57 #include "debug/Activity.hh"
  58 #include "debug/Commit.hh"
  59 #include "debug/CommitRate.hh"
  60 #include "debug/ExecFaulting.hh"
  61 #include "debug/O3PipeView.hh"
  62 #include "params/DerivO3CPU.hh"
  63 #include "sim/faults.hh"
  64 #include "sim/full_system.hh"
  65
  66 using namespace std;
  67
  68 template <class Impl>
  69 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  70                                           ThreadID _tid)
  71     : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
  72 {
  73 }
  74
  75 template <class Impl>
  76 void
  77 DefaultCommit<Impl>::TrapEvent::process()
  78 {
  79     // This will get reset by commit if it was switched out at the
  80     // time of this event processing.
  81     commit->trapSquash[tid] = true;
  82 }
  83
  84 template <class Impl>
  85 const char *
  86 DefaultCommit<Impl>::TrapEvent::description() const
  87 {
  88     return "Trap";
  89 }
  90
  91 template <class Impl>
  92 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
  93     : cpu(_cpu),
  94       squashCounter(0),
  95       iewToCommitDelay(params->iewToCommitDelay),
  96       commitToIEWDelay(params->commitToIEWDelay),
  97       renameToROBDelay(params->renameToROBDelay),
  98       fetchToCommitDelay(params->commitToFetchDelay),
  99       renameWidth(params->renameWidth),
 100       commitWidth(params->commitWidth),
 101       numThreads(params->numThreads),
 102       drainPending(false),
 103       switchedOut(false),
 104       trapLatency(params->trapLatency),
 105       canHandleInterrupts(true)
 106 {
 107     _status = Active;
 108     _nextStatus = Inactive;
 109     std::string policy = params->smtCommitPolicy;
 110
 111     //Convert string to lowercase
 112     std::transform(policy.begin(), policy.end(), policy.begin(),
 113                    (int(*)(int)) tolower);
 114
 115     //Assign commit policy
 116     if (policy == "aggressive"){
 117         commitPolicy = Aggressive;
 118
 119         DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
 120     } else if (policy == "roundrobin"){
 121         commitPolicy = RoundRobin;
 122
 123         //Set-Up Priority List
 124         for (ThreadID tid = 0; tid < numThreads; tid++) {
 125             priority_list.push_back(tid);
 126         }
 127
 128         DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
 129     } else if (policy == "oldestready"){
 130         commitPolicy = OldestReady;
 131
 132         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 133     } else {
 134         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 135                "RoundRobin,OldestReady}");
 136     }
 137
 138     for (ThreadID tid = 0; tid < numThreads; tid++) {
 139         commitStatus[tid] = Idle;
 140         changedROBNumEntries[tid] = false;
 141         checkEmptyROB[tid] = false;
 142         trapInFlight[tid] = false;
 143         committedStores[tid] = false;
 144         trapSquash[tid] = false;
 145         tcSquash[tid] = false;
 146         pc[tid].set(0);
 147         lastCommitedSeqNum[tid] = 0;
 148     }
 149     interrupt = NoFault;
 150 }
 151
 152 template <class Impl>
 153 std::string
 154 DefaultCommit<Impl>::name() const
 155 {
 156     return cpu->name() + ".commit";
 157 }
 158
 159 template <class Impl>
 160 void
 161 DefaultCommit<Impl>::regStats()
 162 {
 163     using namespace Stats;
 164     commitSquashedInsts
 165         .name(name() + ".commitSquashedInsts")
 166         .desc("The number of squashed insts skipped by commit")
 167         .prereq(commitSquashedInsts);
 168     commitSquashEvents
 169         .name(name() + ".commitSquashEvents")
 170         .desc("The number of times commit is told to squash")
 171         .prereq(commitSquashEvents);
 172     commitNonSpecStalls
 173         .name(name() + ".commitNonSpecStalls")
 174         .desc("The number of times commit has been forced to stall to "
 175               "communicate backwards")
 176         .prereq(commitNonSpecStalls);
 177     branchMispredicts
 178         .name(name() + ".branchMispredicts")
 179         .desc("The number of times a branch was mispredicted")
 180         .prereq(branchMispredicts);
 181     numCommittedDist
 182         .init(0,commitWidth,1)
 183         .name(name() + ".committed_per_cycle")
 184         .desc("Number of insts commited each cycle")
 185         .flags(Stats::pdf)
 186         ;
 187
 188     instsCommitted
 189         .init(cpu->numThreads)
 190         .name(name() + ".committedInsts")
 191         .desc("Number of instructions committed")
 192         .flags(total)
 193         ;
 194
 195     opsCommitted
 196         .init(cpu->numThreads)
 197         .name(name() + ".committedOps")
 198         .desc("Number of ops (including micro ops) committed")
 199         .flags(total)
 200         ;
 201
 202     statComSwp
 203         .init(cpu->numThreads)
 204         .name(name() + ".swp_count")
 205         .desc("Number of s/w prefetches committed")
 206         .flags(total)
 207         ;
 208
 209     statComRefs
 210         .init(cpu->numThreads)
 211         .name(name() +  ".refs")
 212         .desc("Number of memory references committed")
 213         .flags(total)
 214         ;
 215
 216     statComLoads
 217         .init(cpu->numThreads)
 218         .name(name() +  ".loads")
 219         .desc("Number of loads committed")
 220         .flags(total)
 221         ;
 222
 223     statComMembars
 224         .init(cpu->numThreads)
 225         .name(name() +  ".membars")
 226         .desc("Number of memory barriers committed")
 227         .flags(total)
 228         ;
 229
 230     statComBranches
 231         .init(cpu->numThreads)
 232         .name(name() + ".branches")
 233         .desc("Number of branches committed")
 234         .flags(total)
 235         ;
 236
 237     statComFloating
 238         .init(cpu->numThreads)
 239         .name(name() + ".fp_insts")
 240         .desc("Number of committed floating point instructions.")
 241         .flags(total)
 242         ;
 243
 244     statComInteger
 245         .init(cpu->numThreads)
 246         .name(name()+".int_insts")
 247         .desc("Number of committed integer instructions.")
 248         .flags(total)
 249         ;
 250
 251     statComFunctionCalls
 252         .init(cpu->numThreads)
 253         .name(name()+".function_calls")
 254         .desc("Number of function calls committed.")
 255         .flags(total)
 256         ;
 257
 258     commitEligible
 259         .init(cpu->numThreads)
 260         .name(name() + ".bw_limited")
 261         .desc("number of insts not committed due to BW limits")
 262         .flags(total)
 263         ;
 264
 265     commitEligibleSamples
 266         .name(name() + ".bw_lim_events")
 267         .desc("number cycles where commit BW limit reached")
 268         ;
 269 }
 270
 271 template <class Impl>
 272 void
 273 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 274 {
 275     thread = threads;
 276 }
 277
 278 template <class Impl>
 279 void
 280 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 281 {
 282     timeBuffer = tb_ptr;
 283
 284     // Setup wire to send information back to IEW.
 285     toIEW = timeBuffer->getWire(0);
 286
 287     // Setup wire to read data from IEW (for the ROB).
 288     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 289 }
 290
 291 template <class Impl>
 292 void
 293 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 294 {
 295     fetchQueue = fq_ptr;
 296
 297     // Setup wire to get instructions from rename (for the ROB).
 298     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 299 }
 300
 301 template <class Impl>
 302 void
 303 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 304 {
 305     renameQueue = rq_ptr;
 306
 307     // Setup wire to get instructions from rename (for the ROB).
 308     fromRename = renameQueue->getWire(-renameToROBDelay);
 309 }
 310
 311 template <class Impl>
 312 void
 313 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 314 {
 315     iewQueue = iq_ptr;
 316
 317     // Setup wire to get instructions from IEW.
 318     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 319 }
 320
 321 template <class Impl>
 322 void
 323 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 324 {
 325     iewStage = iew_stage;
 326 }
 327
 328 template<class Impl>
 329 void
 330 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 331 {
 332     activeThreads = at_ptr;
 333 }
 334
 335 template <class Impl>
 336 void
 337 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 338 {
 339     for (ThreadID tid = 0; tid < numThreads; tid++)
 340         renameMap[tid] = &rm_ptr[tid];
 341 }
 342
 343 template <class Impl>
 344 void
 345 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 346 {
 347     rob = rob_ptr;
 348 }
 349
 350 template <class Impl>
 351 void
 352 DefaultCommit<Impl>::initStage()
 353 {
 354     rob->setActiveThreads(activeThreads);
 355     rob->resetEntries();
 356
 357     // Broadcast the number of free entries.
 358     for (ThreadID tid = 0; tid < numThreads; tid++) {
 359         toIEW->commitInfo[tid].usedROB = true;
 360         toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 361         toIEW->commitInfo[tid].emptyROB = true;
 362     }
 363
 364     // Commit must broadcast the number of free entries it has at the
 365     // start of the simulation, so it starts as active.
 366     cpu->activateStage(O3CPU::CommitIdx);
 367
 368     cpu->activityThisCycle();
 369 }
 370
 371 template <class Impl>
 372 bool
 373 DefaultCommit<Impl>::drain()
 374 {
 375     drainPending = true;
 376
 377     return false;
 378 }
 379
 380 template <class Impl>
 381 void
 382 DefaultCommit<Impl>::switchOut()
 383 {
 384     switchedOut = true;
 385     drainPending = false;
 386     rob->switchOut();
 387 }
 388
 389 template <class Impl>
 390 void
 391 DefaultCommit<Impl>::resume()
 392 {
 393     drainPending = false;
 394 }
 395
 396 template <class Impl>
 397 void
 398 DefaultCommit<Impl>::takeOverFrom()
 399 {
 400     switchedOut = false;
 401     _status = Active;
 402     _nextStatus = Inactive;
 403     for (ThreadID tid = 0; tid < numThreads; tid++) {
 404         commitStatus[tid] = Idle;
 405         changedROBNumEntries[tid] = false;
 406         trapSquash[tid] = false;
 407         tcSquash[tid] = false;
 408     }
 409     squashCounter = 0;
 410     rob->takeOverFrom();
 411 }
 412
 413 template <class Impl>
 414 void
 415 DefaultCommit<Impl>::updateStatus()
 416 {
 417     // reset ROB changed variable
 418     list<ThreadID>::iterator threads = activeThreads->begin();
 419     list<ThreadID>::iterator end = activeThreads->end();
 420
 421     while (threads != end) {
 422         ThreadID tid = *threads++;
 423
 424         changedROBNumEntries[tid] = false;
 425
 426         // Also check if any of the threads has a trap pending
 427         if (commitStatus[tid] == TrapPending ||
 428             commitStatus[tid] == FetchTrapPending) {
 429             _nextStatus = Active;
 430         }
 431     }
 432
 433     if (_nextStatus == Inactive && _status == Active) {
 434         DPRINTF(Activity, "Deactivating stage.\n");
 435         cpu->deactivateStage(O3CPU::CommitIdx);
 436     } else if (_nextStatus == Active && _status == Inactive) {
 437         DPRINTF(Activity, "Activating stage.\n");
 438         cpu->activateStage(O3CPU::CommitIdx);
 439     }
 440
 441     _status = _nextStatus;
 442 }
 443
 444 template <class Impl>
 445 void
 446 DefaultCommit<Impl>::setNextStatus()
 447 {
 448     int squashes = 0;
 449
 450     list<ThreadID>::iterator threads = activeThreads->begin();
 451     list<ThreadID>::iterator end = activeThreads->end();
 452
 453     while (threads != end) {
 454         ThreadID tid = *threads++;
 455
 456         if (commitStatus[tid] == ROBSquashing) {
 457             squashes++;
 458         }
 459     }
 460
 461     squashCounter = squashes;
 462
 463     // If commit is currently squashing, then it will have activity for the
 464     // next cycle. Set its next status as active.
 465     if (squashCounter) {
 466         _nextStatus = Active;
 467     }
 468 }
 469
 470 template <class Impl>
 471 bool
 472 DefaultCommit<Impl>::changedROBEntries()
 473 {
 474     list<ThreadID>::iterator threads = activeThreads->begin();
 475     list<ThreadID>::iterator end = activeThreads->end();
 476
 477     while (threads != end) {
 478         ThreadID tid = *threads++;
 479
 480         if (changedROBNumEntries[tid]) {
 481             return true;
 482         }
 483     }
 484
 485     return false;
 486 }
 487
 488 template <class Impl>
 489 size_t
 490 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
 491 {
 492     return rob->numFreeEntries(tid);
 493 }
 494
 495 template <class Impl>
 496 void
 497 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
 498 {
 499     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 500
 501     TrapEvent *trap = new TrapEvent(this, tid);
 502
 503     cpu->schedule(trap, cpu->clockEdge(trapLatency));
 504     trapInFlight[tid] = true;
 505     thread[tid]->trapPending = true;
 506 }
 507
 508 template <class Impl>
 509 void
 510 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
 511 {
 512     assert(!trapInFlight[tid]);
 513     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 514
 515     tcSquash[tid] = true;
 516 }
 517
 518 template <class Impl>
 519 void
 520 DefaultCommit<Impl>::squashAll(ThreadID tid)
 521 {
 522     // If we want to include the squashing instruction in the squash,
 523     // then use one older sequence number.
 524     // Hopefully this doesn't mess things up.  Basically I want to squash
 525     // all instructions of this thread.
 526     InstSeqNum squashed_inst = rob->isEmpty() ?
 527         lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
 528
 529     // All younger instructions will be squashed. Set the sequence
 530     // number as the youngest instruction in the ROB (0 in this case.
 531     // Hopefully nothing breaks.)
 532     youngestSeqNum[tid] = lastCommitedSeqNum[tid];
 533
 534     rob->squash(squashed_inst, tid);
 535     changedROBNumEntries[tid] = true;
 536
 537     // Send back the sequence number of the squashed instruction.
 538     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 539
 540     // Send back the squash signal to tell stages that they should
 541     // squash.
 542     toIEW->commitInfo[tid].squash = true;
 543
 544     // Send back the rob squashing signal so other stages know that
 545     // the ROB is in the process of squashing.
 546     toIEW->commitInfo[tid].robSquashing = true;
 547
 548     toIEW->commitInfo[tid].mispredictInst = NULL;
 549     toIEW->commitInfo[tid].squashInst = NULL;
 550
 551     toIEW->commitInfo[tid].pc = pc[tid];
 552 }
 553
 554 template <class Impl>
 555 void
 556 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
 557 {
 558     squashAll(tid);
 559
 560     DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
 561
 562     thread[tid]->trapPending = false;
 563     thread[tid]->inSyscall = false;
 564     trapInFlight[tid] = false;
 565
 566     trapSquash[tid] = false;
 567
 568     commitStatus[tid] = ROBSquashing;
 569     cpu->activityThisCycle();
 570 }
 571
 572 template <class Impl>
 573 void
 574 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
 575 {
 576     squashAll(tid);
 577
 578     DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
 579
 580     thread[tid]->inSyscall = false;
 581     assert(!thread[tid]->trapPending);
 582
 583     commitStatus[tid] = ROBSquashing;
 584     cpu->activityThisCycle();
 585
 586     tcSquash[tid] = false;
 587 }
 588
 589 template <class Impl>
 590 void
 591 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
 592         uint64_t squash_after_seq_num)
 593 {
 594     youngestSeqNum[tid] = squash_after_seq_num;
 595
 596     rob->squash(squash_after_seq_num, tid);
 597     changedROBNumEntries[tid] = true;
 598
 599     // Send back the sequence number of the squashed instruction.
 600     toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
 601
 602     toIEW->commitInfo[tid].squashInst = head_inst;
 603     // Send back the squash signal to tell stages that they should squash.
 604     toIEW->commitInfo[tid].squash = true;
 605
 606     // Send back the rob squashing signal so other stages know that
 607     // the ROB is in the process of squashing.
 608     toIEW->commitInfo[tid].robSquashing = true;
 609
 610     toIEW->commitInfo[tid].mispredictInst = NULL;
 611
 612     toIEW->commitInfo[tid].pc = pc[tid];
 613     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
 614             tid, squash_after_seq_num);
 615     commitStatus[tid] = ROBSquashing;
 616 }
 617
 618 template <class Impl>
 619 void
 620 DefaultCommit<Impl>::tick()
 621 {
 622     wroteToTimeBuffer = false;
 623     _nextStatus = Inactive;
 624
 625     if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
 626         interrupt == NoFault) {
 627         cpu->signalDrained();
 628         drainPending = false;
 629         return;
 630     }
 631
 632     if (activeThreads->empty())
 633         return;
 634
 635     list<ThreadID>::iterator threads = activeThreads->begin();
 636     list<ThreadID>::iterator end = activeThreads->end();
 637
 638     // Check if any of the threads are done squashing.  Change the
 639     // status if they are done.
 640     while (threads != end) {
 641         ThreadID tid = *threads++;
 642
 643         // Clear the bit saying if the thread has committed stores
 644         // this cycle.
 645         committedStores[tid] = false;
 646
 647         if (commitStatus[tid] == ROBSquashing) {
 648
 649             if (rob->isDoneSquashing(tid)) {
 650                 commitStatus[tid] = Running;
 651             } else {
 652                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 653                         " insts this cycle.\n", tid);
 654                 rob->doSquash(tid);
 655                 toIEW->commitInfo[tid].robSquashing = true;
 656                 wroteToTimeBuffer = true;
 657             }
 658         }
 659     }
 660
 661     commit();
 662
 663     markCompletedInsts();
 664
 665     threads = activeThreads->begin();
 666
 667     while (threads != end) {
 668         ThreadID tid = *threads++;
 669
 670         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 671             // The ROB has more instructions it can commit. Its next status
 672             // will be active.
 673             _nextStatus = Active;
 674
 675             DynInstPtr inst = rob->readHeadInst(tid);
 676
 677             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
 678                     " ROB and ready to commit\n",
 679                     tid, inst->seqNum, inst->pcState());
 680
 681         } else if (!rob->isEmpty(tid)) {
 682             DynInstPtr inst = rob->readHeadInst(tid);
 683
 684             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 685                     "%s is head of ROB and not ready\n",
 686                     tid, inst->seqNum, inst->pcState());
 687         }
 688
 689         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 690                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 691     }
 692
 693
 694     if (wroteToTimeBuffer) {
 695         DPRINTF(Activity, "Activity This Cycle.\n");
 696         cpu->activityThisCycle();
 697     }
 698
 699     updateStatus();
 700 }
 701
 702 template <class Impl>
 703 void
 704 DefaultCommit<Impl>::handleInterrupt()
 705 {
 706     // Verify that we still have an interrupt to handle
 707     if (!cpu->checkInterrupts(cpu->tcBase(0))) {
 708         DPRINTF(Commit, "Pending interrupt is cleared by master before "
 709                 "it got handled. Restart fetching from the orig path.\n");
 710         toIEW->commitInfo[0].clearInterrupt = true;
 711         interrupt = NoFault;
 712         return;
 713     }
 714
 715     // Wait until all in flight instructions are finished before enterring
 716     // the interrupt.
 717     if (canHandleInterrupts && cpu->instList.empty()) {
 718         // Squash or record that I need to squash this cycle if
 719         // an interrupt needed to be handled.
 720         DPRINTF(Commit, "Interrupt detected.\n");
 721
 722         // Clear the interrupt now that it's going to be handled
 723         toIEW->commitInfo[0].clearInterrupt = true;
 724
 725         assert(!thread[0]->inSyscall);
 726         thread[0]->inSyscall = true;
 727
 728         if (cpu->checker) {
 729             cpu->checker->handlePendingInt();
 730         }
 731
 732         // CPU will handle interrupt.
 733         cpu->processInterrupts(interrupt);
 734
 735         thread[0]->inSyscall = false;
 736
 737         commitStatus[0] = TrapPending;
 738
 739         // Generate trap squash event.
 740         generateTrapEvent(0);
 741
 742         interrupt = NoFault;
 743     } else {
 744         DPRINTF(Commit, "Interrupt pending: instruction is %sin "
 745                 "flight, ROB is %sempty\n",
 746                 canHandleInterrupts ? "not " : "",
 747                 cpu->instList.empty() ? "" : "not " );
 748     }
 749 }
 750
 751 template <class Impl>
 752 void
 753 DefaultCommit<Impl>::propagateInterrupt()
 754 {
 755     if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
 756             tcSquash[0])
 757         return;
 758
 759     // Process interrupts if interrupts are enabled, not in PAL
 760     // mode, and no other traps or external squashes are currently
 761     // pending.
 762     // @todo: Allow other threads to handle interrupts.
 763
 764     // Get any interrupt that happened
 765     interrupt = cpu->getInterrupts();
 766
 767     // Tell fetch that there is an interrupt pending.  This
 768     // will make fetch wait until it sees a non PAL-mode PC,
 769     // at which point it stops fetching instructions.
 770     if (interrupt != NoFault)
 771         toIEW->commitInfo[0].interruptPending = true;
 772 }
 773
 774 template <class Impl>
 775 void
 776 DefaultCommit<Impl>::commit()
 777 {
 778     if (FullSystem) {
 779         // Check if we have a interrupt and get read to handle it
 780         if (cpu->checkInterrupts(cpu->tcBase(0)))
 781             propagateInterrupt();
 782     }
 783
 784     ////////////////////////////////////
 785     // Check for any possible squashes, handle them first
 786     ////////////////////////////////////
 787     list<ThreadID>::iterator threads = activeThreads->begin();
 788     list<ThreadID>::iterator end = activeThreads->end();
 789
 790     while (threads != end) {
 791         ThreadID tid = *threads++;
 792
 793         // Not sure which one takes priority.  I think if we have
 794         // both, that's a bad sign.
 795         if (trapSquash[tid] == true) {
 796             assert(!tcSquash[tid]);
 797             squashFromTrap(tid);
 798         } else if (tcSquash[tid] == true) {
 799             assert(commitStatus[tid] != TrapPending);
 800             squashFromTC(tid);
 801         }
 802
 803         // Squashed sequence number must be older than youngest valid
 804         // instruction in the ROB. This prevents squashes from younger
 805         // instructions overriding squashes from older instructions.
 806         if (fromIEW->squash[tid] &&
 807             commitStatus[tid] != TrapPending &&
 808             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 809
 810             if (fromIEW->mispredictInst[tid]) {
 811                 DPRINTF(Commit,
 812                     "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
 813                     tid,
 814                     fromIEW->mispredictInst[tid]->instAddr(),
 815                     fromIEW->squashedSeqNum[tid]);
 816             } else {
 817                 DPRINTF(Commit,
 818                     "[tid:%i]: Squashing due to order violation [sn:%i]\n",
 819                     tid, fromIEW->squashedSeqNum[tid]);
 820             }
 821
 822             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 823                     tid,
 824                     fromIEW->pc[tid].nextInstAddr());
 825
 826             commitStatus[tid] = ROBSquashing;
 827
 828             // If we want to include the squashing instruction in the squash,
 829             // then use one older sequence number.
 830             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 831
 832             if (fromIEW->includeSquashInst[tid] == true) {
 833                 squashed_inst--;
 834             }
 835
 836             // All younger instructions will be squashed. Set the sequence
 837             // number as the youngest instruction in the ROB.
 838             youngestSeqNum[tid] = squashed_inst;
 839
 840             rob->squash(squashed_inst, tid);
 841             changedROBNumEntries[tid] = true;
 842
 843             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 844
 845             toIEW->commitInfo[tid].squash = true;
 846
 847             // Send back the rob squashing signal so other stages know that
 848             // the ROB is in the process of squashing.
 849             toIEW->commitInfo[tid].robSquashing = true;
 850
 851             toIEW->commitInfo[tid].mispredictInst =
 852                 fromIEW->mispredictInst[tid];
 853             toIEW->commitInfo[tid].branchTaken =
 854                 fromIEW->branchTaken[tid];
 855             toIEW->commitInfo[tid].squashInst =
 856                                     rob->findInst(tid, squashed_inst);
 857             if (toIEW->commitInfo[tid].mispredictInst) {
 858                 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
 859                      toIEW->commitInfo[tid].branchTaken = true;
 860                 }
 861             }
 862
 863             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 864
 865             if (toIEW->commitInfo[tid].mispredictInst) {
 866                 ++branchMispredicts;
 867             }
 868         }
 869
 870     }
 871
 872     setNextStatus();
 873
 874     if (squashCounter != numThreads) {
 875         // If we're not currently squashing, then get instructions.
 876         getInsts();
 877
 878         // Try to commit any instructions.
 879         commitInsts();
 880     }
 881
 882     //Check for any activity
 883     threads = activeThreads->begin();
 884
 885     while (threads != end) {
 886         ThreadID tid = *threads++;
 887
 888         if (changedROBNumEntries[tid]) {
 889             toIEW->commitInfo[tid].usedROB = true;
 890             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 891
 892             wroteToTimeBuffer = true;
 893             changedROBNumEntries[tid] = false;
 894             if (rob->isEmpty(tid))
 895                 checkEmptyROB[tid] = true;
 896         }
 897
 898         // ROB is only considered "empty" for previous stages if: a)
 899         // ROB is empty, b) there are no outstanding stores, c) IEW
 900         // stage has received any information regarding stores that
 901         // committed.
 902         // c) is checked by making sure to not consider the ROB empty
 903         // on the same cycle as when stores have been committed.
 904         // @todo: Make this handle multi-cycle communication between
 905         // commit and IEW.
 906         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
 907             !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
 908             checkEmptyROB[tid] = false;
 909             toIEW->commitInfo[tid].usedROB = true;
 910             toIEW->commitInfo[tid].emptyROB = true;
 911             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 912             wroteToTimeBuffer = true;
 913         }
 914
 915     }
 916 }
 917
 918 template <class Impl>
 919 void
 920 DefaultCommit<Impl>::commitInsts()
 921 {
 922     ////////////////////////////////////
 923     // Handle commit
 924     // Note that commit will be handled prior to putting new
 925     // instructions in the ROB so that the ROB only tries to commit
 926     // instructions it has in this current cycle, and not instructions
 927     // it is writing in during this cycle.  Can't commit and squash
 928     // things at the same time...
 929     ////////////////////////////////////
 930
 931     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 932
 933     unsigned num_committed = 0;
 934
 935     DynInstPtr head_inst;
 936
 937     // Commit as many instructions as possible until the commit bandwidth
 938     // limit is reached, or it becomes impossible to commit any more.
 939     while (num_committed < commitWidth) {
 940         // Check for any interrupt that we've already squashed for
 941         // and start processing it.
 942         if (interrupt != NoFault)
 943             handleInterrupt();
 944
 945         int commit_thread = getCommittingThread();
 946
 947         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 948             break;
 949
 950         head_inst = rob->readHeadInst(commit_thread);
 951
 952         ThreadID tid = head_inst->threadNumber;
 953
 954         assert(tid == commit_thread);
 955
 956         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 957                 head_inst->seqNum, tid);
 958
 959         // If the head instruction is squashed, it is ready to retire
 960         // (be removed from the ROB) at any time.
 961         if (head_inst->isSquashed()) {
 962
 963             DPRINTF(Commit, "Retiring squashed instruction from "
 964                     "ROB.\n");
 965
 966             rob->retireHead(commit_thread);
 967
 968             ++commitSquashedInsts;
 969
 970             // Record that the number of ROB entries has changed.
 971             changedROBNumEntries[tid] = true;
 972         } else {
 973             pc[tid] = head_inst->pcState();
 974
 975             // Increment the total number of non-speculative instructions
 976             // executed.
 977             // Hack for now: it really shouldn't happen until after the
 978             // commit is deemed to be successful, but this count is needed
 979             // for syscalls.
 980             thread[tid]->funcExeInst++;
 981
 982             // Try to commit the head instruction.
 983             bool commit_success = commitHead(head_inst, num_committed);
 984
 985             if (commit_success) {
 986                 ++num_committed;
 987
 988                 changedROBNumEntries[tid] = true;
 989
 990                 // Set the doneSeqNum to the youngest committed instruction.
 991                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 992
 993                 if (tid == 0) {
 994                     canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
 995                                            ((THE_ISA != ALPHA_ISA) ||
 996                                              (!(pc[0].instAddr() & 0x3)));
 997                 }
 998
 999                 // Updates misc. registers.
1000                 head_inst->updateMiscRegs();
1001
1002                 cpu->traceFunctions(pc[tid].instAddr());
1003
1004                 TheISA::advancePC(pc[tid], head_inst->staticInst);
1005
1006                 // Keep track of the last sequence number commited
1007                 lastCommitedSeqNum[tid] = head_inst->seqNum;
1008
1009                 // If this is an instruction that doesn't play nicely with
1010                 // others squash everything and restart fetch
1011                 if (head_inst->isSquashAfter())
1012                     squashAfter(tid, head_inst, head_inst->seqNum);
1013
1014                 int count = 0;
1015                 Addr oldpc;
1016                 // Debug statement.  Checks to make sure we're not
1017                 // currently updating state while handling PC events.
1018                 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1019                 do {
1020                     oldpc = pc[tid].instAddr();
1021                     cpu->system->pcEventQueue.service(thread[tid]->getTC());
1022                     count++;
1023                 } while (oldpc != pc[tid].instAddr());
1024                 if (count > 1) {
1025                     DPRINTF(Commit,
1026                             "PC skip function event, stopping commit\n");
1027                     break;
1028                 }
1029             } else {
1030                 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1031                         "[tid:%i] [sn:%i].\n",
1032                         head_inst->pcState(), tid ,head_inst->seqNum);
1033                 break;
1034             }
1035         }
1036     }
1037
1038     DPRINTF(CommitRate, "%i\n", num_committed);
1039     numCommittedDist.sample(num_committed);
1040
1041     if (num_committed == commitWidth) {
1042         commitEligibleSamples++;
1043     }
1044 }
1045
1046 template <class Impl>
1047 bool
1048 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1049 {
1050     assert(head_inst);
1051
1052     ThreadID tid = head_inst->threadNumber;
1053
1054     // If the instruction is not executed yet, then it will need extra
1055     // handling.  Signal backwards that it should be executed.
1056     if (!head_inst->isExecuted()) {
1057         // Keep this number correct.  We have not yet actually executed
1058         // and committed this instruction.
1059         thread[tid]->funcExeInst--;
1060
1061         if (head_inst->isNonSpeculative() ||
1062             head_inst->isStoreConditional() ||
1063             head_inst->isMemBarrier() ||
1064             head_inst->isWriteBarrier()) {
1065
1066             DPRINTF(Commit, "Encountered a barrier or non-speculative "
1067                     "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1068                     head_inst->seqNum, head_inst->pcState());
1069
1070             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1071                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1072                 return false;
1073             }
1074
1075             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1076
1077             // Change the instruction so it won't try to commit again until
1078             // it is executed.
1079             head_inst->clearCanCommit();
1080
1081             ++commitNonSpecStalls;
1082
1083             return false;
1084         } else if (head_inst->isLoad()) {
1085             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1086                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1087                 return false;
1088             }
1089
1090             assert(head_inst->uncacheable());
1091             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1092                     head_inst->seqNum, head_inst->pcState());
1093
1094             // Send back the non-speculative instruction's sequence
1095             // number.  Tell the lsq to re-execute the load.
1096             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1097             toIEW->commitInfo[tid].uncached = true;
1098             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1099
1100             head_inst->clearCanCommit();
1101
1102             return false;
1103         } else {
1104             panic("Trying to commit un-executed instruction "
1105                   "of unknown type!\n");
1106         }
1107     }
1108
1109     if (head_inst->isThreadSync()) {
1110         // Not handled for now.
1111         panic("Thread sync instructions are not handled yet.\n");
1112     }
1113
1114     // Check if the instruction caused a fault.  If so, trap.
1115     Fault inst_fault = head_inst->getFault();
1116
1117     // Stores mark themselves as completed.
1118     if (!head_inst->isStore() && inst_fault == NoFault) {
1119         head_inst->setCompleted();
1120     }
1121
1122     // Use checker prior to updating anything due to traps or PC
1123     // based events.
1124     if (cpu->checker) {
1125         cpu->checker->verify(head_inst);
1126     }
1127
1128     if (inst_fault != NoFault) {
1129         DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1130                 head_inst->seqNum, head_inst->pcState());
1131
1132         if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1133             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1134             return false;
1135         }
1136
1137         head_inst->setCompleted();
1138
1139         if (cpu->checker) {
1140             // Need to check the instruction before its fault is processed
1141             cpu->checker->verify(head_inst);
1142         }
1143
1144         assert(!thread[tid]->inSyscall);
1145
1146         // Mark that we're in state update mode so that the trap's
1147         // execution doesn't generate extra squashes.
1148         thread[tid]->inSyscall = true;
1149
1150         // Execute the trap.  Although it's slightly unrealistic in
1151         // terms of timing (as it doesn't wait for the full timing of
1152         // the trap event to complete before updating state), it's
1153         // needed to update the state as soon as possible.  This
1154         // prevents external agents from changing any specific state
1155         // that the trap need.
1156         cpu->trap(inst_fault, tid, head_inst->staticInst);
1157
1158         // Exit state update mode to avoid accidental updating.
1159         thread[tid]->inSyscall = false;
1160
1161         commitStatus[tid] = TrapPending;
1162
1163         DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1164             head_inst->seqNum);
1165         if (head_inst->traceData) {
1166             if (DTRACE(ExecFaulting)) {
1167                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1168                 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1169                 head_inst->traceData->dump();
1170             }
1171             delete head_inst->traceData;
1172             head_inst->traceData = NULL;
1173         }
1174
1175         // Generate trap squash event.
1176         generateTrapEvent(tid);
1177         return false;
1178     }
1179
1180     updateComInstStats(head_inst);
1181
1182     if (FullSystem) {
1183         if (thread[tid]->profile) {
1184             thread[tid]->profilePC = head_inst->instAddr();
1185             ProfileNode *node = thread[tid]->profile->consume(
1186                     thread[tid]->getTC(), head_inst->staticInst);
1187
1188             if (node)
1189                 thread[tid]->profileNode = node;
1190         }
1191         if (CPA::available()) {
1192             if (head_inst->isControl()) {
1193                 ThreadContext *tc = thread[tid]->getTC();
1194                 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1195             }
1196         }
1197     }
1198     DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1199             head_inst->seqNum, head_inst->pcState());
1200     if (head_inst->traceData) {
1201         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1202         head_inst->traceData->setCPSeq(thread[tid]->numOp);
1203         head_inst->traceData->dump();
1204         delete head_inst->traceData;
1205         head_inst->traceData = NULL;
1206     }
1207     if (head_inst->isReturn()) {
1208         DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1209                         head_inst->seqNum, head_inst->pcState());
1210     }
1211
1212     // Update the commit rename map
1213     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1214         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1215                                  head_inst->renamedDestRegIdx(i));
1216     }
1217
1218     // Finally clear the head ROB entry.
1219     rob->retireHead(tid);
1220
1221 #if TRACING_ON
1222     // Print info needed by the pipeline activity viewer.
1223     DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1224              head_inst->fetchTick,
1225              head_inst->instAddr(),
1226              head_inst->microPC(),
1227              head_inst->seqNum,
1228              head_inst->staticInst->disassemble(head_inst->instAddr()));
1229     DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->fetchTick + head_inst->decodeTick);
1230     DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->fetchTick + head_inst->renameTick);
1231     DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->fetchTick + head_inst->dispatchTick);
1232     DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->fetchTick + head_inst->issueTick);
1233     DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->fetchTick + head_inst->completeTick);
1234     DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1235 #endif
1236
1237     // If this was a store, record it for this cycle.
1238     if (head_inst->isStore())
1239         committedStores[tid] = true;
1240
1241     // Return true to indicate that we have committed an instruction.
1242     return true;
1243 }
1244
1245 template <class Impl>
1246 void
1247 DefaultCommit<Impl>::getInsts()
1248 {
1249     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1250
1251     // Read any renamed instructions and place them into the ROB.
1252     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1253
1254     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1255         DynInstPtr inst;
1256
1257         inst = fromRename->insts[inst_num];
1258         ThreadID tid = inst->threadNumber;
1259
1260         if (!inst->isSquashed() &&
1261             commitStatus[tid] != ROBSquashing &&
1262             commitStatus[tid] != TrapPending) {
1263             changedROBNumEntries[tid] = true;
1264
1265             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1266                     inst->pcState(), inst->seqNum, tid);
1267
1268             rob->insertInst(inst);
1269
1270             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1271
1272             youngestSeqNum[tid] = inst->seqNum;
1273         } else {
1274             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1275                     "squashed, skipping.\n",
1276                     inst->pcState(), inst->seqNum, tid);
1277         }
1278     }
1279 }
1280
1281 template <class Impl>
1282 void
1283 DefaultCommit<Impl>::skidInsert()
1284 {
1285     DPRINTF(Commit, "Attempting to any instructions from rename into "
1286             "skidBuffer.\n");
1287
1288     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1289         DynInstPtr inst = fromRename->insts[inst_num];
1290
1291         if (!inst->isSquashed()) {
1292             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1293                     "skidBuffer.\n", inst->pcState(), inst->seqNum,
1294                     inst->threadNumber);
1295             skidBuffer.push(inst);
1296         } else {
1297             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1298                     "squashed, skipping.\n",
1299                     inst->pcState(), inst->seqNum, inst->threadNumber);
1300         }
1301     }
1302 }
1303
1304 template <class Impl>
1305 void
1306 DefaultCommit<Impl>::markCompletedInsts()
1307 {
1308     // Grab completed insts out of the IEW instruction queue, and mark
1309     // instructions completed within the ROB.
1310     for (int inst_num = 0;
1311          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1312          ++inst_num)
1313     {
1314         if (!fromIEW->insts[inst_num]->isSquashed()) {
1315             DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1316                     "within ROB.\n",
1317                     fromIEW->insts[inst_num]->threadNumber,
1318                     fromIEW->insts[inst_num]->pcState(),
1319                     fromIEW->insts[inst_num]->seqNum);
1320
1321             // Mark the instruction as ready to commit.
1322             fromIEW->insts[inst_num]->setCanCommit();
1323         }
1324     }
1325 }
1326
1327 template <class Impl>
1328 bool
1329 DefaultCommit<Impl>::robDoneSquashing()
1330 {
1331     list<ThreadID>::iterator threads = activeThreads->begin();
1332     list<ThreadID>::iterator end = activeThreads->end();
1333
1334     while (threads != end) {
1335         ThreadID tid = *threads++;
1336
1337         if (!rob->isDoneSquashing(tid))
1338             return false;
1339     }
1340
1341     return true;
1342 }
1343
1344 template <class Impl>
1345 void
1346 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1347 {
1348     ThreadID tid = inst->threadNumber;
1349
1350     if (!inst->isMicroop() || inst->isLastMicroop())
1351         instsCommitted[tid]++;
1352     opsCommitted[tid]++;
1353
1354     // To match the old model, don't count nops and instruction
1355     // prefetches towards the total commit count.
1356     if (!inst->isNop() && !inst->isInstPrefetch()) {
1357         cpu->instDone(tid, inst);
1358     }
1359
1360     //
1361     //  Control Instructions
1362     //
1363     if (inst->isControl())
1364         statComBranches[tid]++;
1365
1366     //
1367     //  Memory references
1368     //
1369     if (inst->isMemRef()) {
1370         statComRefs[tid]++;
1371
1372         if (inst->isLoad()) {
1373             statComLoads[tid]++;
1374         }
1375     }
1376
1377     if (inst->isMemBarrier()) {
1378         statComMembars[tid]++;
1379     }
1380
1381     // Integer Instruction
1382     if (inst->isInteger())
1383         statComInteger[tid]++;
1384
1385     // Floating Point Instruction
1386     if (inst->isFloating())
1387         statComFloating[tid]++;
1388
1389     // Function Calls
1390     if (inst->isCall())
1391         statComFunctionCalls[tid]++;
1392
1393 }
1394
1395 ////////////////////////////////////////
1396 //                                    //
1397 //  SMT COMMIT POLICY MAINTAINED HERE //
1398 //                                    //
1399 ////////////////////////////////////////
1400 template <class Impl>
1401 ThreadID
1402 DefaultCommit<Impl>::getCommittingThread()
1403 {
1404     if (numThreads > 1) {
1405         switch (commitPolicy) {
1406
1407           case Aggressive:
1408             //If Policy is Aggressive, commit will call
1409             //this function multiple times per
1410             //cycle
1411             return oldestReady();
1412
1413           case RoundRobin:
1414             return roundRobin();
1415
1416           case OldestReady:
1417             return oldestReady();
1418
1419           default:
1420             return InvalidThreadID;
1421         }
1422     } else {
1423         assert(!activeThreads->empty());
1424         ThreadID tid = activeThreads->front();
1425
1426         if (commitStatus[tid] == Running ||
1427             commitStatus[tid] == Idle ||
1428             commitStatus[tid] == FetchTrapPending) {
1429             return tid;
1430         } else {
1431             return InvalidThreadID;
1432         }
1433     }
1434 }
1435
1436 template<class Impl>
1437 ThreadID
1438 DefaultCommit<Impl>::roundRobin()
1439 {
1440     list<ThreadID>::iterator pri_iter = priority_list.begin();
1441     list<ThreadID>::iterator end      = priority_list.end();
1442
1443     while (pri_iter != end) {
1444         ThreadID tid = *pri_iter;
1445
1446         if (commitStatus[tid] == Running ||
1447             commitStatus[tid] == Idle ||
1448             commitStatus[tid] == FetchTrapPending) {
1449
1450             if (rob->isHeadReady(tid)) {
1451                 priority_list.erase(pri_iter);
1452                 priority_list.push_back(tid);
1453
1454                 return tid;
1455             }
1456         }
1457
1458         pri_iter++;
1459     }
1460
1461     return InvalidThreadID;
1462 }
1463
1464 template<class Impl>
1465 ThreadID
1466 DefaultCommit<Impl>::oldestReady()
1467 {
1468     unsigned oldest = 0;
1469     bool first = true;
1470
1471     list<ThreadID>::iterator threads = activeThreads->begin();
1472     list<ThreadID>::iterator end = activeThreads->end();
1473
1474     while (threads != end) {
1475         ThreadID tid = *threads++;
1476
1477         if (!rob->isEmpty(tid) &&
1478             (commitStatus[tid] == Running ||
1479              commitStatus[tid] == Idle ||
1480              commitStatus[tid] == FetchTrapPending)) {
1481
1482             if (rob->isHeadReady(tid)) {
1483
1484                 DynInstPtr head_inst = rob->readHeadInst(tid);
1485
1486                 if (first) {
1487                     oldest = tid;
1488                     first = false;
1489                 } else if (head_inst->seqNum < oldest) {
1490                     oldest = tid;
1491                 }
1492             }
1493         }
1494     }
1495
1496     if (!first) {
1497         return oldest;
1498     } else {
1499         return InvalidThreadID;
1500     }
1501 }