src/cpu/o3/commit_impl.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <algorithm>
  45 #include <string>
  46
  47 #include "arch/utility.hh"
  48 #include "base/loader/symtab.hh"
  49 #include "base/cp_annotate.hh"
  50 #include "config/the_isa.hh"
  51 #include "config/use_checker.hh"
  52 #include "cpu/o3/commit.hh"
  53 #include "cpu/o3/thread_state.hh"
  54 #include "cpu/base.hh"
  55 #include "cpu/exetrace.hh"
  56 #include "cpu/timebuf.hh"
  57 #include "debug/Activity.hh"
  58 #include "debug/Commit.hh"
  59 #include "debug/CommitRate.hh"
  60 #include "debug/ExecFaulting.hh"
  61 #include "debug/O3PipeView.hh"
  62 #include "params/DerivO3CPU.hh"
  63 #include "sim/faults.hh"
  64 #include "sim/full_system.hh"
  65
  66 #if USE_CHECKER
  67 #include "cpu/checker/cpu.hh"
  68 #endif
  69
  70 using namespace std;
  71
  72 template <class Impl>
  73 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
  74                                           ThreadID _tid)
  75     : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
  76 {
  77 }
  78
  79 template <class Impl>
  80 void
  81 DefaultCommit<Impl>::TrapEvent::process()
  82 {
  83     // This will get reset by commit if it was switched out at the
  84     // time of this event processing.
  85     commit->trapSquash[tid] = true;
  86 }
  87
  88 template <class Impl>
  89 const char *
  90 DefaultCommit<Impl>::TrapEvent::description() const
  91 {
  92     return "Trap";
  93 }
  94
  95 template <class Impl>
  96 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
  97     : cpu(_cpu),
  98       squashCounter(0),
  99       iewToCommitDelay(params->iewToCommitDelay),
 100       commitToIEWDelay(params->commitToIEWDelay),
 101       renameToROBDelay(params->renameToROBDelay),
 102       fetchToCommitDelay(params->commitToFetchDelay),
 103       renameWidth(params->renameWidth),
 104       commitWidth(params->commitWidth),
 105       numThreads(params->numThreads),
 106       drainPending(false),
 107       switchedOut(false),
 108       trapLatency(params->trapLatency)
 109 {
 110     _status = Active;
 111     _nextStatus = Inactive;
 112     std::string policy = params->smtCommitPolicy;
 113
 114     //Convert string to lowercase
 115     std::transform(policy.begin(), policy.end(), policy.begin(),
 116                    (int(*)(int)) tolower);
 117
 118     //Assign commit policy
 119     if (policy == "aggressive"){
 120         commitPolicy = Aggressive;
 121
 122         DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
 123     } else if (policy == "roundrobin"){
 124         commitPolicy = RoundRobin;
 125
 126         //Set-Up Priority List
 127         for (ThreadID tid = 0; tid < numThreads; tid++) {
 128             priority_list.push_back(tid);
 129         }
 130
 131         DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
 132     } else if (policy == "oldestready"){
 133         commitPolicy = OldestReady;
 134
 135         DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
 136     } else {
 137         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
 138                "RoundRobin,OldestReady}");
 139     }
 140
 141     for (ThreadID tid = 0; tid < numThreads; tid++) {
 142         commitStatus[tid] = Idle;
 143         changedROBNumEntries[tid] = false;
 144         checkEmptyROB[tid] = false;
 145         trapInFlight[tid] = false;
 146         committedStores[tid] = false;
 147         trapSquash[tid] = false;
 148         tcSquash[tid] = false;
 149         pc[tid].set(0);
 150         lastCommitedSeqNum[tid] = 0;
 151     }
 152     interrupt = NoFault;
 153 }
 154
 155 template <class Impl>
 156 std::string
 157 DefaultCommit<Impl>::name() const
 158 {
 159     return cpu->name() + ".commit";
 160 }
 161
 162 template <class Impl>
 163 void
 164 DefaultCommit<Impl>::regStats()
 165 {
 166     using namespace Stats;
 167     commitCommittedInsts
 168         .name(name() + ".commitCommittedInsts")
 169         .desc("The number of committed instructions")
 170         .prereq(commitCommittedInsts);
 171     commitSquashedInsts
 172         .name(name() + ".commitSquashedInsts")
 173         .desc("The number of squashed insts skipped by commit")
 174         .prereq(commitSquashedInsts);
 175     commitSquashEvents
 176         .name(name() + ".commitSquashEvents")
 177         .desc("The number of times commit is told to squash")
 178         .prereq(commitSquashEvents);
 179     commitNonSpecStalls
 180         .name(name() + ".commitNonSpecStalls")
 181         .desc("The number of times commit has been forced to stall to "
 182               "communicate backwards")
 183         .prereq(commitNonSpecStalls);
 184     branchMispredicts
 185         .name(name() + ".branchMispredicts")
 186         .desc("The number of times a branch was mispredicted")
 187         .prereq(branchMispredicts);
 188     numCommittedDist
 189         .init(0,commitWidth,1)
 190         .name(name() + ".committed_per_cycle")
 191         .desc("Number of insts commited each cycle")
 192         .flags(Stats::pdf)
 193         ;
 194
 195     statComInst
 196         .init(cpu->numThreads)
 197         .name(name() + ".count")
 198         .desc("Number of instructions committed")
 199         .flags(total)
 200         ;
 201
 202     statComSwp
 203         .init(cpu->numThreads)
 204         .name(name() + ".swp_count")
 205         .desc("Number of s/w prefetches committed")
 206         .flags(total)
 207         ;
 208
 209     statComRefs
 210         .init(cpu->numThreads)
 211         .name(name() +  ".refs")
 212         .desc("Number of memory references committed")
 213         .flags(total)
 214         ;
 215
 216     statComLoads
 217         .init(cpu->numThreads)
 218         .name(name() +  ".loads")
 219         .desc("Number of loads committed")
 220         .flags(total)
 221         ;
 222
 223     statComMembars
 224         .init(cpu->numThreads)
 225         .name(name() +  ".membars")
 226         .desc("Number of memory barriers committed")
 227         .flags(total)
 228         ;
 229
 230     statComBranches
 231         .init(cpu->numThreads)
 232         .name(name() + ".branches")
 233         .desc("Number of branches committed")
 234         .flags(total)
 235         ;
 236
 237     statComFloating
 238         .init(cpu->numThreads)
 239         .name(name() + ".fp_insts")
 240         .desc("Number of committed floating point instructions.")
 241         .flags(total)
 242         ;
 243
 244     statComInteger
 245         .init(cpu->numThreads)
 246         .name(name()+".int_insts")
 247         .desc("Number of committed integer instructions.")
 248         .flags(total)
 249         ;
 250
 251     statComFunctionCalls
 252         .init(cpu->numThreads)
 253         .name(name()+".function_calls")
 254         .desc("Number of function calls committed.")
 255         .flags(total)
 256         ;
 257
 258     commitEligible
 259         .init(cpu->numThreads)
 260         .name(name() + ".bw_limited")
 261         .desc("number of insts not committed due to BW limits")
 262         .flags(total)
 263         ;
 264
 265     commitEligibleSamples
 266         .name(name() + ".bw_lim_events")
 267         .desc("number cycles where commit BW limit reached")
 268         ;
 269 }
 270
 271 template <class Impl>
 272 void
 273 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 274 {
 275     thread = threads;
 276 }
 277
 278 template <class Impl>
 279 void
 280 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 281 {
 282     timeBuffer = tb_ptr;
 283
 284     // Setup wire to send information back to IEW.
 285     toIEW = timeBuffer->getWire(0);
 286
 287     // Setup wire to read data from IEW (for the ROB).
 288     robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
 289 }
 290
 291 template <class Impl>
 292 void
 293 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 294 {
 295     fetchQueue = fq_ptr;
 296
 297     // Setup wire to get instructions from rename (for the ROB).
 298     fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
 299 }
 300
 301 template <class Impl>
 302 void
 303 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 304 {
 305     renameQueue = rq_ptr;
 306
 307     // Setup wire to get instructions from rename (for the ROB).
 308     fromRename = renameQueue->getWire(-renameToROBDelay);
 309 }
 310
 311 template <class Impl>
 312 void
 313 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 314 {
 315     iewQueue = iq_ptr;
 316
 317     // Setup wire to get instructions from IEW.
 318     fromIEW = iewQueue->getWire(-iewToCommitDelay);
 319 }
 320
 321 template <class Impl>
 322 void
 323 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
 324 {
 325     iewStage = iew_stage;
 326 }
 327
 328 template<class Impl>
 329 void
 330 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 331 {
 332     activeThreads = at_ptr;
 333 }
 334
 335 template <class Impl>
 336 void
 337 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
 338 {
 339     for (ThreadID tid = 0; tid < numThreads; tid++)
 340         renameMap[tid] = &rm_ptr[tid];
 341 }
 342
 343 template <class Impl>
 344 void
 345 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 346 {
 347     rob = rob_ptr;
 348 }
 349
 350 template <class Impl>
 351 void
 352 DefaultCommit<Impl>::initStage()
 353 {
 354     rob->setActiveThreads(activeThreads);
 355     rob->resetEntries();
 356
 357     // Broadcast the number of free entries.
 358     for (ThreadID tid = 0; tid < numThreads; tid++) {
 359         toIEW->commitInfo[tid].usedROB = true;
 360         toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 361         toIEW->commitInfo[tid].emptyROB = true;
 362     }
 363
 364     // Commit must broadcast the number of free entries it has at the
 365     // start of the simulation, so it starts as active.
 366     cpu->activateStage(O3CPU::CommitIdx);
 367
 368     cpu->activityThisCycle();
 369     trapLatency = cpu->ticks(trapLatency);
 370 }
 371
 372 template <class Impl>
 373 bool
 374 DefaultCommit<Impl>::drain()
 375 {
 376     drainPending = true;
 377
 378     return false;
 379 }
 380
 381 template <class Impl>
 382 void
 383 DefaultCommit<Impl>::switchOut()
 384 {
 385     switchedOut = true;
 386     drainPending = false;
 387     rob->switchOut();
 388 }
 389
 390 template <class Impl>
 391 void
 392 DefaultCommit<Impl>::resume()
 393 {
 394     drainPending = false;
 395 }
 396
 397 template <class Impl>
 398 void
 399 DefaultCommit<Impl>::takeOverFrom()
 400 {
 401     switchedOut = false;
 402     _status = Active;
 403     _nextStatus = Inactive;
 404     for (ThreadID tid = 0; tid < numThreads; tid++) {
 405         commitStatus[tid] = Idle;
 406         changedROBNumEntries[tid] = false;
 407         trapSquash[tid] = false;
 408         tcSquash[tid] = false;
 409     }
 410     squashCounter = 0;
 411     rob->takeOverFrom();
 412 }
 413
 414 template <class Impl>
 415 void
 416 DefaultCommit<Impl>::updateStatus()
 417 {
 418     // reset ROB changed variable
 419     list<ThreadID>::iterator threads = activeThreads->begin();
 420     list<ThreadID>::iterator end = activeThreads->end();
 421
 422     while (threads != end) {
 423         ThreadID tid = *threads++;
 424
 425         changedROBNumEntries[tid] = false;
 426
 427         // Also check if any of the threads has a trap pending
 428         if (commitStatus[tid] == TrapPending ||
 429             commitStatus[tid] == FetchTrapPending) {
 430             _nextStatus = Active;
 431         }
 432     }
 433
 434     if (_nextStatus == Inactive && _status == Active) {
 435         DPRINTF(Activity, "Deactivating stage.\n");
 436         cpu->deactivateStage(O3CPU::CommitIdx);
 437     } else if (_nextStatus == Active && _status == Inactive) {
 438         DPRINTF(Activity, "Activating stage.\n");
 439         cpu->activateStage(O3CPU::CommitIdx);
 440     }
 441
 442     _status = _nextStatus;
 443 }
 444
 445 template <class Impl>
 446 void
 447 DefaultCommit<Impl>::setNextStatus()
 448 {
 449     int squashes = 0;
 450
 451     list<ThreadID>::iterator threads = activeThreads->begin();
 452     list<ThreadID>::iterator end = activeThreads->end();
 453
 454     while (threads != end) {
 455         ThreadID tid = *threads++;
 456
 457         if (commitStatus[tid] == ROBSquashing) {
 458             squashes++;
 459         }
 460     }
 461
 462     squashCounter = squashes;
 463
 464     // If commit is currently squashing, then it will have activity for the
 465     // next cycle. Set its next status as active.
 466     if (squashCounter) {
 467         _nextStatus = Active;
 468     }
 469 }
 470
 471 template <class Impl>
 472 bool
 473 DefaultCommit<Impl>::changedROBEntries()
 474 {
 475     list<ThreadID>::iterator threads = activeThreads->begin();
 476     list<ThreadID>::iterator end = activeThreads->end();
 477
 478     while (threads != end) {
 479         ThreadID tid = *threads++;
 480
 481         if (changedROBNumEntries[tid]) {
 482             return true;
 483         }
 484     }
 485
 486     return false;
 487 }
 488
 489 template <class Impl>
 490 size_t
 491 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
 492 {
 493     return rob->numFreeEntries(tid);
 494 }
 495
 496 template <class Impl>
 497 void
 498 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
 499 {
 500     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
 501
 502     TrapEvent *trap = new TrapEvent(this, tid);
 503
 504     cpu->schedule(trap, curTick() + trapLatency);
 505     trapInFlight[tid] = true;
 506     thread[tid]->trapPending = true;
 507 }
 508
 509 template <class Impl>
 510 void
 511 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
 512 {
 513     assert(!trapInFlight[tid]);
 514     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 515
 516     tcSquash[tid] = true;
 517 }
 518
 519 template <class Impl>
 520 void
 521 DefaultCommit<Impl>::squashAll(ThreadID tid)
 522 {
 523     // If we want to include the squashing instruction in the squash,
 524     // then use one older sequence number.
 525     // Hopefully this doesn't mess things up.  Basically I want to squash
 526     // all instructions of this thread.
 527     InstSeqNum squashed_inst = rob->isEmpty() ?
 528         lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
 529
 530     // All younger instructions will be squashed. Set the sequence
 531     // number as the youngest instruction in the ROB (0 in this case.
 532     // Hopefully nothing breaks.)
 533     youngestSeqNum[tid] = lastCommitedSeqNum[tid];
 534
 535     rob->squash(squashed_inst, tid);
 536     changedROBNumEntries[tid] = true;
 537
 538     // Send back the sequence number of the squashed instruction.
 539     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 540
 541     // Send back the squash signal to tell stages that they should
 542     // squash.
 543     toIEW->commitInfo[tid].squash = true;
 544
 545     // Send back the rob squashing signal so other stages know that
 546     // the ROB is in the process of squashing.
 547     toIEW->commitInfo[tid].robSquashing = true;
 548
 549     toIEW->commitInfo[tid].mispredictInst = NULL;
 550     toIEW->commitInfo[tid].squashInst = NULL;
 551
 552     toIEW->commitInfo[tid].pc = pc[tid];
 553 }
 554
 555 template <class Impl>
 556 void
 557 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
 558 {
 559     squashAll(tid);
 560
 561     DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
 562
 563     thread[tid]->trapPending = false;
 564     thread[tid]->inSyscall = false;
 565     trapInFlight[tid] = false;
 566
 567     trapSquash[tid] = false;
 568
 569     commitStatus[tid] = ROBSquashing;
 570     cpu->activityThisCycle();
 571 }
 572
 573 template <class Impl>
 574 void
 575 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
 576 {
 577     squashAll(tid);
 578
 579     DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
 580
 581     thread[tid]->inSyscall = false;
 582     assert(!thread[tid]->trapPending);
 583
 584     commitStatus[tid] = ROBSquashing;
 585     cpu->activityThisCycle();
 586
 587     tcSquash[tid] = false;
 588 }
 589
 590 template <class Impl>
 591 void
 592 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
 593         uint64_t squash_after_seq_num)
 594 {
 595     youngestSeqNum[tid] = squash_after_seq_num;
 596
 597     rob->squash(squash_after_seq_num, tid);
 598     changedROBNumEntries[tid] = true;
 599
 600     // Send back the sequence number of the squashed instruction.
 601     toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
 602
 603     toIEW->commitInfo[tid].squashInst = head_inst;
 604     // Send back the squash signal to tell stages that they should squash.
 605     toIEW->commitInfo[tid].squash = true;
 606
 607     // Send back the rob squashing signal so other stages know that
 608     // the ROB is in the process of squashing.
 609     toIEW->commitInfo[tid].robSquashing = true;
 610
 611     toIEW->commitInfo[tid].mispredictInst = NULL;
 612
 613     toIEW->commitInfo[tid].pc = pc[tid];
 614     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
 615             tid, squash_after_seq_num);
 616     commitStatus[tid] = ROBSquashing;
 617 }
 618
 619 template <class Impl>
 620 void
 621 DefaultCommit<Impl>::tick()
 622 {
 623     wroteToTimeBuffer = false;
 624     _nextStatus = Inactive;
 625
 626     if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
 627         cpu->signalDrained();
 628         drainPending = false;
 629         return;
 630     }
 631
 632     if (activeThreads->empty())
 633         return;
 634
 635     list<ThreadID>::iterator threads = activeThreads->begin();
 636     list<ThreadID>::iterator end = activeThreads->end();
 637
 638     // Check if any of the threads are done squashing.  Change the
 639     // status if they are done.
 640     while (threads != end) {
 641         ThreadID tid = *threads++;
 642
 643         // Clear the bit saying if the thread has committed stores
 644         // this cycle.
 645         committedStores[tid] = false;
 646
 647         if (commitStatus[tid] == ROBSquashing) {
 648
 649             if (rob->isDoneSquashing(tid)) {
 650                 commitStatus[tid] = Running;
 651             } else {
 652                 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
 653                         " insts this cycle.\n", tid);
 654                 rob->doSquash(tid);
 655                 toIEW->commitInfo[tid].robSquashing = true;
 656                 wroteToTimeBuffer = true;
 657             }
 658         }
 659     }
 660
 661     commit();
 662
 663     markCompletedInsts();
 664
 665     threads = activeThreads->begin();
 666
 667     while (threads != end) {
 668         ThreadID tid = *threads++;
 669
 670         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
 671             // The ROB has more instructions it can commit. Its next status
 672             // will be active.
 673             _nextStatus = Active;
 674
 675             DynInstPtr inst = rob->readHeadInst(tid);
 676
 677             DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
 678                     " ROB and ready to commit\n",
 679                     tid, inst->seqNum, inst->pcState());
 680
 681         } else if (!rob->isEmpty(tid)) {
 682             DynInstPtr inst = rob->readHeadInst(tid);
 683
 684             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
 685                     "%s is head of ROB and not ready\n",
 686                     tid, inst->seqNum, inst->pcState());
 687         }
 688
 689         DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
 690                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
 691     }
 692
 693
 694     if (wroteToTimeBuffer) {
 695         DPRINTF(Activity, "Activity This Cycle.\n");
 696         cpu->activityThisCycle();
 697     }
 698
 699     updateStatus();
 700 }
 701
 702 template <class Impl>
 703 void
 704 DefaultCommit<Impl>::handleInterrupt()
 705 {
 706     // Verify that we still have an interrupt to handle
 707     if (!cpu->checkInterrupts(cpu->tcBase(0))) {
 708         DPRINTF(Commit, "Pending interrupt is cleared by master before "
 709                 "it got handled. Restart fetching from the orig path.\n");
 710         toIEW->commitInfo[0].clearInterrupt = true;
 711         interrupt = NoFault;
 712         return;
 713     }
 714
 715     // Wait until all in flight instructions are finished before enterring
 716     // the interrupt.
 717     if (cpu->instList.empty()) {
 718         // Squash or record that I need to squash this cycle if
 719         // an interrupt needed to be handled.
 720         DPRINTF(Commit, "Interrupt detected.\n");
 721
 722         // Clear the interrupt now that it's going to be handled
 723         toIEW->commitInfo[0].clearInterrupt = true;
 724
 725         assert(!thread[0]->inSyscall);
 726         thread[0]->inSyscall = true;
 727
 728         // CPU will handle interrupt.
 729         cpu->processInterrupts(interrupt);
 730
 731         thread[0]->inSyscall = false;
 732
 733         commitStatus[0] = TrapPending;
 734
 735         // Generate trap squash event.
 736         generateTrapEvent(0);
 737
 738         interrupt = NoFault;
 739     } else {
 740         DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
 741     }
 742 }
 743
 744 template <class Impl>
 745 void
 746 DefaultCommit<Impl>::propagateInterrupt()
 747 {
 748     if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
 749             tcSquash[0])
 750         return;
 751
 752     // Process interrupts if interrupts are enabled, not in PAL
 753     // mode, and no other traps or external squashes are currently
 754     // pending.
 755     // @todo: Allow other threads to handle interrupts.
 756
 757     // Get any interrupt that happened
 758     interrupt = cpu->getInterrupts();
 759
 760     // Tell fetch that there is an interrupt pending.  This
 761     // will make fetch wait until it sees a non PAL-mode PC,
 762     // at which point it stops fetching instructions.
 763     if (interrupt != NoFault)
 764         toIEW->commitInfo[0].interruptPending = true;
 765 }
 766
 767 template <class Impl>
 768 void
 769 DefaultCommit<Impl>::commit()
 770 {
 771     if (FullSystem) {
 772         // Check for any interrupt that we've already squashed for and start
 773         // processing it.
 774         if (interrupt != NoFault)
 775             handleInterrupt();
 776
 777         // Check if we have a interrupt and get read to handle it
 778         if (cpu->checkInterrupts(cpu->tcBase(0)))
 779             propagateInterrupt();
 780     }
 781
 782     ////////////////////////////////////
 783     // Check for any possible squashes, handle them first
 784     ////////////////////////////////////
 785     list<ThreadID>::iterator threads = activeThreads->begin();
 786     list<ThreadID>::iterator end = activeThreads->end();
 787
 788     while (threads != end) {
 789         ThreadID tid = *threads++;
 790
 791         // Not sure which one takes priority.  I think if we have
 792         // both, that's a bad sign.
 793         if (trapSquash[tid] == true) {
 794             assert(!tcSquash[tid]);
 795             squashFromTrap(tid);
 796         } else if (tcSquash[tid] == true) {
 797             assert(commitStatus[tid] != TrapPending);
 798             squashFromTC(tid);
 799         }
 800
 801         // Squashed sequence number must be older than youngest valid
 802         // instruction in the ROB. This prevents squashes from younger
 803         // instructions overriding squashes from older instructions.
 804         if (fromIEW->squash[tid] &&
 805             commitStatus[tid] != TrapPending &&
 806             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 807
 808             if (fromIEW->mispredictInst[tid]) {
 809                 DPRINTF(Commit,
 810                     "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
 811                     tid,
 812                     fromIEW->mispredictInst[tid]->instAddr(),
 813                     fromIEW->squashedSeqNum[tid]);
 814             } else {
 815                 DPRINTF(Commit,
 816                     "[tid:%i]: Squashing due to order violation [sn:%i]\n",
 817                     tid, fromIEW->squashedSeqNum[tid]);
 818             }
 819
 820             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
 821                     tid,
 822                     fromIEW->pc[tid].nextInstAddr());
 823
 824             commitStatus[tid] = ROBSquashing;
 825
 826             // If we want to include the squashing instruction in the squash,
 827             // then use one older sequence number.
 828             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 829
 830             if (fromIEW->includeSquashInst[tid] == true) {
 831                 squashed_inst--;
 832             }
 833
 834             // All younger instructions will be squashed. Set the sequence
 835             // number as the youngest instruction in the ROB.
 836             youngestSeqNum[tid] = squashed_inst;
 837
 838             rob->squash(squashed_inst, tid);
 839             changedROBNumEntries[tid] = true;
 840
 841             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 842
 843             toIEW->commitInfo[tid].squash = true;
 844
 845             // Send back the rob squashing signal so other stages know that
 846             // the ROB is in the process of squashing.
 847             toIEW->commitInfo[tid].robSquashing = true;
 848
 849             toIEW->commitInfo[tid].mispredictInst =
 850                 fromIEW->mispredictInst[tid];
 851             toIEW->commitInfo[tid].branchTaken =
 852                 fromIEW->branchTaken[tid];
 853             toIEW->commitInfo[tid].squashInst = NULL;
 854
 855             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 856
 857             if (toIEW->commitInfo[tid].mispredictInst) {
 858                 ++branchMispredicts;
 859             }
 860         }
 861
 862     }
 863
 864     setNextStatus();
 865
 866     if (squashCounter != numThreads) {
 867         // If we're not currently squashing, then get instructions.
 868         getInsts();
 869
 870         // Try to commit any instructions.
 871         commitInsts();
 872     }
 873
 874     //Check for any activity
 875     threads = activeThreads->begin();
 876
 877     while (threads != end) {
 878         ThreadID tid = *threads++;
 879
 880         if (changedROBNumEntries[tid]) {
 881             toIEW->commitInfo[tid].usedROB = true;
 882             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 883
 884             wroteToTimeBuffer = true;
 885             changedROBNumEntries[tid] = false;
 886             if (rob->isEmpty(tid))
 887                 checkEmptyROB[tid] = true;
 888         }
 889
 890         // ROB is only considered "empty" for previous stages if: a)
 891         // ROB is empty, b) there are no outstanding stores, c) IEW
 892         // stage has received any information regarding stores that
 893         // committed.
 894         // c) is checked by making sure to not consider the ROB empty
 895         // on the same cycle as when stores have been committed.
 896         // @todo: Make this handle multi-cycle communication between
 897         // commit and IEW.
 898         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
 899             !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
 900             checkEmptyROB[tid] = false;
 901             toIEW->commitInfo[tid].usedROB = true;
 902             toIEW->commitInfo[tid].emptyROB = true;
 903             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
 904             wroteToTimeBuffer = true;
 905         }
 906
 907     }
 908 }
 909
 910 template <class Impl>
 911 void
 912 DefaultCommit<Impl>::commitInsts()
 913 {
 914     ////////////////////////////////////
 915     // Handle commit
 916     // Note that commit will be handled prior to putting new
 917     // instructions in the ROB so that the ROB only tries to commit
 918     // instructions it has in this current cycle, and not instructions
 919     // it is writing in during this cycle.  Can't commit and squash
 920     // things at the same time...
 921     ////////////////////////////////////
 922
 923     DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 924
 925     unsigned num_committed = 0;
 926
 927     DynInstPtr head_inst;
 928
 929     // Commit as many instructions as possible until the commit bandwidth
 930     // limit is reached, or it becomes impossible to commit any more.
 931     while (num_committed < commitWidth) {
 932         int commit_thread = getCommittingThread();
 933
 934         if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
 935             break;
 936
 937         head_inst = rob->readHeadInst(commit_thread);
 938
 939         ThreadID tid = head_inst->threadNumber;
 940
 941         assert(tid == commit_thread);
 942
 943         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
 944                 head_inst->seqNum, tid);
 945
 946         // If the head instruction is squashed, it is ready to retire
 947         // (be removed from the ROB) at any time.
 948         if (head_inst->isSquashed()) {
 949
 950             DPRINTF(Commit, "Retiring squashed instruction from "
 951                     "ROB.\n");
 952
 953             rob->retireHead(commit_thread);
 954
 955             ++commitSquashedInsts;
 956
 957             // Record that the number of ROB entries has changed.
 958             changedROBNumEntries[tid] = true;
 959         } else {
 960             pc[tid] = head_inst->pcState();
 961
 962             // Increment the total number of non-speculative instructions
 963             // executed.
 964             // Hack for now: it really shouldn't happen until after the
 965             // commit is deemed to be successful, but this count is needed
 966             // for syscalls.
 967             thread[tid]->funcExeInst++;
 968
 969             // Try to commit the head instruction.
 970             bool commit_success = commitHead(head_inst, num_committed);
 971
 972             if (commit_success) {
 973                 ++num_committed;
 974
 975                 changedROBNumEntries[tid] = true;
 976
 977                 // Set the doneSeqNum to the youngest committed instruction.
 978                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 979
 980                 ++commitCommittedInsts;
 981
 982                 // To match the old model, don't count nops and instruction
 983                 // prefetches towards the total commit count.
 984                 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
 985                     cpu->instDone(tid);
 986                 }
 987
 988                 // Updates misc. registers.
 989                 head_inst->updateMiscRegs();
 990
 991                 cpu->traceFunctions(pc[tid].instAddr());
 992
 993                 TheISA::advancePC(pc[tid], head_inst->staticInst);
 994
 995                 // Keep track of the last sequence number commited
 996                 lastCommitedSeqNum[tid] = head_inst->seqNum;
 997
 998                 // If this is an instruction that doesn't play nicely with
 999                 // others squash everything and restart fetch
1000                 if (head_inst->isSquashAfter())
1001                     squashAfter(tid, head_inst, head_inst->seqNum);
1002
1003                 int count = 0;
1004                 Addr oldpc;
1005                 // Debug statement.  Checks to make sure we're not
1006                 // currently updating state while handling PC events.
1007                 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1008                 do {
1009                     oldpc = pc[tid].instAddr();
1010                     cpu->system->pcEventQueue.service(thread[tid]->getTC());
1011                     count++;
1012                 } while (oldpc != pc[tid].instAddr());
1013                 if (count > 1) {
1014                     DPRINTF(Commit,
1015                             "PC skip function event, stopping commit\n");
1016                     break;
1017                 }
1018             } else {
1019                 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1020                         "[tid:%i] [sn:%i].\n",
1021                         head_inst->pcState(), tid ,head_inst->seqNum);
1022                 break;
1023             }
1024         }
1025     }
1026
1027     DPRINTF(CommitRate, "%i\n", num_committed);
1028     numCommittedDist.sample(num_committed);
1029
1030     if (num_committed == commitWidth) {
1031         commitEligibleSamples++;
1032     }
1033 }
1034
1035 template <class Impl>
1036 bool
1037 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1038 {
1039     assert(head_inst);
1040
1041     ThreadID tid = head_inst->threadNumber;
1042
1043     // If the instruction is not executed yet, then it will need extra
1044     // handling.  Signal backwards that it should be executed.
1045     if (!head_inst->isExecuted()) {
1046         // Keep this number correct.  We have not yet actually executed
1047         // and committed this instruction.
1048         thread[tid]->funcExeInst--;
1049
1050         if (head_inst->isNonSpeculative() ||
1051             head_inst->isStoreConditional() ||
1052             head_inst->isMemBarrier() ||
1053             head_inst->isWriteBarrier()) {
1054
1055             DPRINTF(Commit, "Encountered a barrier or non-speculative "
1056                     "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1057                     head_inst->seqNum, head_inst->pcState());
1058
1059             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1060                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1061                 return false;
1062             }
1063
1064             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1065
1066             // Change the instruction so it won't try to commit again until
1067             // it is executed.
1068             head_inst->clearCanCommit();
1069
1070             ++commitNonSpecStalls;
1071
1072             return false;
1073         } else if (head_inst->isLoad()) {
1074             if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1075                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1076                 return false;
1077             }
1078
1079             assert(head_inst->uncacheable());
1080             DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1081                     head_inst->seqNum, head_inst->pcState());
1082
1083             // Send back the non-speculative instruction's sequence
1084             // number.  Tell the lsq to re-execute the load.
1085             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1086             toIEW->commitInfo[tid].uncached = true;
1087             toIEW->commitInfo[tid].uncachedLoad = head_inst;
1088
1089             head_inst->clearCanCommit();
1090
1091             return false;
1092         } else {
1093             panic("Trying to commit un-executed instruction "
1094                   "of unknown type!\n");
1095         }
1096     }
1097
1098     if (head_inst->isThreadSync()) {
1099         // Not handled for now.
1100         panic("Thread sync instructions are not handled yet.\n");
1101     }
1102
1103     // Check if the instruction caused a fault.  If so, trap.
1104     Fault inst_fault = head_inst->getFault();
1105
1106     // Stores mark themselves as completed.
1107     if (!head_inst->isStore() && inst_fault == NoFault) {
1108         head_inst->setCompleted();
1109     }
1110
1111 #if USE_CHECKER
1112     // Use checker prior to updating anything due to traps or PC
1113     // based events.
1114     if (cpu->checker) {
1115         cpu->checker->verify(head_inst);
1116     }
1117 #endif
1118
1119     if (inst_fault != NoFault) {
1120         DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1121                 head_inst->seqNum, head_inst->pcState());
1122
1123         if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1124             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1125             return false;
1126         }
1127
1128         head_inst->setCompleted();
1129
1130 #if USE_CHECKER
1131         if (cpu->checker && head_inst->isStore()) {
1132             cpu->checker->verify(head_inst);
1133         }
1134 #endif
1135
1136         assert(!thread[tid]->inSyscall);
1137
1138         // Mark that we're in state update mode so that the trap's
1139         // execution doesn't generate extra squashes.
1140         thread[tid]->inSyscall = true;
1141
1142         // Execute the trap.  Although it's slightly unrealistic in
1143         // terms of timing (as it doesn't wait for the full timing of
1144         // the trap event to complete before updating state), it's
1145         // needed to update the state as soon as possible.  This
1146         // prevents external agents from changing any specific state
1147         // that the trap need.
1148         cpu->trap(inst_fault, tid, head_inst->staticInst);
1149
1150         // Exit state update mode to avoid accidental updating.
1151         thread[tid]->inSyscall = false;
1152
1153         commitStatus[tid] = TrapPending;
1154
1155         DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1156             head_inst->seqNum);
1157         if (head_inst->traceData) {
1158             if (DTRACE(ExecFaulting)) {
1159                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1160                 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1161                 head_inst->traceData->dump();
1162             }
1163             delete head_inst->traceData;
1164             head_inst->traceData = NULL;
1165         }
1166
1167         // Generate trap squash event.
1168         generateTrapEvent(tid);
1169         return false;
1170     }
1171
1172     updateComInstStats(head_inst);
1173
1174     if (FullSystem) {
1175         if (thread[tid]->profile) {
1176             thread[tid]->profilePC = head_inst->instAddr();
1177             ProfileNode *node = thread[tid]->profile->consume(
1178                     thread[tid]->getTC(), head_inst->staticInst);
1179
1180             if (node)
1181                 thread[tid]->profileNode = node;
1182         }
1183         if (CPA::available()) {
1184             if (head_inst->isControl()) {
1185                 ThreadContext *tc = thread[tid]->getTC();
1186                 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1187             }
1188         }
1189     }
1190     DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1191             head_inst->seqNum, head_inst->pcState());
1192     if (head_inst->traceData) {
1193         head_inst->traceData->setFetchSeq(head_inst->seqNum);
1194         head_inst->traceData->setCPSeq(thread[tid]->numInst);
1195         head_inst->traceData->dump();
1196         delete head_inst->traceData;
1197         head_inst->traceData = NULL;
1198     }
1199
1200     // Update the commit rename map
1201     for (int i = 0; i < head_inst->numDestRegs(); i++) {
1202         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1203                                  head_inst->renamedDestRegIdx(i));
1204     }
1205
1206     // Finally clear the head ROB entry.
1207     rob->retireHead(tid);
1208
1209 #if TRACING_ON
1210     // Print info needed by the pipeline activity viewer.
1211     DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1212              head_inst->fetchTick,
1213              head_inst->instAddr(),
1214              head_inst->microPC(),
1215              head_inst->seqNum,
1216              head_inst->staticInst->disassemble(head_inst->instAddr()));
1217     DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1218     DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1219     DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1220     DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1221     DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1222     DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1223 #endif
1224
1225     // If this was a store, record it for this cycle.
1226     if (head_inst->isStore())
1227         committedStores[tid] = true;
1228
1229     // Return true to indicate that we have committed an instruction.
1230     return true;
1231 }
1232
1233 template <class Impl>
1234 void
1235 DefaultCommit<Impl>::getInsts()
1236 {
1237     DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1238
1239     // Read any renamed instructions and place them into the ROB.
1240     int insts_to_process = std::min((int)renameWidth, fromRename->size);
1241
1242     for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1243         DynInstPtr inst;
1244
1245         inst = fromRename->insts[inst_num];
1246         ThreadID tid = inst->threadNumber;
1247
1248         if (!inst->isSquashed() &&
1249             commitStatus[tid] != ROBSquashing &&
1250             commitStatus[tid] != TrapPending) {
1251             changedROBNumEntries[tid] = true;
1252
1253             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1254                     inst->pcState(), inst->seqNum, tid);
1255
1256             rob->insertInst(inst);
1257
1258             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1259
1260             youngestSeqNum[tid] = inst->seqNum;
1261         } else {
1262             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1263                     "squashed, skipping.\n",
1264                     inst->pcState(), inst->seqNum, tid);
1265         }
1266     }
1267 }
1268
1269 template <class Impl>
1270 void
1271 DefaultCommit<Impl>::skidInsert()
1272 {
1273     DPRINTF(Commit, "Attempting to any instructions from rename into "
1274             "skidBuffer.\n");
1275
1276     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1277         DynInstPtr inst = fromRename->insts[inst_num];
1278
1279         if (!inst->isSquashed()) {
1280             DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1281                     "skidBuffer.\n", inst->pcState(), inst->seqNum,
1282                     inst->threadNumber);
1283             skidBuffer.push(inst);
1284         } else {
1285             DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1286                     "squashed, skipping.\n",
1287                     inst->pcState(), inst->seqNum, inst->threadNumber);
1288         }
1289     }
1290 }
1291
1292 template <class Impl>
1293 void
1294 DefaultCommit<Impl>::markCompletedInsts()
1295 {
1296     // Grab completed insts out of the IEW instruction queue, and mark
1297     // instructions completed within the ROB.
1298     for (int inst_num = 0;
1299          inst_num < fromIEW->size && fromIEW->insts[inst_num];
1300          ++inst_num)
1301     {
1302         if (!fromIEW->insts[inst_num]->isSquashed()) {
1303             DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1304                     "within ROB.\n",
1305                     fromIEW->insts[inst_num]->threadNumber,
1306                     fromIEW->insts[inst_num]->pcState(),
1307                     fromIEW->insts[inst_num]->seqNum);
1308
1309             // Mark the instruction as ready to commit.
1310             fromIEW->insts[inst_num]->setCanCommit();
1311         }
1312     }
1313 }
1314
1315 template <class Impl>
1316 bool
1317 DefaultCommit<Impl>::robDoneSquashing()
1318 {
1319     list<ThreadID>::iterator threads = activeThreads->begin();
1320     list<ThreadID>::iterator end = activeThreads->end();
1321
1322     while (threads != end) {
1323         ThreadID tid = *threads++;
1324
1325         if (!rob->isDoneSquashing(tid))
1326             return false;
1327     }
1328
1329     return true;
1330 }
1331
1332 template <class Impl>
1333 void
1334 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1335 {
1336     ThreadID tid = inst->threadNumber;
1337
1338     //
1339     //  Pick off the software prefetches
1340     //
1341 #ifdef TARGET_ALPHA
1342     if (inst->isDataPrefetch()) {
1343         statComSwp[tid]++;
1344     } else {
1345         statComInst[tid]++;
1346     }
1347 #else
1348     statComInst[tid]++;
1349 #endif
1350
1351     //
1352     //  Control Instructions
1353     //
1354     if (inst->isControl())
1355         statComBranches[tid]++;
1356
1357     //
1358     //  Memory references
1359     //
1360     if (inst->isMemRef()) {
1361         statComRefs[tid]++;
1362
1363         if (inst->isLoad()) {
1364             statComLoads[tid]++;
1365         }
1366     }
1367
1368     if (inst->isMemBarrier()) {
1369         statComMembars[tid]++;
1370     }
1371
1372     // Integer Instruction
1373     if (inst->isInteger())
1374         statComInteger[tid]++;
1375
1376     // Floating Point Instruction
1377     if (inst->isFloating())
1378         statComFloating[tid]++;
1379
1380     // Function Calls
1381     if (inst->isCall())
1382         statComFunctionCalls[tid]++;
1383
1384 }
1385
1386 ////////////////////////////////////////
1387 //                                    //
1388 //  SMT COMMIT POLICY MAINTAINED HERE //
1389 //                                    //
1390 ////////////////////////////////////////
1391 template <class Impl>
1392 ThreadID
1393 DefaultCommit<Impl>::getCommittingThread()
1394 {
1395     if (numThreads > 1) {
1396         switch (commitPolicy) {
1397
1398           case Aggressive:
1399             //If Policy is Aggressive, commit will call
1400             //this function multiple times per
1401             //cycle
1402             return oldestReady();
1403
1404           case RoundRobin:
1405             return roundRobin();
1406
1407           case OldestReady:
1408             return oldestReady();
1409
1410           default:
1411             return InvalidThreadID;
1412         }
1413     } else {
1414         assert(!activeThreads->empty());
1415         ThreadID tid = activeThreads->front();
1416
1417         if (commitStatus[tid] == Running ||
1418             commitStatus[tid] == Idle ||
1419             commitStatus[tid] == FetchTrapPending) {
1420             return tid;
1421         } else {
1422             return InvalidThreadID;
1423         }
1424     }
1425 }
1426
1427 template<class Impl>
1428 ThreadID
1429 DefaultCommit<Impl>::roundRobin()
1430 {
1431     list<ThreadID>::iterator pri_iter = priority_list.begin();
1432     list<ThreadID>::iterator end      = priority_list.end();
1433
1434     while (pri_iter != end) {
1435         ThreadID tid = *pri_iter;
1436
1437         if (commitStatus[tid] == Running ||
1438             commitStatus[tid] == Idle ||
1439             commitStatus[tid] == FetchTrapPending) {
1440
1441             if (rob->isHeadReady(tid)) {
1442                 priority_list.erase(pri_iter);
1443                 priority_list.push_back(tid);
1444
1445                 return tid;
1446             }
1447         }
1448
1449         pri_iter++;
1450     }
1451
1452     return InvalidThreadID;
1453 }
1454
1455 template<class Impl>
1456 ThreadID
1457 DefaultCommit<Impl>::oldestReady()
1458 {
1459     unsigned oldest = 0;
1460     bool first = true;
1461
1462     list<ThreadID>::iterator threads = activeThreads->begin();
1463     list<ThreadID>::iterator end = activeThreads->end();
1464
1465     while (threads != end) {
1466         ThreadID tid = *threads++;
1467
1468         if (!rob->isEmpty(tid) &&
1469             (commitStatus[tid] == Running ||
1470              commitStatus[tid] == Idle ||
1471              commitStatus[tid] == FetchTrapPending)) {
1472
1473             if (rob->isHeadReady(tid)) {
1474
1475                 DynInstPtr head_inst = rob->readHeadInst(tid);
1476
1477                 if (first) {
1478                     oldest = tid;
1479                     first = false;
1480                 } else if (head_inst->seqNum < oldest) {
1481                     oldest = tid;
1482                 }
1483             }
1484         }
1485     }
1486
1487     if (!first) {
1488         return oldest;
1489     } else {
1490         return InvalidThreadID;
1491     }
1492 }